TW200945415A - Process sequence for formation of patterned hard mask film (RFP) without need for photoresist or dry etch - Google Patents

Abstract

Method and systems for patterning a hardmask film using ultraviolet light is disclosed according to one embodiment of the invention. Embodiments of the present invention alleviate the processing problem of depositing and etching photoresist in order to produce a hardmask pattern. A hardmask layer, such as, silicon oxide, is first deposited on a substrate within a deposition chamber. In some cases, the hardmask layer is baked or annealed following deposition. After which, portions of the hardmask layer are exposed with ultraviolet light. The ultraviolet light produces a pattern of exposed and unexposed portions of hardmask material. Following the exposure, an etching process, such as a wet etch, may occur that removes the unexposed portions of the hardmask. Following the etch, the hardmask may be annealed, baked or subjected to a plasma treatment.

Description

200945415 VI. Description of the Invention: Technical Field of the Invention The embodiments of the present invention generally relate to photolithography etching, and are not limited to resist free patterning (R_FP) photolithography #刻0 © [previously Technology] In general, photolithography is the process used to specifically remove a portion of a film during microfabrication. Typically, light is used to transfer the pattern on the reticle to a photosensitive chemical photoresist on the substrate. The exposure pattern is engraved into the material under the photoresist using a series of chemical treatments. In complex integrated circuits, wafers even require up to 50 photolithographic etch cycles. ❿ Traditional photolithography processing can include the following steps: preparation, application of photoresist, exposure, development, etching, and removal. The wafer is prepared by heating the wafer to a temperature sufficient to dissipate any moisture remaining on the surface of the wafer. The surface of the wafer that has been stored must first be chemically cleaned to remove any contaminants from the surface. Apply a liquid or gaseous adhesion promoter (such as 'hexamethyl disilazane (HMDS)) to help The photoresist adheres to the wafer. The 200945415 f resistance is then applied to the wafer surface by various deposition techniques such as spin coating, chemical vapor deposition, atomic layer deposition, physical vapor deposition, and the like. Next, the wafer coated with the photoresist is soft baked or pre-baked to disperse excess solvent. After prebaking, the photoresist is exposed to intense light. After exposure, the JL type photoresist will become opposite to W when it is reduced, and the 贞-type light will become more lively. Such chemical changes allow certain photoresists to be removed by the developing solution. Typically, post-exposure post-baking is performed to reduce the standing wave effect produced by defective or destructive interference. . Next, the wafer is hard baked. In some cases, this hard bake is at 120. (: to 180 it is carried out for about 2 to 3 minutes. This hard bake hardens the remaining photoresist to become a more resistant protective film for future ion implantation, wet etching or plasma etching. After hard baking, the wafer is left in a liquid (wet) or plasma chemistry that removes the uppermost layer of the substrate that is not protected by the protective film. Φ After etching, remove from the substrate Photoresist. A liquid photoresist stripper can be used to change the photoresist resistance so that it no longer adheres to the substrate. Alternatively, the photoresist can be removed by ashing (oxidation of the photoresist with an oxygen-containing plasma). Other techniques and/or improvements can be used in photolithographic etching systems. These conventional photolithographic etching processes are quite time consuming and cumbersome, and embodiments of the present invention focus on reducing the complexity of photolithographic etching systems. [Description of Requirements] 5 200945415 A method and system for patterning a hard mask film using ultraviolet light is disclosed according to an embodiment of the present invention. Embodiments of the present invention can reduce deposition and etching of photoresist for manufacturing a hard mask pattern. Time A problem will arise: a hard mask layer (eg, hafnium oxide) is first deposited on the substrate in the deposition chamber. In some cases, the hard mask layer is baked and annealed after deposition. After hardening, 卩 ultraviolet light (eg, light less than 348 nm) exposes a portion of the hard mask layer. The ultraviolet light causes an exposure pattern and an unexposed portion to appear on the hard mask material. After exposure, an etch process can be performed (eg, , including HF, NH4〇h, sci, rca wet etching) 'Removing the unexposed portion of the hard mask. After etching, the hard mask is annealed, baked or plasma treated. Annealing includes steam annealing , thermal annealing, inductively coupled plasma annealing, capacitively coupled plasma annealing, ultraviolet annealing, electron beam annealing (e-beam annealing), acid gas phase catalyst annealing, alkali vapor phase catalyst annealing, and microwave annealing. It is implemented in an inert gas atmosphere, for example, in a gas environment such as A, Ar, Ο:, Η", 仙3, n2/H2, and n2〇. In addition, plasma processing may include capacitively coupled plasma and inductively coupled plasma processing. "This plasma treatment can be The substrate can be implemented in n2, Ar, 〇2, h2 〇, NH3, Νζ/Η2, and the like. The substrate can include a ruthenium substrate, a ΠΙ ν family composite substrate, a ruthenium/iridium substrate, an epi-substrate, and an insulating layer. a substrate, a display substrate, a liquid crystal display substrate, a plasma display substrate, an electroluminescent lamp substrate, and a light-emitting diode substrate. Further, a place can be used, such as spin coating, chemical vapor deposition, Atomic layer deposition and physical vapor deposition) and one or more processes and/or steps in the deposition chamber. Other applications of the present disclosure will be more apparent from the detailed description provided below. The details and specific embodiments are merely illustrative of the invention, and the scope of the invention is not limited to the embodiments. [Embodiment] The following description provides only the preferred exemplary embodiments, and the combinations of the invention, the application, and the disclosure are not limited to these examples. The following description will enable those skilled in the art to implement the preferred embodiments of the present disclosure in accordance with the description, but it should be understood that various modifications may be made to the preferred embodiments without departing from the scope of the claimed invention. Change or modification. ® Embodiments of the invention include processes, methods, and apparatus for providing a patterned hard mask layer without the need to deposit photoresist and etch. In a preferred embodiment of the invention, a hard mask layer (e.g., a hard mask layer comprising ruthenium dioxide) is deposited onto the substrate. In some embodiments, these hard mask layers may need to be annealed or baked prior to exposure. A portion of the hard mask layer can be exposed to ultraviolet light to create an exposure pattern on the hard mask layer. After exposure, the unexposed portions of the hard mask layer are removed by wet etching and the exposed portions are left behind. This wet etch can include, for example, a 7 200945415 HF solution. After wet etching, in some embodiments, the hard mask layers are subjected to a plasma treatment or annealing treatment to further improve the properties of these hard mask layers for future use. Various modifications or variations of such embodiments are also included within the scope of the invention. This hard mask pattern can be applied to the fabrication of semiconductors, microelectronic mechanical systems, and other components.

Figure 1 shows the various steps of a typical hard mask etch process. A substrate 110 is provided in step 〇, and a hard mask layer 115 is deposited on the substrate 110. The result is shown in step 101, and then a photoresist 120 is deposited on the hard mask layer 115. The results are shown in step 1〇2. Referring now to 1〇3', the photoresist 12 is exposed to a specific pattern by UV light 130. This UV light 13 can come from a stepper or other photolithography system. The photoresist 12 暴露 exposed under 1 乂 13 〇 can then be partially removed using a PR development step and the results are shown in (4) 1Q4. Next, the material mask is subjected to dry etching or wet etching. The results are shown in (4) 1〇5. After the photoresist etching, the photoresist is removed by an ashing process, and the result is shown in step ι6, followed by a wet (four) process step (10). As shown in the figure and the text (4), the typical hard mask button engraving process requires the use of complicated processing steps. The most important one must use the photoresist to be deposited and engraved. Although there are many variations in the process of etching the hard mask described above, the general hard mask (4) must contain the deposition of the photoresist and (4) steps. Conversely, embodiments of the invention include hard masks that do not require the use of deposition and motive photoresist. dust? Circle _ 1 Figure 2 illustrates an embodiment in which a hard mask etched with a photoresist is not required in accordance with the present invention. The substrate 110 is provided in the step 201 as shown in FIG. The substrate 110 can be used as a composite substrate, a Ιπ_ν composite substrate, a ruthenium/ruthenium substrate, a worm substrate, an insulating substrate, a display substrate (eg, a liquid crystal display (LCD) substrate, an electric display substrate, and an electric Luminescence (called a light substrate or a light-emitting diode (LED) substrate). In some embodiments, the substrate 110 can include at least a structure, for example, (4) structural cards, joint faces, a pole body, a transistor, a metal oxide Semiconductor field effect transistor (MOSFET), interlayer dielectric (IDL) structure, inter-metal dielectric (IMD) structure, circuit, other semiconductor structure or various groups thereof. The substrate 110 may be a semiconductor wafer ( For example, a germanium wafer of 2 mm, 3 mm, 400 mm, etc.) β may have at least one trench in some implementations. In some embodiments, the substrate 11 may be a semiconductor. Wafers (eg, '200 wafers of '200 mm, 300 mm, 400 mm, etc.') may include structures, component components, etc. formed in previous steps. For example, the substrate may include trenches having a high aspect ratio, such as 'South wide ratio at 5. 1 Above, 6:1 or more, 7:1 or more '8:1 or more, 9:1 or more, 1 〇: 1 or more, 〗 i: 1 or more, 12:1 or more, etc. Step 202 The hard mask layer 115' deposited on the surface of the substrate 11. The hard mask layer 115 may be a layer of tantalum oxide, and the hard mask layer may be deposited using any of the following deposition techniques. Including: spin coating, chemical vapor deposition, atomic layer deposition, and / 200945415 or physical vapor deposition. According to the present invention, the hard mask layer may include tantalum oxide. For example, for depositing the hard mask layer The chemical includes an adjustable Si〇c (which contains carbon that is adjustable under baking conditions, Sio including baking conditions and/or precursor chemicals, and/or has a precursor that includes NH3 as a nitrogen source) The sioN of the chemical. Various other deposition techniques can be used to deposit the hard mask layer. Some techniques are exemplified in the present disclosure. After deposition, the hard mask layer 115 can be subjected to an optional annealing treatment. Annealing can enhance the film by increasing E. Annealing can also improve the hard cover. The optical properties of the layer, such as varying the η and 1 values of the hard mask layer. The anneal may comprise a single step or a multi-step anneal. The anneal may also be wet or dry anneal. According to one embodiment of the invention, a single Annealing of the step. According to one embodiment, the annealing may be carried out at a temperature of about 3 〇 c to 75 〇 C and in an environment containing N 2 , Ar and/or other inert gases. Including 〇2, Η", WHS and/or Νζ〇. In another embodiment of the invention, the film can be deposited in an environment of substantially dry (ie, dry nitrogen, helium, argon, etc.) The layer is heated to about 30 (rc to about 1 Torr) (e.g., about 6 Torr to about 900). The temperature of the crucible is annealed. This annealing treatment removes moisture from the deposited film layer and converts the Si_〇H group into oxidized stone. The annealed ruthenium oxide layer preferably has a film property (i.e., a werr value in the range of from about 6 to about 3, or less), and the dielectric properties are good (i.e., the value of 200945415 is close to or equal to that of pure ruthenium). ). In certain embodiments, this annealing step can be carried out under nitrogen at a temperature of about 90 (rc) for about i hours. In certain embodiments, a multi-step annealing process can be used, including a two-step annealing, such as First, the hard mask layer ιΐ5 is first subjected to wet annealing, for example, heating the film layer under steam to a temperature of about 65 〇t; then, the hard mask layer 115 is subjected to dry annealing, for example, in the vicinity of almost no gas. Under ambient conditions (eg, under dry nitrogen), the crucible layer is heated to a high temperature of about 900° C. In addition to dry and wet thermal annealing, other annealing techniques can be used to anneal the hard mask layer 115. Including vapor annealing thermal annealing, inductively coupled plasma (ICP) annealing, ultraviolet annealing, electron beam annealing, acid vapor phase catalyst annealing, gas phase catalyst annealing, and/or microwave annealing, etc. Step 203 shows that the hard mask layer 115 can be exposed to the ultraviolet light 130. A mode of UV light 130 is incident on the surface of the hard mask layer 115. This UV light U0, for example, can include About 43 6nm, 3 65nm, 24 Light at 8 nm, 193 nm or 157 nm. The exposure step of this UV light 130 can be performed in a stepper or other photolithography device. The stepper allows UV light 130 to pass through a mask or mask. The pattern of UV light 130 can be created on the surface of the hard mask layer 115. Various image patterning techniques, devices, and/or processes can be used to create a pattern on the hard mask with UV light 130. The mask layer 115 to be hardened After being exposed to the UV light pattern, a wet etching of 200945415 can be applied to remove the unexposed portions of the hard mask film, and the results are shown in 204. Wet etching includes the use of an etchant containing HF. Additional ingredients are included, such as HF, NH4 〇 H, SCL, and or RCA. Component materials and/or concentrations that improve the etch selectivity between the exposed and unexposed portions of the hard mask film can be used in wet etching. After etching, plasma treatment and/or annealing may be performed to adjust the properties of the hard mask layer for future use. Annealing may be wet annealing, ® annealing, vapor annealing, ultraviolet annealing, electron beam annealing, acid strontium Phase catalyst annealing, gas test Chemical annealing, microwave annealing, single-step or multi-step annealing, etc. The annealing may include Ν2, Αγ and/or other inert gases in an environment other than 〇2, η2〇, Νη3, Νζ/Η2 and Ν2 Performed in a reactive environment such as helium. Plasma treatment may include capacitively coupled plasma processing and/or inductively coupled electricity in an environment of 〇2, Ν2, Ar, Η0, Ν2〇, and/or inert gas. Slurry Processing. The flowchart of Figure 3 illustrates the various steps of the υν hard mask patterning process in accordance with an embodiment of the present invention. In block 3〇5, a hard mask film is deposited on the substrate. This hard mask film may include, for example, cerium oxide. Such deposition methods may include, for example, spin coating, chemical vapor deposition, atomic layer deposition, and physical vapor deposition. After deposition, in some cases, the hard mask film may be baked or annealed as shown in block 31. The hard mask film may be exposed to the UV light pattern in block 3 15 using any of the annealing techniques. The length of exposure depends on the chemical properties of the hard mask, during annealing (if any), the gaseous environment, and the conditions of the hard mask. After UV exposure, the hard mask film can be removed using wet etching in block 320. After etching, a non-essential plasma treatment and/or annealing may be performed in block 325 to adjust the properties of the hard mask film. The flowchart of Fig. 4 shows various steps of an exemplary method 400 for forming an oxide layer on a substrate. The method 400 includes providing a substrate 110 in a deposition chamber. The substrate 110 may be a type of ε 基板 substrate, a iii_v group composite substrate, a 矽/锗 substrate, an epitaxial substrate, an insulating layer overlying ruthenium substrate, a display substrate (eg, a liquid crystal display (LCD) substrate, a plasma display substrate , an electroluminescence (EL) lamp substrate, or a light-emitting diode (led) substrate). In some embodiments, the substrate 110 can include at least one structure, such as a trench structure, a well, a bonding surface, a diode, a transistor, a metal oxide semiconductor field effect transistor (MOSFET), and an interlayer dielectric (IDL). Structure, inter-metal dielectric (IMD) structure, circuit, other semiconductor structure, or various combinations thereof. The substrate 110 may be a semiconductor wafer (e.g., a chip of 200 mm, 300 mm, 400 mm, etc.). In some embodiments, the substrate 110 can have at least one trench. In some embodiments, the substrate 110 can be a semiconductor wafer (e.g., a 200 mm, 300 mm, 400 mm, etc.) and can include structures, component components, and the like formed in the prior steps. For example, the substrate may comprise a trench having a higher aspect ratio 'eg, an aspect ratio of 5: 1 or above, 6: 1 or more '7: 1 or more, 8: 1 or more, 9: 1 Or above, 10: 1 or above ' 11 : 1 or above, 12 : 1 13 200945415 or above and so on. In certain embodiments, method 400 can include generating an atomic oxygen precursor at a distal end of the deposition chamber at step 4〇4. The atomic oxygen precursor can be formed by dissociating an oxygen-containing precursor such as oxygen molecules (〇2), ozone (Ο;), and nitrogen oxides (eg, NO, N02, n2〇, etc.). ), hydrogen-oxygen compounds (eg, Η ", he»2, etc.), carbon oxy-compounds (eg, c〇, c〇2, etc.), and other oxygen-containing precursors and combinations of these precursors . In certain embodiments, the atomic oxygen precursor can be formed by dissociating the internally odorous precursor. These ozone-containing precursors can be a mixture of oxygen and ozone. For example, f oxygen can be supplied to the ozone generator. In an ozone generator, at least a portion of the oxygen can be ozonated to form ozone. In some embodiments, the flow rate of this oxygen is between about 3 slm (standard liters per minute) to about ® lm. The weight of ozone in the oxygen after ozonation. / 〇 between about 6% to about 20%. In some embodiments, the step of dissociating the oxygen-containing precursor to produce atomic oxygen can be 70% by thermal dissociation, uv photodissociation, and/or electropolymerization. Plasma dissociation involves the generation of an atomic oxygen precursor by injecting a gas such as helium, argon, etc. into the plasma at the far end plasma generation chamber, and then arching the oxygen precursor into the plasma. In step 4 〇 6, the atomic oxygen precursor is introduced into the deposition chamber, first with the ruthenium precursor (which is introduced into the sink 14 e in step 4〇8)

H3C0 .〇ch3 h3c〇 〇ch3 Tetramethoxysiloxane (TMOS) H OC2H5 c2h5o oc2h5 Triethoxysiloxane (TRIES) 200945415 The chamber is mixed. In step 410, the atomic oxygen precursor may be associated with a ruthenium precursor (and other deposition precursors that may be present in the reaction chamber) at a temperature of from about -10 ° C to about 200 ° C and from about 10 torr to about 760 torr. The reaction is carried out under the total chamber pressure to form a yttrium oxide hard mask film 115 (as shown in Fig. 2). The ruthenium oxide film 115 reduces the aspect ratio between the trench and the trench. The C:Si atomic ratio of the ruthenium precursor is about 8 or less (e.g., C: Si atomic ratio is about 7, 6, 5, 4, 3, 2, 1 or less). This represents less than eight carbon atoms per ruthenium atom of the ruthenium precursor. In certain embodiments, the ruthenium precursor can be a oxoxane compound, for example, triethoxy methoxy hydride (TRIES), tetramethoxy methoxy hydride (TMOS), trimethoxy methoxy hydride (TRIMOS), six Other oxane compounds such as oxime dioxane (HM0DS), octamethoxytrioxane (0M0TS), and/or octadecyloxydecane (0MODDS)·· Η 〆 \ h3co och3

Trimethoxysiloxane (TRIMOS) H3CO, , OCH3 H3CO. OCH3 OCH3 H3CO-

Si——〇——Si- -OCH3

H3CO

Si-O -Si- -Si--OCH3

H3CO OCH3

H3CO

Hexamethoxydisiloxane (HMODS) OCH3 Octamethoxytrisiloxane (OMOTS) OCH3 15 200945415

Och3 I Si——O—Si /〇CH3 4 / i / l-OCHg H3CO——Si——ώ——&一 h3co ο 〇

H3CO

Si—-a φ——SLI / \ I / 9 d och3° 〇1/ 1/ Si——〇——Si OCH3, 〇CH3

Octametho^dodecasiloxane (OMODDS) H3CO--Si-O, .OCH3/ \ / 〇Si^ , OCH3 H3CO - Si Ω 〇•Si, H3CO I , och3 och3 Octamethoxycyclicsiloxane ❹ In other embodiments, the ruthenium precursor can Is a silazoxane comprising one or more nitrogen groups. These indole oxynitride compounds include hexamethoxydisilazoxane (HMDS-H), methyl hexamethoxydisilazoxane (HMDS-CH3), and gas hexamethoxydiazoxide ( Chlorohexamethoxydisilazoxane, HMDS-C1), hexaethoxydisilazoxane (HEDS-H), nonamethoxytrisilazoxane (NMTS), and octamethoxycyclic silazoxane (octamethoxycyclicsilazoxane, Other oxane compounds such as OMCS): 200945415 e h3c〇\ H3CO——Si-HzC〇/ -N- /〇CH3 -Si-—OCH3 \〇ch3 H3CO, ch3 〇CH3 H3CO--Si-N-Si- OCH3

Hexamethoxydisilazoxane (HMDS-H) H3CO\ 『 /OCH3 H3CO--Si--N-Si;-OCH3 H3CO Chlorohexamelhoxydi! (HMDS-Cl) OCH3 silazoxane

Lethoxytnsilazoxane (NMTS) H3CO 〇CH3 Methyl hexamethoxydisilazoxane (HMDS-CH3) c2h5o, C2H5O—)Si-N- /〇C2H5 -Si—OC2H5 C2H5O OC2H5 Hexaethoxydislazoxane (HEDS-H)

H3CO

H H3CO——Si-N /OCH3〇 , Si\ , OCH3 H3CO-

Si HN - Si I, 〇CH3 OCH3 Octamethoxycyclicsilazoxane (OMCS)

H3CO In still other embodiments, the ruthenium precursor can be a halogenated oxosiloxane compound comprising one or more halo groups (e.g., fluorine, chlorine, desert or broken). For example, the halogenated oxoxane compound may be a vaporized oxoxane compound, for example, tetraclorosilane (TECS), dichlorodiethoxy siloxane (DCDES), gasification three. Other chlorinated oxime oxygenation of chlorotriethoxysiloxane (CTES), hexachlorodi si loxane (HCDS), or octachlorotrisiloxane (OCDS) 17 200945415 Compound.

Cl OC2H5 OC2H5

Cl——Si——Cl I Cl Tetrachlorosilane (TECS)

Cl——Si——OC2H5

Cl

Dichlorodiethoxysiloxane (DCDES)

Cl-Si-OC5H5

I OC2H5

Chlorotriethoxysiloxane (CTES)

Cl

Ci a.

Cl

Cl

A- -Si——0——Si——Cl ci- •Si-〇-Si-〇-Si-Cl a ci Hexachlorodisiloxane (HCDS)

Cl CI Octachlorotrisiloxane (OCTS)

Cl The oxygen: 矽 ratio of the ruthenium precursor is about 〇, 〇. 5, 1, 2, 3, 4, 5, 6, etc. or higher. For example, the oxygen:twist ratio in TMOS is about 4. Other ruthenium precursors, for example, TRIES and TRIMOS have an oxygen: 矽 ratio of about 3. Other oxygen, e.g., HCDS ratios are about 0.5, and the oxygen:ruth ratio of TECS is zero.

The ruthenium precursor may include a Si-0-Si bond, as is the bond contained in other organic ruthenium compounds such as HMODS, OMOTS, OMODDS 'HCDS, and OCTS. The ruthenium linkage in the ruthenium precursor helps to form a SiOx film with less contamination from carbon and hydroxyl groups. In certain embodiments, the ruthenium precursor may include amino oxime, such as trisilylamine (TS A), hexamethyldisilazane (HMDS), heterogeneous H. Silatrane), tetrakis(didecylamino)shi shochu 18 200945415 (tetrakis(dimethylamino)silane), bis(diethylamino)silane 'di-tert-butylammonium sulphide (bis-tert-butylaminosilane), bis(dimethylamino)silane (BDMAS), tris(dimethylamino)chlorosilane, and methyl Other compounds such as methylsilatrane.

SiH3 H3C-ch3 -Si CH3 ,Si:

H3C

N ^CH3 , ch3 H3Si- 'SiH3

H

Trisilylamine (TSA)

Hexamethyldisilazane (HMDS)

(H3C)2N, (h3c)2n/ /N(CH3)2 Si\ N(CH3)2

(C2H5>2N /H (H3C)2N

(H3Q2N-^Si-Cl (C2H5)2N H (H3C)2N

Tetrakis(dimethylamino)silane Bis(diethylainino)silane Tris(dimethylamino)chlorosilane

In other embodiments, the ruthenium precursor may include dioxanes including alkoxydioxanes, alkoxy-alkyldioxanes, and alkoxy-ethoxydioxanes. The alkoxydioxane may include: 19 200945415 R2~~^Si-Si<--R5 R, wherein Rw may be a Cw alkyloxy group, respectively. For example, the alkoxydioxane may include other alkoxydioxanes such as hexamethoxydioxane and hexaethoxydioxane. The alkoxydioxane may also include a cyclic dioxane compound having an alkoxy group bonded to a ruthenium atom. For example, the alkoxycyclodecane may include octaethoxycyclobutane, decahydrocyclopentane, dodecaoxycyclohexane, and the like. Some examples of alkoxydioxanes are shown below: (H3C)0. .0(CH3) (H3C)O^Si—Si^〇(CH3) (H3C)0X \〇(ch3) Hexamethoxydisilane H3CH2CO\ /〇 CH2CH3 H3CH2CO—^Si-Si^-"〇CH2〇H3 h3ch2c〇/ , OCH2CH3

Hexaethoxydisilane

H3CO y〇CH3 h3co, \Si, /OCH3 H3CO- H3CO, -SiI •.Si,

SiI, Si s〇CH3 och3

H3CO

Si OCH3 H3CO 〇CH3 Dodecamethoxycyclohexasilane This alkoxydioxane may include: R7\^ ^^^Rio R8~~~pSl-Siv^-Rn

Rg wherein R7_12 may be C!_3 alkyl or Cm alkoxy, respectively, and wherein up to 20 200945415 one 117.12 is an alkyl group and at least one r7_12 is an alkyloxy group. The alkoxyalkyldioxane may also include a cyclic bismuth sulphide having an alkyl group and an alkoxy group, for example, butyl sulphate, pentylene sulphate, hexa sulphur, stagnation, octane, etc. , having at least one alkyl group and an alkoxy group bonded thereto. Examples include: octamethyl-1,4-dioxy-2,3,5,6-tetramous 衷 己 炫 >, 1,4 -dioxy-2,3,5,6-trioxane Other alkoxy-alkyl cyclic decanes such as alkane and 1,2,3,4,5,6-hexamethoxy-1,2,3,4,5,6-hexamethylenecyclohexane . Examples of certain alkoxy-alkyldioxane compounds are as follows: H3Cn ch3 H3C\)Si O H3c〆II λ ii-ch3 Sl ch3 H3CT, CH3 octamethyl-l, 4-dioxa-2,3,5,6 -tetrasilacyclohexane

l,4-dioxa-2,3,5,6-tetrasilacyclohexane ❿ h3ch2co^ .OCH2CH3 H3C--pSi-Si^--〇Η3 H3CH2CO', OCH2CH3 1,1,2,2-tetraethoxy-1,2-dimethyldisilane The alkoxy-acetoxydioxane may include: R13\^R16 R14~~~; Si-Si<-R17 R15', R18 wherein R13_17 may be Cw alkyl, (^_3 alkoxy or ethoxylated, respectively). And wherein at least one Rn-17 can be an alkoxy group and at least one r13_17 21 200945415 can be an ethoxycarbonyl group. The ruthenium precursor can include an organic ring, cyclopentane, cyclohexane, and cycloglycan. By way of example, decane, for example, cyclobutane decane, cyclooctane, etc. In certain embodiments, the spleen & first introduces the sputum drive with a carrier gas mixture into the conditional chamber. Carrier gas can be no substantial

Interfering with the formation of U5 (IV) active gas on the base & m. Examples of carrier gases include those in which the word a is sputum, helium, argon, and hydrogen. In an embodiment of method 400, prior to introduction into the deposition chamber, the atomic oxygen precursor may be first mixed with the Shixia precursor. These precursors are introduced into the chamber via separate, independent precursor inlets disposed around the reaction chamber. For example, the atomic oxygen precursor can be introduced into the substrate by the inlet at the top of the chamber and directly above the substrate. This population can direct the oxygen precursor to flow substantially perpendicular to the substrate deposition surface. At the same time, the Shixi precursor may enter the chamber by one or more inlets around the side of the chamber. These persons may induce the (4) precursor to flow in a direction substantially parallel to the substrate deposition surface. In some embodiments, the atomic oxygen precursor and the Shixia precursor can be passed through individual mouthpieces on the multi-mouth nozzle. For example, a showerhead positioned above the substrate can include a plurality of openings in a mode for the precursor to enter the deposition chamber. An opening of the first subset can be provided to flow into the original: oxygen precursor while providing an opening of the second subset to flow into the crucible. Through the different subsets, the precursors are fluid to each other 22 200945415 isolated state 'until leaving the deposition chamber. Other details and types of design relating to the precursor treatment equipment are disclosed in the US Provisional Application No. 6〇/8〇3,499, entitled “Process Chamber,” in May 30, 2006. For DieleCtricGapfiUj, the disclosure of which is incorporated herein by reference. Because the atomic oxygen precursor and the ruthenium precursor can react in the deposition chamber, a ruthenium compound layer can be formed on the substrate deposition surface in step 41. 115. The initial oxide layer may have desirable fluidity and may migrate into gaps, trenches, holes, slits, etc. on the deposition surface. This allows method 400 to provide oxide filling with almost no pores and slits. Gap, groove, and other high aspect ratio values (eg, aspect ratios of approximately 5:1, 6:1, 7:1, 8:1, 9:1, 1〇:1, 11:1, and 12:1) The structure may be hardened in block 412. φ Referring to Figure 5A, which is a vertical wear view of CVD system 10, showing a vacuum or processing chamber 15 This chamber 15 includes a chamber wall 15a and a chamber lid assembly 15b. This CVD system 10 pack The gas knife is equipped with a manifold 11' for distributing the processing gas to the substrate on the heating platform 12 parked in the center of the processing chamber 15 (the gas distribution manifold U is not shown to be made of a conductive material for forming a capacitive plasma) Electrode during processing. During processing, the substrate (eg, semiconductor wafer) is parked on the flat surface 12a of the heating platform 12. The platform 12 can be controlled to be in a lower loading/unloading position (eg, as shown in FIG. 5A) Moving between the higher 23 200945415 processing position (as indicated by the dashed line in Figure 5A), which is in close proximity to the manifold 11. There is also a central panel (not shown) including the sensor 'used to Providing positional information on the wafer. The deposition and carrier gas are introduced into the chamber 15 via a plurality of holes in a conventional flat, circular gas distribution panel 13a. In detail, the deposition process gas flows in through the inlet manifold 11 The chamber passes through a conventional, porous baffle and then passes through a plurality of holes in the gas distribution panel 13a. ® before the manifold 11 is reached, the gas source is supplied via a gas line to the gas reservoir to a gas mixture. Within the system' The mixture is then sent to the manifold 11. In general, the supply line for each process gas includes (i) a plurality of female full shut-off valves (not shown) that can be used to automatically or manually shut off the gas flowing into the chamber. , and (ii) a mass flow controller (not shown) for measuring the inflow of gas through the supply line. When toxic gases are used in the process, multiple safety can be set on each gas supply line in a conventional manner. The deposition process performed on the CVD system 1 may be a heat treatment or a plasma strengthening treatment. In the plasma strengthening treatment, electric power is applied between the gas distribution panel 13a and the stage 12 with an RF power source to excite the processing gas. The mixture forms a plasma in a cylindrical region between the gas distribution panel 13a and the platform 12 (this region is referred to as a "reaction zone"). The composition in the plasma can be deposited to form a desired film layer onto the surface of the semiconductor wafer supported on the stage 12. The RF power is a mixed power, typically supplying a high frequency of 13.56 bribes and a low frequency of 36 kHz. 24 200945415 Power to enhance dissociation of reactive species introduced into the vacuum chamber 15. In the heat treatment, the RFf force is not caused, and the process gas mixture is thermally reacted with each other to form a film layer on the surface of the semiconductor wafer supported on the stage 12, which is provided by resistive heating. The heat energy required for the reaction. During the plasma enhanced deposition process, the plasma can heat the entire processing chamber 15' including the chamber walls surrounding the chambers 15 of the exhaust passage 23 and the shutoff valve 24. When the plasma has not been opened or during thermal deposition, a flow-hot fluid can be circulated in the chamber wall 15a of the processing chamber 15 to maintain the chamber at a high temperature. Other channels in the chamber wall 15a are not depicted. The thermal fluid used to heat the chamber wall 15a includes a typical fluid class, i.e., an aqueous glycol or an oily heat transfer fluid. This heating (referred to as heating by "heat exchange") can advantageously reduce or eliminate condensation of the undesired reaction product and improve the volatile products of the treated gas enthalpy and other contaminants that may contaminate the process (if The elimination of condensing on the walls of the cooling vacuum channel and migrating back into the processing chamber during the absence of gas flow. The remaining portion of the gas mixture σ which is not deposited as a layer is included by a vacuum pump (not shown), including reaction by-products, and is evacuated from the chamber 15. In particular, the exhaust gas is discharged into an annular discharge chamber 17 from an annular, slotted opening 16 surrounding the reaction zone. The annular groove 16 and the plenum 17 are common to the gap 25 200945415 between the top of the cylindrical side wall 15a of the chamber (including the upper dielectric lining 19 on the wall) and the bottom of the annular chamber cover 2〇. The world is coming. The annular groove 16 is adjacent to the gas chamber 17. Uniform fluidity of wafer dicing during symmetry and uniformity of nuclear gas is very important, such as shisha heat + θ _ to deposit a uniform film on the wafer. ,

The air flow from the exhaust chamber 17 flows under the horizontal extension of the exhaust chamber 17 'through the viewing portion (not shown), the gas extends through the lower portion, the passage 23, through the vacuum shut-off valve 24 (the body and the lower chamber) The wall 15a is shaped and enters an exhaust port 25 connected to an external vacuum pump (not shown) via a leading edge (not shown). It is designed as two full-circle parallel concentric circular in-line military loops. Insert the heater to replace the wafer support plate on the resistive heating plate (preferably the name, the ceramics or a combination thereof). The outer part of the heater element is parallel to the inside of the heater element. A concentric, circular path of small radii. The line of this heater element will pass through the struts of the platform 12. Typically, any or all of the chamber liners, gas population manifold panels, and various other reactors are It is made, for example, by singular, anodizing, or ceramic. One of the examples of such a CVD apparatus is disclosed in U.S. Patent No. 5,558,7, the entire disclosure of which is incorporated herein by reference. Need to insert through the side wall of the chamber /Remove the opening % When the wafer is moved into or out of the body of the chamber 15 by a robotic arm cutter (not shown), the motor 32 of the lifting mechanism (Fig. 5A) and the wafer lift lock 26 thereof may be utilized. b to the well; g; + v or lower the heated platform assembly 12. The motor 32 can be raised or lowered between the processing 1 / 1 A 14 and the lower wafer loading position. / / 1 σ ° open 12. Motor, valve connected to the supply line or flow controller gas delivery system, throttle valve, RJF power supply and chamber and substrate heating system are all in the system control through the control line (partial display Out) to control the controller to rely on the feedback signal of the light sensor to determine the movable machine

The moving position of a piece (such as a throttle valve and a carrier that moves with a suitable motor under the action of a controller).

In the illustrated embodiment, the system controller includes a hard disk drive (memory), a floppy disk drive, and a processor. The processor includes a stand-alone computer (slngle_b()ard_puter>, prison), analog and digital input/output cards, an interface card, and a stepper motor controller card. Each component of the CVD system 10 is adapted to define a substrate, a card. Box and connector sizes and types of Versa Modular European (VEM) standards. This VEM standard also delimits the bus structure & 16_bit data bus and 2 heart address bus. The system controller controls all activities on the CVD machine. The system controller can execute system control software stored on a computer readable medium (e.g., memory). Preferably, the memory is a hard disk, but it can be other forms of memory. The computer program includes sets of instructions: 'It: indicates the time associated with a particular process, gas mix, cavity to fool, chamber temperature, lamp power level, carrier position, and eight parameters. A computer package stored on other component (4) 27 200945415 includes, for example, a floppy disk or other suitable drive for operating the controller.乍 The computer program product executed by the controller can be used to implement the processing of the film layer on the substrate or a master and an enlightenment for cleaning the cavity. These computer programs can be written by conventional computer readable programs: for example, 68000 combined languages, C, C++, Pascah_ortran or others. The appropriate code is stored in a single file or multiple files using a conventional code editor and stored in a computer system such as a computer's memory system. If the stored coded text is in a higher-level language, editing must be performed, and the resulting edits are then linked to the pre-edited Microsoft Windows 8 regular object code. To perform the link, the system user activates the object code so that the computer system loads the code into the memory. The CPU can then read and execute the code ' to perform the work identified by the program. ®. The interface between the user and the controller is via the CRT screen 5A and the light pen 50b' as shown in Figure 5B, which is a system screen and substrate processing system (which may include one or more chambers) CVD system 10 Simplified diagram. In the preferred embodiment, two screens 50a are used, one mounted on the cleanroom wall for all operators to use 'the other is installed behind the chamber wall' for service technicians." Screen 50a can display the same information at the same time. 'But only one light pen 50b is operational. The light sensor at the top of the light pen 5 Ob detects the light emitted by the CRT display. To select a specific screen or function, the operator simply touches a specific area on the 200945415 and presses the button on the stylus. The touched area will change its cue color (highHghted or display a new screen or menu to confirm the connection between the screens.) Other devices such as keyboard, mouse, or Other pointing or connecting devices replace the light pen _ or interact with the light pen 50b to allow the user to communicate with the controller. Figure 5A shows the remote electrical generator 6 on the processing chamber 15 ❿-, The chamber lid assembly 15b includes a bull gas distribution panel 13a and a gas distribution manifold u. The remote power generator 6 is mounted to the chamber lid assembly with a mounting adapter 64, as shown in Figure 5A. The adapter 64 is typically made of metal. A mixing device 70 is coupled to the upstream side of the gas distribution manifold (as shown in Figure 5A). The mixing device 7 includes a mixing insert 72 (located in The tank in the mixing zone is used to mix the process gas. A ceramic insulator 66 (Fig. 5A) is provided between the adapter 与 and the mixing device 70. The ceramic insulator 66 may be made of a ceramic material such as alumina ( 99% purity), Teflon®, or Others. When installed, the mixing device 70 and the Tauman insulator 66 can form a portion of the chamber cover 15b. The ceramic insulator 66 can insulate the metal adapter material from contact with the mixing device 70 and the gas distribution manifold u. The probability of forming a secondary plasma in the chamber lid assembly 15b is minimized, as detailed below. A three-way valve is used to control the flow of process gas directly to the processing chamber 15 or through the slurry generator 60. The flow to the processing chamber 15 200945415 The remote plasma generator 60 is preferably a small, self-contained unit and can be conveniently mounted on the chamber lid assembly 15b and can be used without the need for mussels. • Expendable or time-consuming modifications are easily reverse mounted to the chamber to be detached. One suitable unit is Applied Science and Technology, Inc, Woburn,

Mass) ASTRON® generator. This ASTR〇N8 generator can use low field toroidal plasma to dissociate the process gas. In one example, the plasma can dissociate a processing wind including a fluorine-containing gas (e.g., NF3) and a carrier gas (e.g., argon) to produce a film that can be used to clean deposits in the processing chamber 15. The free fluorine atom of the layer. Several embodiments have been described in detail above, and those skilled in the art

Said. Therefore, the scope of the invention is not limited to the above description.

Except or excluded from this range, the upper and lower limits of each of the small intervening values in the value and any intervening values therein may be excluded, and each range, regardless of its 30 200945415 The inclusion of one or both ends is excluded or excluded from the scope of the invention. When the range includes one or both of the two ends, it also covers the exclusion of the second one. As stated in the accompanying claims, the singular forms "a", "the" and "the" are used in the plural. Thus, for example, "a method" includes a plurality of such methods, and "the precursor" includes one or more precursors and equivalents thereof. In addition, the words "comprises", "including", "include", "include", "include", "include", "include", "include", "include" However, the existence of one or more other features, values, components or steps is not excluded. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 shows various steps of a typical hard mask etching process; Fig. 2 is a view showing results of respective processing steps in a hard mask etching process according to an embodiment of the present invention; A flow chart of a method for patterning a hard mask according to an embodiment of the invention; FIG. 4 is a flow chart of a process including a method for forming an oxide layer on a substrate according to an embodiment of the present invention. Process 31 200945415 Step; Figure 5A is a vertical cross-sectional view of an exemplary thin film deposition system; Figure 5B is a simplified diagram of an exemplary system monitor/controller assembly of a thin film deposition system. The same element symbols are used in the drawings to indicate similar components and/or features. Moreover, various components of the same type may be distinguished by dashed lines and component symbols used to distinguish the second number of similar components. If only the first reference number is used in the specification, the description of the first reference number applies to all similar components having the same first reference number (regardless of the second reference number). [Main component symbol description] 10 CVD system 11 gas distribution manifold 12 platform 12a flat surface 12b wafer lift pin 14 processing position 15 processing chamber 15a chamber wall 15b chamber cover assembly 16 annular, slotted opening 17 ring Exhaust chamber 19 upper square dielectric liner 20 chamber cover 21 horizontal extension 23 exhaust passage 24 shutoff valve 25 exhaust port 32 motor 50a CRT screen 50a 50b light pen 60 remote plasma generator 64 adapter 66 ceramic insulator 70 mixing device 32 200945415 72 hybrid insert step 100, 101, 102, 103, 104, 105, 106 107 wet etching process 110 substrate 115 hard mask layer, tantalum oxide layer 120 photoresist 130 UV light 201, 202, 203, 204 Steps 305, 310, 315, 320, 325 Block 400 Method 402, 404, 406, 408, 410, 412 #STEP

33

Claims (1)

200945415 VII. Patent application scope: 1. A method for coating a hard mask layer by ultraviolet light, comprising: depositing a hard mask layer on a substrate in a deposition chamber; A plurality of portions of the cover layer are exposed to ultraviolet light, wherein portions of the hard mask layer exposed to ultraviolet light form a pattern of eXposed ❿ area on the hard mask layer And the last name of the hard mask layer 'where the etch removes a plurality of unexposed portions of the hard mask layer. 2) The method of claim 1, further comprising annealing the hard mask layer. 3. The method of claim 2, wherein the annealing is selected from the group consisting of vapor annealing, thermal annealing, inductively coupled plasma annealing, capacitively coupled plasma annealing, ultraviolet annealing, electron beam annealing, and beam annealing. , acid gas phase catalyst annealing, alkali vapor phase catalyst annealing or microwave annealing. 4. The method of claim 2, wherein the annealing occurs before the hard mask layer is exposed to the ultraviolet light. 5. The system of claim 2, wherein the annealing occurs after etching the hard mask layer 34 200945415. The method of claim 2, wherein the annealing occurs in a gas atmosphere containing an inert gas. 7. The method of claim 2, wherein the annealing occurs in a gas atmosphere selected from the group consisting of ν2, Αγ, 〇2, η2〇, ΝΗ3, Ν2/Η2 or Ν20. 8. The method of claim 1 further comprising providing a plasma treatment to the hard mask layer after the last name. 9. The method of claim 8, wherein the plasma is a capacitively coupled plasma or an inductively coupled plasma. The method of claim 8, wherein the plasma treatment is carried out under a gas atmosphere selected from the group consisting of ν2, Ar, 〇2, η2〇, Νη3, ν2/Η2 or ν2〇. U. The method of claim i, wherein the ultraviolet light comprises a wavelength of light at or equal to 348 nm. The method of claim 2, wherein the etching comprises a wet etching 35. The method of claim 12, wherein the wet etching comprises an etchant selected from the group consisting of HF, NH4OH, SCI And a group consisting of RCAs. 14. The method of claim 1 wherein the hard mask layer comprises 0 yttrium oxide. The method of claim 1, wherein the hard mask layer is deposited by a treatment selected from the group consisting of spin coating, chemical vapor deposition, atomic layer deposition, or physical vapor deposition. The method of claim 1, wherein the substrate comprises: a substrate selected from the group consisting of: a germanium substrate, a m_V composite substrate, a germanium/germanium substrate, a stray substrate, an insulating layer overlying germanium substrate, a display substrate, a liquid crystal display A substrate, a plasma display substrate, an electroluminescence lamp substrate, and a light emitting diode substrate. A hard mask deposition and patterning system comprising a deposition chamber and an ultraviolet light source, comprising: a deposition member for depositing a hard mask layer on the substrate in the deposition chamber to 36 200945415; exposing member For exposing portions of the hard mask layer to ultraviolet light; wherein the ultraviolet light can expose portions of the hard mask layer according to a pattern; and removing components for removing the hard A plurality of unexposed portions on the mask layer 0. The hard mask deposition and patterning system of claim 17 further comprises an annealing member for annealing the hard mask layer. 19. The hard mask deposition and patterning system of claim i, wherein the annealing is selected from the group consisting of vapor annealing, thermal annealing, inductive coupling, plasma annealing, capacitively coupled plasma annealing, ultraviolet annealing, electron beam annealing (e-beam annealing), acid gas phase catalyst annealing, alkali vapor phase catalyst annealing or microwave annealing. 20. The hard mask deposition and patterning system of claim 37, wherein the annealing occurs prior to the hard mask layer being exposed to the ultraviolet light. 21. The hard mask deposition and patterning system of claim 18, wherein the annealing occurs after etching the hard mask layer. The hard mask deposition and patterning system of claim 18, wherein the annealing occurs in a gas atmosphere comprising an inert gas. 23. The hard mask deposition and patterning system of claim 18, wherein the annealing occurs in a gas atmosphere selected from the group consisting of Ν2, Αγ, 〇2, η2〇, ΝΗ3, Ν2/Ϊ2 or Ν2〇. . 24. The hard mask deposition and patterning system of claim 17 further comprising means for providing a plasma treatment to the hard mask layer after etching. 25. The hard mask deposition and patterning system of claim 24, wherein the plasma is a capacitively coupled plasma or an inductively coupled plasma. 26. The hard mask deposition and patterning system of claim 24 wherein the plasma treatment is a gas selected from the group consisting of N2, Ar, 〇2, η2〇, ΝΗ3, 乂/出, or >j2〇 β 27. Occurs in the atmosphere 27. The hard mask deposition and patterning system as claimed in claim ι7, wherein the ultraviolet light comprises light having a wavelength less than or equal to 348 nm. 28. The hard mask deposition and patterning system of claim 17, wherein the etching comprises wet etching. 29. The hard mask deposition and patterning system of claim 28, wherein the wet residue comprises an etchant selected from the group consisting of HF, NH4OH, SCI, and RCA. 30. The hard mask deposition and patterning system of claim 17, wherein the hard mask layer comprises a oxidized layer. 31. The hard mask deposition and patterning system of claim 17, wherein the hard mask layer is deposited by a process selected from the group consisting of spin coating, chemical vapor deposition, atomic layer deposition, or physical vapor deposition. Into. 32. The hard mask deposition and patterning system of claim 17, wherein the substrate comprises a substrate selected from the group consisting of a germanium substrate, a III-V germanium composite substrate, a germanium/germanium substrate, an epitaxial substrate, and an insulating layer. The layer is covered with a substrate, a display substrate, a liquid crystal display substrate, a plasma display substrate, an electroluminescence lamp substrate, and a light-emitting diode substrate. 39