TW200423364A - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

A semiconductor package comprises a semiconductor chip, a first isolation layer, a second isolation layer, first traces, second traces, and bonding wires. The semiconductor chip defines an active surface and a back surface, and comprises a plurality of pads disposed on the active surface of the semiconductor chip. The first isolation layer covers the active surface of the semiconductor chip, and the second isolate layer covers the back surface of the semiconductor chip. The first traces are disposed between the first isolation layer and the active surface of the semiconductor chip, and are electronically connected to the pads, and the second traces are disposed on the second isolation layer. The bonding wires are used to electronically connect the first trace to the second trace, respectively. The semiconductor package further comprises an encapsulant for encapsulating the bonding wires.

Description

200423364 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package structure and beans, in particular, to a wafer-level semiconductor package structure and manufacturer [prior art] ® ^ body package It mainly has four functions, including: signal connection, power connection, & quantity distribution, and protection. Generally speaking, a semiconductor wafer is first formed into an enclosure, such as a single chip (jCM) or a chip carrier, called a semiconductor package. These packaged chips, along with other components, such as capacitors, resistors, poles, filters, switches, optical components, and RF components, are then assembled on a printed circuit board. With the increasing demand for lighter and more complex electronic devices, the speed and complexity of chips are relatively higher and higher, so higher packaging efficiency is required. The prior art has tried to provide various package structures and methods to improve the efficiency and reliability of the package. For example, U.S. Patent No. pr 6,040,235, issued to Badeh i on May 21, 2000, entitled `` Methods and Apparatus For Manufacturing Integrated Circuit Devices Producing Integrated • Circuit Devices), and US Patent No. 6, 1 1 7, 707, issued to Badehi on September 12, 2000, entitled "Methods of Producing Integrated Circuit Devices" , Reveals the method of manufacturing semiconductor package structure. However, the prior art semiconductor package structure and its manufacturing method have many limitations and disadvantages,

00656.ptd Page 6 200423364 V. Description of the invention (2) Such as relatively low credibility and electrical efficiency (Electrica) performance, relatively large volume, and relatively high manufacturing costs, and Can not fully meet the needs of semiconductor package construction. In view of this, there is a need for a wafer-level semiconductor package structure to further meet the needs of the semiconductor package structure. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor package structure and a direct manufacturing method, which have higher packaging efficiency and a relatively small size, and overcome many limitations in the prior art. It is a half-conductor, a first and a back insulation covering the edge layer and the connection, and the first structure is further obvious. In detail [implementing the above-mentioned object, the present invention provides a semiconductor package structure including a body chip, a first-insulation Layer, a second insulating layer, a first line and a second line, and a connection line. The semiconductor wafer defines an active surface and has a plurality of pads disposed on the active surface. The active surface of the conductor wafer, and the second insulating layer is the back surface. The first circuit is disposed between the active surfaces of the first- and last-minute films, and is electrically connected to the pads. The individual circuits are electrically connected to the connection line, including a 4+ gauge 2: a first circuit. The semiconductor package includes an encapsulant for encapsulating the connection line. Second, his purpose, characteristics, and advantages can be further improved. Take the example of Ben Sheming ’s car father ’s best example, and cooperate with the attached diagram. [Y] Please refer to FIG. 1, which shows a semiconductor package according to the present invention.

200423364

Structure 10. The semiconductor package structure 10 includes a semiconductor wafer 12, a first insulating layer 22, and a second insulating layer 24. The semiconductor wafer 12 has an active surf 14, and a semiconductor element (not shown) is disposed thereon, and a plurality of bonding pads 16 are electrically connected to the semiconductor element. The first insulating layer 22 is adhered to the active surface of the semiconductor wafer 12 through a first adhesive layer 26. The second insulating layer 24 is adhered to the back surface of the semiconductor wafer 12 through a second adhesive layer 28 '. The semiconductor wafer 12 further has a plurality of traces 18, which are electrically connected to the pad μ and extend beyond the semiconductor wafer 2. The second insulating layer 24 includes a plurality of solder balls 30 and a plurality of lines 38. The plurality of circuits 38 include a plurality of fingers 40 and pads 42. A solder mask 44 is applied on the second insulating layer 24 and exposes the pins 40 and the bonding pads 42. The solder ball 30 is fixed on the soldering pad 42. The second insulating layer 24, the plurality of circuits 38, and the solder mask 44 are formed by a plastic substrate or a tape with circuits attached to the back surface of the semiconductor wafer 12. The semiconductor package structure 10 also has a plurality of bonding wires 36, which electrically connect the circuit 18 of the semiconductor wafer 12 to the pin 40 of the circuit 38 of the second insulating layer 24, so that the tin The ball 30 is electrically connected to the pad 16 and the semiconductor element of the semiconductor wafer 12. A piece of colloid (61 ^ 3031113111 :) 32 encloses the line 18 of the semiconductor wafer 12, the line 38 of the second insulating layer 24, and the connection line 36. Those skilled in the art will understand that the multiple lines 18 series are not necessary

200423364 V. Description of Invention (4). The pad 16 can be extended to an edge, or even a side, of the semiconductor wafer 12 so as to be electrically connected to the second insulation sound line 38 through the connection line 36. Said

Please refer to FIG. 2 to FIG. 11 'for explaining the manufacturing method of the semiconductor package structure 11 according to the present invention. Here, the same elements will be assigned the same reference numerals between the different illustrations. B As shown in FIGS. 2a and 2b, a wafer 52 includes a plurality of semiconductor wafers 1 2 ', and adjacent semiconductor wafers 2 and 2 are spaced apart by scribe lines 54. Plurality: The pad 16 can be disposed on the wafer 52 by a photolithography process. The number of pads on each semiconductor wafer 12 depends on the design of the I / O circuit on the semiconductor wafer 12. As shown in FIG. 3, a metal extension layer 56 is disposed on the wafer 52, and is electrically connected to the pads 6 and 6 'to form the circuit 18, respectively. As shown in FIG. 4, the wafer 52 is adhered to a first insulating layer 22 through a first adhesive layer 26. Thereafter, as shown in FIG. 5, the back surface of the wafer 52 is polished by a mechanical polishing wheel 58 or a chemical polishing process, thereby reducing the wafer 52 by a predetermined thickness. As shown in FIG. 6 again, a cutting blade 60 cuts the back surface of the wafer 52 along a predetermined path to form a notch 62. The predetermined path may correspond to the scribe line 54 of the wafer 52. Thereafter, an etching process is performed to expose the metal extension layer M.丨,: In an alternative embodiment according to the present invention, after the wafer 52 has borrowed the first adhesive layer 26 to adhere to the first insulating layer 22, a cutting blade 60 may follow the cutting path. 5 4 corresponds to a predetermined path to cut the wafer 5 2

200423364 V. The back of invention description (5) ’, to form a notch 6 2. After that, after a rice-engraving process, the metal extension layer 56 is exposed, and the thickness of the wafer 52 is reduced to a predetermined thickness. In this embodiment, the polishing step can be omitted. As shown in FIGS. 7 and 8, the second adhesive layer 28 is coated on the back surface of the wafer 52 to laminate the second layer. Insulation layer 24. Referring to FIG. 9 ', a plurality of lines 38 are arranged on the second insulating layer 24, and include a plurality of fingers 40 and pads 42. The pin 40 is electrically connected to the metal extension layer 56 of the semiconductor chip 12 through a connection wire 36 through a wire bonding technology. The notch 62 is injected into the sealing compound 32 to encapsulate the metal extension layer 56, the pin 40, and the connection line 36. A solder mask and parts 38, and (tape) fine. Out of the edge of the connection should be connected 3, 6, and then power on. As shown in the wafer slicing, the layer (so 1de) covers the solder resist layer 44 and is attached to the semiconductor wafer of this technology, and then the pad 16 is connected to the cutting step as shown in FIG. 10 and FIG. 11. The metal mask 44 is coated on the second insulating layer 24 and the circuit 38. The second insulating layer 24 and the plurality of lines may be formed by a plastic substrate or a back surface of the tape-and-reel wafer 52 with lines. It will be understood that the metal extension layer 5 6 can omit the sheet 12, and the pad 16 can be disposed on the semiconductor wafer 12 to form the recess 62 after the process of etching and the etching process, and then exposed by wire bonding. Connection technology, the pin 40 of the line 38 by the connection line. As shown, a plurality of solder balls 32 are arranged on the bonding pad 42 and a separate semiconductor package structure is formed along the cutting line 54 of the wafer 52. After the extension layer 56 is cut as shown in FIG.

200423364 V. Description of the invention (6) Line 18. Those skilled in the art will understand that the active surface of the wafer is covered by the first insulating layer 22, and the first insulating layer 22 may be made of a transparent material such as glass, acrylic resin, or Sapph ire, so that light can penetrate the first insulating layer 22 and interact with semiconductor elements on the semiconductor wafer 12. In summary, in the method of manufacturing a semiconductor package structure according to the present invention, the semiconductor package structure can be manufactured in large quantities at a wafer level, so that the cost of the packaging process can be reduced, and the reliability of the package can be improved. . Furthermore, the semiconductor package structure according to the present invention can be applied to packaging of optical elements. Please refer to FIGS. 12 to 18, which are used to explain another manufacturing method of the semiconductor package structure 10 according to the present invention. Here, the same components between different illustrations will be given the same reference numerals. 24 layers of two insulation boards stacked on the wheel 58 or as shown in FIG. 12 'The wafer 5 2 is bonded to a first insulating layer 22 by a first adhesive layer 2 6, and the wafer The back surface of 52 is polished by mechanical grinding to reduce the far wafer 52 by a predetermined thickness. As shown in FIG. 13, the second adhesive layer 28 is deposited on the back surface of the wafer 52 to laminate the second insulating layer 24. Referring to FIG. 14, a plurality of lines 38 are arranged on the second insulation and include a plurality of fingers 40 and pads 42. A so 1 der mask 44 is coated on the second insulating layer 24. The first edge layer 24, the plurality of circuits 38, and the solder mask layer 44 are formed by tapes of a plastic substrate circuit attached to the back surface of the wafer 52.

200423364 V. Description of the invention (7) As shown in FIG. 15, a cutting blade 60 cuts the back surface of the wafer 52 along a predetermined path to form a notch 62. The predetermined path may correspond to the scribe line 54 of the wafer 52. Thereafter, a surname engraving process is performed to expose the metal extension layer 56. Referring to FIG. 16, the pin 40 is electrically connected to the metal extension layer 56 of the semiconductor wafer 2 through a connection line 36 through a wire bonding technology. The notch 62 is injected into the sealing compound 32 for encapsulating the metal extension f56 and the pin 40 and the connecting wire 36. As shown in FIG. 17, a plurality of solder balls 32 are arranged on the pad 42. As shown in FIG. 18 (a), a wafer cutting is performed on the cutting line 54 of the wafer 52 to be used to form an individual semiconductor package structure. Referring again to FIG. 19, there is shown a conductor package structure 80 according to another embodiment of the present invention. The semiconductor package structure 80 is generally a body package structure 10, and a similar branch in the bean—the upper β h is only guided by A. ^ ^ ^ ^ ^ Λ… ... like components are not the same. The second insulating layer 22 of the semiconductor package structure U80 further has a recess for receiving a passive component. The material conductor chip 84 is adhered to the bottom of the concave recess 82 and is electrically connected to the line 38 of the second insulating layer 22 through the connection line 86. A piece of # ss ~. The semiconductor wafer 84 and the connection compound 8 are used to encapsulate the recess 82, the structure 8 is a multi-chip mold as described above, and the semiconductor package is described as described above. And illustrations already | must understand that various additions, repairs 4 orders 73 I ^ Jiaguan embodiment, ^ ^. Xihe substitution may be used in the & embodiment of the present invention without departing from the attached female second The spirit and scope of the goods β 軚 隹 principle. Familiar; too: the present invention will help those who understand the present invention may make

534 200423364 V. Description of the invention (8) It is used to modify many forms, structures, arrangements, proportions, materials, components and components. Therefore, the embodiments disclosed herein should, in all respects, be considered to illustrate the present invention, rather than to limit the present invention. The scope of the present invention should be defined by the scope of the appended patents and the legal equivalents thereof, and is not limited to the previous description.

00656.ptd Page 13 200423364 Brief description of the drawings [Simplified description of the drawings] Figure 1: It is a schematic sectional view according to the present invention. Semiconductor Package Structure of the Preferred Embodiments Figures 2 to 11 are schematic cross-sectional views of a manufacturing method according to a > of the present invention. The semiconductor package structure of the yoke example Figures 12 to 18: A schematic cross-sectional view of a manufacturing method according to the present invention. The semiconductor package structure of another embodiment: the semiconductor package structure according to another embodiment of the present invention is illustrated in the drawing number: 10 semiconductor package structure 14 active surface 18. Circuit 2 4 second insulating layer 28 second adhesive layer 32 Sealing compound 38 Circuit 42 Solder pad 5 2 Wafer 5 6 Metal extension layer Semiconductor wafer pad First insulation layer First adhesive layer Solder ball lead wire Solder resist Cutting line Mechanical grinding wheel 00656.ptd Page 14 200423364 Figure Brief description of the formula 60 Cutter 62 Notch 80 Semiconductor package structure 82 Recess 84 88 Semiconductor wafer encapsulant 86 Connection line

11 · 1Ι 00656.ptd Page 15

Claims (1)

6. Scope of Patent Application 1. A semiconductor package structure, including a semiconductor chip, defining a master-private interface and a plurality of contacts arranged on the active surface and a back surface, and having a complex-first-insulating layer covering the The semiconductor edge layer 'covers the semiconductor wafer with a plurality of first circuits' and is disposed on the 'road :: r connection line'. The connection is individually electrically = the first line is a gel to encapsulate the connection line. 2. According to the semiconductor package structure according to the item in the patent claim, a plurality of second lines are arranged on the first insulation layer: == between the active surface ... 1. The semiconductor package structure insulation layer according to item 1 of the scope of patent application is made of transparent material. Mingzhi 4. The semiconductor package structure according to item 3 of the scope of patent application, where the material is selected from the group of glass, pressed resin and sapphire =. m into 5. The semiconductor package structure according to item 1 of the scope of the patent application, including: — a solder mask is arranged on the second insulation layer, and it is rugged, and the blade is thin. 200423364 6. The scope of the patent application covers the First line. 6. According to the semiconductor package structure of the first patent application scope, a separate solder ball is arranged on the second insulation layer, and each of them is electrically ^ a hard number and a plurality of first lines. Connected to 7. A method for manufacturing a semiconductor package structure, including the following steps: Provide a wafer, define an active surface and a back surface, and have a semiconductor wafer with a plurality of pads arranged on the active surface and a plurality of cuts The wires are located between the semiconductor wafers; and on the active surface of the wafer, a plurality of metal ductile connections are formed to the pads; the first insulating layer covers the active surface of the semiconductor wafer; A cutting line is used to cut the back surface of the wafer to form a concave etched notch to expose the metal extension line; a second insulation layer is used to cover the back surface of the semiconductor wafer on the second insulation layer Configure a plurality of lines: road; through a plurality of connecting lines, electrically connect the line and the metal extension line with a sealing gel in the notch to encapsulate the connecting line: and a knife. This wafer is formed to form an individual semiconductor package structure. 8. The manufacturing method of semiconductor package structure according to item p of the patent scope, 00656.ptd page 17 200423364 6. Application scope of patent Where the first insulation layer is made of transparent material. 9. According to the scope of the patent application, the material of the sun and moon is a manufacturing method of 1 + conductor packaging structure, and the material f is in the group consisting of broken glass, acrylic resin and steel (saPPhlre). Elected. I. The method of manufacturing a semiconductor package structure according to item 7 of the above-mentioned patent scope 'further includes the following steps: Extraction:-A solder resist is disposed on the second insulating layer and partially covers the effective circuit. II. The manufacturing method of the semiconductor package structure according to item 7 of the scope of the patent application 'further includes the following steps: providing a plurality of solder balls, arranged on the second insulating layer, and individually electrically connecting to the plurality of lines. 12. A method for manufacturing a semiconductor package structure, comprising the following steps :: providing a wafer defining an active surface and a back surface, and having a plurality of semiconductor wafers, a plurality of pads disposed on the active surface, and A plurality of cutting lines are located between the semiconductor wafers; a first insulating layer covers the active surface of the semiconductor wafer; along the cutting lines, the back surface of the wafer is cut to form a concave σ; The notch is used to expose the semiconductor wafer on the wafer 6. The patent application scope of the pad; two: two f-edge layers covering the back surface of the semiconductor wafer; a plurality of lines are arranged on the first and second edge layers: the pad, a plurality of connection lines, electrical The circuit and the main encapsulation gel of the semiconductor chip are used to encapsulate the connection line: and cut.彳 Yen to form individual semiconductor package structures. 12. The manufacturing method of the semiconductor package structure according to item 12 of the Erli Scope, wherein the insulation layer is made of a transparent material. 14. According to the manufacturing method of the semiconductor package structure according to item 13 of the scope of the patent application, the transparent material is selected from the group consisting of glass, acrylic resin and steel (sapph i r e). 15. The method for manufacturing a semiconductor package structure according to item 12 of the scope of the patent application, further comprising the following steps. A solder resist layer is provided on the second insulation layer, and the second part of the circuit is partially covered. 16. The method for manufacturing a semiconductor package structure according to item 2 of the patent application scope, further including the following steps: k A, a plurality of solder balls, arranged on the second insulating layer, and individually electrically connected to the Plural lines. ,,9