JP4334397B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor chip packaging technique.

  In recent years, MCM (Multi Chip Module) has attracted attention as a new packaging technology. MCM implements a high-function module by incorporating a plurality of semiconductor chips in one package. There are many types of MCMs depending on how semiconductor chips are arranged. Among them, “stacked MCM” in which a plurality of semiconductor chips are stacked has recently attracted particular attention.

  An example of the structure of this stacked MCM is shown in FIG. The stacked MCM 200 is formed by stacking a plurality of semiconductor chips 204. A via hole 205 penetrating the semiconductor chip 204 is formed by laser processing, and a barrier metal 202 is formed on the side surface of the via hole 205 by a sputtering method or a CVD method. Thereafter, a conductive material is embedded in the via hole 205 by copper plating, thereby forming a wiring for connecting the semiconductor chips 204 and 204 disposed adjacent to each other in the vertical direction.

  Insulation between the semiconductor chips 204 is maintained by inserting a thermoplastic film 203. By repeatedly performing such a manufacturing process, a plurality of semiconductor chips 204 can be stacked. The lowermost semiconductor chip 204 is connected to an external circuit by attaching a conductive terminal 206.

The stacked MCM 200 can be manufactured by the above manufacturing process. The stacked MCM described above is disclosed in Patent Document 1.
JP-A-9-232503

  In order to manufacture the stacked MCM 200 described above, it is necessary to form a via hole having a diameter and depth of about several tens of μm and to embed a conductive material in the via hole. As a result, the laser processing machine for via hole processing, the barrier CVD apparatus for forming the barrier metal, and the copper plating apparatus for filling the via hole are expensive and have not been used in conventional semiconductor packaging. There was a problem that an apparatus was required and the manufacturing cost was high.

A semiconductor device according to the present invention includes a first semiconductor device and a second semiconductor device disposed on the first semiconductor device, and the first semiconductor device is formed on a first semiconductor chip. The first wiring and the second wiring formed through one insulating film, and the first semiconductor chip on which the first and second wirings are formed are bonded via an adhesive. A support substrate having an opening for exposing the second wiring; a second insulating film formed on a side surface and a back surface of the first semiconductor chip; and a back surface of the first wiring; A third wiring extending from the side surface portion to the back surface portion of the semiconductor chip so as to be in contact with the insulating film, and a protective film formed on the back surface portion of the semiconductor chip so as to cover the third wiring; A conductive terminal formed on the third wiring via the protective film, The second semiconductor device includes a second semiconductor chip and a conductive terminal formed on the back surface of the second semiconductor chip, and the conductive terminal of the second semiconductor device is the first semiconductor. It is connected to the second wiring through an opening of the device.
Further, the conductive terminal formed on the third wiring or the conductive terminal formed on the back surface of the second semiconductor device is a protruding electrode terminal.
Further, the protruding electrode terminal is a solder bump or a gold bump.
Further, the support substrate is a plate material made of any one of a glass substrate, a silicon substrate, and a plastic.
According to another aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: preparing a semiconductor wafer having a plurality of semiconductor chips on which a first wiring and a second wiring are formed via a first insulating film; A step of bonding a support substrate on the semiconductor wafer on which the wiring of 2 is formed via an adhesive, a step of etching boundary portions of the plurality of semiconductor chips from the back surface of the semiconductor wafer, and a semiconductor exposed by the etching A step of forming a second insulating film on the side surface portion and the back surface portion of the chip; and a back surface portion from the side surface portion of the semiconductor chip connected to the back surface of the first wiring and in contact with the second insulating film. A step of forming a third wiring extending to the semiconductor chip, a step of forming a protective film on the back surface of the semiconductor chip so as to cover the third wiring, and the third wiring on the third wiring via the protective film Form a conductive terminal A step of forming an opening exposing the second wiring on the support substrate, and a step of dividing the semiconductor substrate into a plurality of semiconductor chips along the boundary portion. The second semiconductor chip is stacked on the first semiconductor chip by connecting the conductive terminal of the second semiconductor chip to the second wiring exposed through the opening of the semiconductor chip.
The method further comprises a step of cutting the surface of the support substrate after the step of forming the conductive terminal on the third wiring and before the step of forming the opening in the support substrate. .
Further, the step of scraping the surface of the support substrate is a step of dropping an etching solution on the surface of the support substrate and rotating the support substrate.
Furthermore, the method includes a step of forming a plating layer on the second wiring after the step of forming the opening exposing the second wiring on the support substrate.

  According to the present invention, it is possible to manufacture a stacked MCM at a low manufacturing cost without using an expensive apparatus.

  Next, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 1, a semiconductor wafer 1a is prepared. The semiconductor wafer 1a is cut and separated into a plurality of semiconductor chips 1 in a process described later. These semiconductor chips 1 are, for example, CCD image sensors and semiconductor memory chips, and are formed by a semiconductor wafer process. A plurality of first wirings 3A and a plurality of second wirings 3B are simultaneously formed on the surface of the semiconductor wafer 1a via the insulating film 2. The first wiring 3A is formed with a predetermined gap on both sides of a boundary S for cutting and separating the semiconductor wafer 1a into a plurality of semiconductor chips 1. The boundary S is called a dicing line or a scribe line.

  Here, the first wiring 3A is a pad extended from the normal bonding pad position of the semiconductor chip 1 to the vicinity of the boundary S. The plurality of second wirings 3B are conductive pads that are electrically connected to conductive terminals of other semiconductor devices stacked on the semiconductor chip 1 in a later step.

  Subsequently, the glass substrate 4 as a support is bonded to the surface of the semiconductor wafer 1a on which the first wiring 3A and the second wiring 3B are formed using the epoxy resin layer 5 as an adhesive. Here, a glass substrate is used as a support and an epoxy resin layer is used as an adhesive. However, in addition to a silicon substrate or a plastic plate, a tape or sheet may be used as a support. For these supports, an appropriate adhesive may be selected.

Next, as shown in FIG. 2, the surface of the semiconductor wafer 1a to which the glass substrate 4 is not bonded, that is, the back surface thereof is back-ground to reduce the thickness of the semiconductor wafer 1a. On the back surface of the back-ground semiconductor wafer 1a, scratches are generated, and irregularities having a width and a depth of about several μm are formed. To reduce this, by using a silicon etching solution with a high selectivity with respect to silicon (hereinafter Si) which is the material of the semiconductor wafer 1a than the silicon oxide film (hereinafter SiO ₂₎ which is a material of the insulating film 2 Wet etching is performed. As such a silicon etching solution, for example, a mixed solution of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid and 37.5% water is suitable.

  Next, as shown in FIG. 3, isotropic etching is performed on the back surface of the semiconductor wafer 1a using a resist pattern (not shown) provided with openings along the boundary S as a mask. Thereby, a groove is formed at the boundary S, and the insulating film 2 is partially exposed. This etching may be performed by either dry etching or wet etching. By this etching, the semiconductor wafer 1a is cut into a plurality of semiconductor chips 1, but is supported by the glass substrate 4 and maintains the form of the semiconductor wafer 1a.

  On the back surface of the etched semiconductor wafer 1a, there are irregularities, residues, and foreign matters, and corners as shown by broken circles a and b in FIG. 3 are formed. Therefore, as shown in FIG. 4, wet etching is performed to remove residues and foreign matters and further round the corners. Thereby, the corners as shown by the broken circles a and b in FIG. 3 have a smooth shape as shown by the broken circles a and b in FIG.

  Next, as shown in FIG. 5, an insulating film 7 is deposited on the back surfaces of the plurality of semiconductor chips 1 and the etched side surfaces. The insulating film 7 is, for example, a silane-based oxide film.

  Next, as shown in FIG. 6, a resist (not shown) is applied to the back surface of the semiconductor chip and patterned. Using the resist film as a mask, the insulating film 7 and the insulating film 2 are etched to expose the end portion of the first wiring 3A.

  Next, the buffer member 8 having flexibility is formed at a position overlapping with a position where the conductive terminal 11 is formed later. Although the buffer member 8 has a function of absorbing a force applied to the conductive terminal 11 and relieving stress at the time of joining the conductive terminal 11, it is not always necessary. Next, a third wiring 9 that covers the insulating film 7, the buffer member 8, and the exposed portion of the first wiring 3A is formed. Thereby, the first wiring 3A and the third wiring 9 are electrically connected.

  Next, as shown in FIG. 7, a resist (not shown) is applied to the back side of the semiconductor chip 1, and a pattern is formed so as to open a portion along the boundary S of the resist. Then, etching is performed using the resist as a mask, and the third wiring 9 near the boundary S is removed. Although not shown, after the third wiring 9 is formed, an electroless plating process may be performed, and the surface of the third wiring 9 may be plated with Ni—Au.

  Next, the protective film 10 is formed on the back surface side of the semiconductor chip 1. In order to form the protective film 10, a thermosetting organic resin is dropped from above with the back surface side of the semiconductor chip 1 facing upward, and a plurality of semiconductor chips 1 are provided, and the glass substrate 4 is bonded. The manufactured semiconductor wafer 1a is rotated. The organic resin spreads on the surface of the semiconductor wafer 1a due to the centrifugal force generated by this rotation. Thereby, the protective film 10 can be formed on the surface of the third wiring 9.

  Next, as shown in FIG. 8, the portion of the protective film 10 where the conductive terminal 11 is to be formed is selectively removed by etching using a resist mask to expose the third wiring 9, which is exposed. A conductive terminal 11 is formed on the third wiring 9 in contact therewith. The conductive terminal 11 can be formed of a protruding electrode terminal such as a solder bump or a gold bump, for example. The thickness of the conductive terminal 11 is 160 μm when using solder bumps, but can be reduced to several μm to several tens of μm when using gold bumps. A plurality of conductive terminals 11 having the same structure on the back surface of the semiconductor chip 1 can be provided to constitute a ball grid array.

  Next, the surface of the glass substrate 4 is scraped to reduce its thickness. Thereby, the processing time for forming an opening part in the glass substrate 4 mentioned later can be shortened. The thickness of the glass substrate is suitably 50 μm to 100 μm. As a method of thinning the glass substrate 4, (1) a method of grinding the glass substrate 4 with a back grinding apparatus, (2) a method of polishing the glass substrate 4 with a CMP apparatus, and (3) a glass substrate such as resist coating. A method of etching the glass substrate 4 by dropping the etching solution on the substrate 4 and rotating the semiconductor wafer 1a to which the glass substrate 4 is bonded to spread the etching solution over the entire glass substrate 4; (4) dry etching And a method of etching the glass substrate 4 using the above. In addition, in this invention, although the process which thins the glass substrate 4 is provided, use of the support body which consists of a board | plate material, tape, or a sheet-like thing of predetermined thickness from the beginning is not restrict | limited.

  Next, as shown in FIG. 10, the glass substrate 4 and the resin layer 5 on a part of the second wiring 3B are removed by etching or the like to form an opening 12 that exposes the surface of the second wiring 3B. . In contrast, the glass substrate 4 may be thinned after the opening 12 is formed, but the processing time for forming the opening 12 becomes long. Next, the plating layer 13 is formed on the surface of the second wiring 3 </ b> B exposed through the opening 12. The plating layer 13 constitutes a part of the second wiring 3B. For example, the plating layer 13 is formed by laminating a Ni plating layer and an Au plating layer.

  Next, as shown in FIG. 12, the semiconductor wafer 1 a is cut along the boundary S and separated into a plurality of semiconductor chips 1 using a dicing apparatus. At this time, the glass substrate 4, the resin layer 5, and the protective film 10 are cut along the boundary S. Thereby, the BGA type semiconductor device 100 incorporating the semiconductor chip 1a is completed. According to this BGA type semiconductor device 100, since only one glass substrate 4 supporting the semiconductor chip 1 is bonded to the semiconductor chip 1 and the glass substrate 4 is thinly processed, the entire package can be thinned. it can. Further, since the glass substrate 4 is formed with an opening 12 exposing the second wiring 3B of the semiconductor chip 1, a necessary electrical connection with an external electronic circuit can be obtained through the opening 12. Can do.

  FIG. 13 is a cross-sectional view showing the structure of a stacked MCM as an example of such an electrical connection structure. In this stacked MCM, a first semiconductor device 100a and a second semiconductor device 100b are stacked. The first semiconductor device 100a and the second semiconductor device 100b have the same structure as the semiconductor device 100 described above. Through the opening 12, the conductive terminal 11B of the second semiconductor device 100B is electrically and mechanically connected to the second wiring 3B of the first semiconductor device 100a. When the connection strength is insufficient, an organic adhesive such as underfill may be used as an auxiliary. Further, the number of semiconductor devices to be stacked can be selected as necessary.

It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is sectional drawing of the manufacturing method of the semiconductor device which concerns on embodiment of this invention. It is a schematic diagram of the cross section of the conventional MCM type semiconductor device.

Claims (9)

A first semiconductor device, and a second semiconductor device disposed on the first semiconductor device,
The first semiconductor device includes a first wiring and a second wiring formed on a first semiconductor chip via a first insulating film,
A support substrate having an opening that is bonded to the first semiconductor chip on which the first and second wirings are formed via an adhesive and exposes the second wiring;
A second insulating film formed on a side surface and a back surface of the first semiconductor chip;
A third wiring connected to the back surface of the first wiring and extending from the side surface portion of the semiconductor chip to the back surface portion so as to be in contact with the second insulating film;
A protective film formed on the back surface of the semiconductor chip so as to cover the third wiring;
A conductive terminal formed on the third wiring via the protective film,
The second semiconductor device includes a second semiconductor chip and a conductive terminal formed on a back surface of the second semiconductor chip, and the conductive terminal of the second semiconductor device is the first semiconductor. A semiconductor device, wherein the semiconductor device is connected to the second wiring through an opening of the device. 2. The semiconductor device according to claim 1, wherein the conductive terminal formed on the third wiring or the conductive terminal formed on the back surface of the second semiconductor device is a protruding electrode terminal.   The semiconductor device according to claim 2, wherein the protruding electrode terminal is a solder bump or a gold bump. 4. The semiconductor device according to claim 1, wherein the support substrate is a plate material made of any one of a glass substrate, a silicon substrate, and a plastic. Preparing a semiconductor wafer having a plurality of semiconductor chips on which a first wiring and a second wiring are formed via a first insulating film;
Bonding a support substrate on the semiconductor wafer on which the first and second wirings are formed via an adhesive;
Etching a boundary portion of the plurality of semiconductor chips from the back surface of the semiconductor wafer;
Forming a second insulating film on the side and back surfaces of the semiconductor chip exposed by the etching;
Forming a third wiring connected to the back surface of the first wiring and extending from the side surface of the semiconductor chip to the back surface so as to be in contact with the second insulating film;
Forming a protective film on the back surface of the semiconductor chip so as to cover the third wiring;
Forming a conductive terminal on the third wiring through the protective film;
Forming an opening exposing the second wiring on the support substrate;
Dividing the plurality of semiconductor chips along the boundary portion,
The second semiconductor chip is stacked on the first semiconductor chip by connecting the conductive terminal of the second semiconductor chip to the second wiring exposed through the opening of the divided first semiconductor chip. A method of manufacturing a semiconductor device.   The method of claim 1, further comprising a step of shaving a surface of the support substrate after the step of forming a conductive terminal on the third wiring and before the step of forming an opening in the support substrate. 6. A method for manufacturing a semiconductor device according to 5.   The method for manufacturing a semiconductor device according to claim 6, wherein the step of scraping the surface of the support substrate is a step of dropping an etching solution on the surface of the support substrate and rotating the support substrate.   8. The method according to claim 5, further comprising a step of forming a plating layer on the second wiring after the step of forming an opening exposing the second wiring on the support substrate. 2. A method for manufacturing a semiconductor device according to item 1. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the support substrate is a plate material made of any one of a glass substrate, a silicon substrate, and a plastic.

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