JP2004343088A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To manufacture a stacked MCM at a low production cost without using an expensive apparatus. <P>SOLUTION: A first wiring 3A and a second wiring 3B are formed on a front face of a semiconductor chip 1 of a first semiconductor device 100a through an insulation film 2. A glass substrate 4 with an aperture 12 for exposing the second wiring 3B is glued on the front face of the semiconductor chip 1 with the first wiring 3A and the second wiring 3B. A third wiring 9 is extended from a back face of the semiconductor chip 1 through an insulation film 7 to a side face of the chip 1 and connected to the first wiring 3A. A conductive terminal 11B of another semiconductor device 100b is connected to the second wiring 3B through the aperture 12. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor chip packaging technique.

  In recent years, an MCM (Multi Chip Module) has attracted attention as a new package technology. The MCM implements a high-performance module by incorporating a plurality of semiconductor chips in one package. There are many types of MCMs depending on how semiconductor chips are arranged. Among them, a “laminated MCM” formed by laminating a plurality of semiconductor chips has recently received particular attention.

  FIG. 14 shows an example of the structure of the stacked MCM. The stacked MCM 200 is obtained by stacking a plurality of semiconductor chips 204. A via hole 205 penetrating the semiconductor chip 204 is formed by laser processing, and a barrier metal 202 is formed on a side surface of the via hole 205 by a sputtering method or a CVD method. Thereafter, a conductive material is buried in the via hole 205 by copper plating to form a wiring for connecting the semiconductor chips 204, 204 arranged vertically above and below.

  The insulation between the semiconductor chips 204 is maintained by inserting the thermoplastic film 203. By repeating such a manufacturing process, a plurality of semiconductor chips 204 can be stacked. The lowermost semiconductor chip 204 is connected to an external circuit by attaching a conductive terminal 206 thereto.

With the above manufacturing steps, the laminated MCM 200 can be manufactured. The above-described stacked MCM is disclosed in Patent Document 1.
JP-A-9-232503

  In order to manufacture the above-described stacked MCM 200, it is necessary to form a via hole having a diameter and a depth of about several tens of μm and to embed a conductive material in the via hole. As a result, expensive lasers not used in conventional semiconductor packaging, such as laser processing machines for processing via holes, barrier CVD apparatuses for forming barrier metal films, and copper plating apparatuses for filling via holes. There is a problem that an apparatus is required and the manufacturing cost is increased.

  In the semiconductor device of the present invention, a first wiring and a second wiring are formed on a surface of a semiconductor chip via a first insulating film. A support having an opening exposing the second wiring is bonded to the surface of the semiconductor chip on which the first and second wirings are formed. The third wiring extends from the back surface of the semiconductor chip to the side surface of the semiconductor chip via the second insulating film, and is connected to the first wiring.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to manufacture laminated MCM at low manufacturing cost, without using an expensive apparatus.

  Next, a semiconductor device and a method for manufacturing the same according to an embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 1, a semiconductor wafer 1a is prepared. The semiconductor wafer 1a is cut and separated into a plurality of semiconductor chips 1 in a process described later. The semiconductor chips 1 are, for example, CCD image sensors or semiconductor memory chips, and are formed by a semiconductor wafer process. A plurality of first wirings 3A and a plurality of second wirings 3B are simultaneously formed on the surface of the semiconductor wafer 1a via the insulating film 2. The first wiring 3A is formed with a predetermined gap on both sides of a boundary S for cutting and separating the semiconductor wafer 1a into a plurality of semiconductor chips 1. The boundary S is called a dicing line or a scribe line.

  Here, the first wiring 3A is a pad extended from the normal bonding pad position of the semiconductor chip 1 to the vicinity of the boundary S. The plurality of second wirings 3B are conductive pads that are electrically connected to conductive terminals of another semiconductor device stacked on the semiconductor chip 1 in a later step.

  Subsequently, a glass substrate 4 as a support is bonded to the surface of the semiconductor wafer 1a on which the first wiring 3A and the second wiring 3B are formed, using the epoxy resin layer 5 as an adhesive. Here, a glass substrate is used as a support, and an epoxy resin layer is used as an adhesive, but a tape or a sheet-like material may be used as a support in addition to a silicon substrate or a plastic plate. In this case, an appropriate adhesive may be selected for these supports.

Next, as shown in FIG. 2, the surface of the semiconductor wafer 1a to which the glass substrate 4 is not bonded, that is, the back surface thereof is back-ground, and the thickness of the semiconductor wafer 1a is reduced. On the back surface of the back-ground semiconductor wafer 1a, scratches occur, and irregularities having a width and depth of about several μm are formed. To reduce this, a silicon etchant having a higher selectivity to silicon (hereinafter, Si) as a material of the semiconductor wafer 1a than a silicon oxide film (hereinafter, SiO ₂ ) as a material of the insulating film 2 is used. Perform wet etching. As such a silicon etching solution, for example, a mixed solution of 2.5% hydrofluoric acid, 50% nitric acid, 10% acetic acid, and 37.5% water is suitable.

  Next, as shown in FIG. 3, isotropic etching is performed on the back surface of the semiconductor wafer 1a using a resist pattern (not shown) provided with an opening along the boundary S as a mask. As a result, a groove is formed at the boundary S, and the insulating film 2 is partially exposed. Note that this etching may be performed by either dry etching or wet etching. Although the semiconductor wafer 1a is cut into a plurality of semiconductor chips 1 by this etching, it is supported by the glass substrate 4 and maintains the form of the semiconductor wafer 1a.

  On the back surface of the etched semiconductor wafer 1a, there are irregularities, residues, and foreign substances, and corners are formed as shown by dashed circles a and b in FIG. Therefore, as shown in FIG. 4, wet etching is performed to remove residues and foreign matters and to round corners. Thus, the corners as shown by the dashed circles a and b in FIG. 3 have a smooth shape as shown by the dashed circles a and b in FIG.

  Next, as shown in FIG. 5, an insulating film 7 is applied to the back surfaces of the plurality of semiconductor chips 1 and the etched side surfaces. The insulating film 7 is, for example, a silane-based oxide film.

  Next, as shown in FIG. 6, a resist (not shown) is applied to the back surface of the semiconductor chip, and patterning is performed. Using the resist film as a mask, the insulating film 7 and the insulating film 2 are etched to expose the end of the first wiring 3A.

  Next, a flexible buffer member 8 is formed at a position overlapping a position where the conductive terminal 11 is to be formed later. The buffer member 8 has a function of absorbing the force applied to the conductive terminal 11 and relieving the stress at the time of joining the conductive terminal 11, but is not always necessary. Next, a third wiring 9 covering the exposed portions of the insulating film 7, the buffer member 8, and the first wiring 3A is formed. Thus, the first wiring 3A and the third wiring 9 are electrically connected.

  Next, as shown in FIG. 7, a resist (not shown) is applied to the back surface side of the semiconductor chip 1, and a pattern is formed so as to open a portion along the boundary S of the resist. Then, etching is performed using the resist as a mask to remove the third wiring 9 near the boundary S. Although not shown, an electroless plating process may be performed after the formation of the third wiring 9, and the surface of the third wiring 9 may be plated with Ni—Au.

  Next, a protective film 10 is formed on the back surface side of the semiconductor chip 1. In order to form the protective film 10, a thermosetting organic resin is dropped from above with the back side of the semiconductor chip 1 facing upward, and a plurality of semiconductor chips 1 are provided. The rotated semiconductor wafer 1a is rotated. Due to the centrifugal force generated by this rotation, the organic resin spreads on the surface of the semiconductor wafer 1a. Thereby, the protective film 10 can be formed on the surface of the third wiring 9.

  Next, as shown in FIG. 8, the portion of the protective film 10 where the conductive terminal 11 is to be formed is selectively removed by etching using a resist mask to expose the third wiring 9, and the exposed portion of the third wiring 9 is exposed. The conductive terminal 11 that contacts the third wiring 9 is formed. The conductive terminal 11 can be formed by, for example, a protruding electrode terminal such as a solder bump or a gold bump. The thickness of the conductive terminal 11 is 160 μm when using solder bumps, but can be reduced to several μm to several tens μm when using gold bumps. A plurality of conductive terminals 11 having the same structure on the back surface of the semiconductor chip 1 can be provided to form a ball grid array.

  Next, the thickness of the glass substrate 4 is reduced by shaving the surface. Thereby, a processing time for forming an opening in the glass substrate 4 described later can be reduced. The thickness of the glass substrate is suitably from 50 μm to 100 μm. The method of thinning the glass substrate 4 includes (1) a method of grinding the glass substrate 4 with a back grinding device, (2) a method of polishing the glass substrate 4 with a CMP device, and (3) a method of coating a glass substrate with a resist. A method of etching the glass substrate 4 by dropping an etchant on the glass substrate 4 and rotating the semiconductor wafer 1a to which the glass substrate 4 is adhered, thereby spreading the etchant over the entire glass substrate 4; (4) dry etching Is used to etch the glass substrate 4. In the present invention, a step of thinning the glass substrate 4 is provided, but the use of a plate, a tape or a sheet-like support having a predetermined thickness from the beginning is not limited.

  Next, as shown in FIG. 10, the glass substrate 4 and the resin layer 5 on a part of the second wiring 3B are removed by etching or the like to form an opening 12 exposing the surface of the second wiring 3B. . Conversely, after the opening 12 is formed, the glass substrate 4 may be shaved to be thinner, but the processing time for forming the opening 12 becomes longer. Next, a plating layer 13 is formed on the surface of the second wiring 3B exposed by the opening 12. The plating layer 13 forms a part of the second wiring 3B. The plating layer 13 is formed, for example, by laminating a Ni plating layer and an Au plating layer.

  Next, as shown in FIG. 12, the semiconductor wafer 1 a is cut along the boundary S using a dicing apparatus, and separated into a plurality of semiconductor chips 1. At this time, the glass substrate 4, the resin layer 5, and the protective film 10 are cut along the boundary S. Thus, the BGA type semiconductor device 100 incorporating the semiconductor chip 1a is completed. According to the BGA type semiconductor device 100, only one glass substrate 4 supporting the semiconductor chip 1 is bonded to the semiconductor chip 1, and the glass substrate 4 is processed to be thin, so that the entire package can be thinned. it can. Since the glass substrate 4 has an opening 12 exposing the second wiring 3B of the semiconductor chip 1, it is possible to obtain a necessary electrical connection with an external electronic circuit through the opening 12. Can be.

  FIG. 13 is a cross-sectional view showing the structure of a stacked MCM as an example of such an electrical connection structure. In this stacked MCM, a first semiconductor device 100a and a second semiconductor device 100b are stacked. The first semiconductor device 100a and the second semiconductor device 100b have the same structure as the semiconductor device 100 described above. The conductive terminal 11B of the second semiconductor device 100B is electrically and mechanically connected to the second wiring 3B of the first semiconductor device 100a through the opening 12. If the connection strength is insufficient, an organic adhesive such as an underfill may be used as an auxiliary. The number of semiconductor devices to be stacked can be selected as needed.

FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. FIG. 4 is a cross-sectional view of the method for manufacturing the semiconductor device according to the embodiment of the present invention. It is a schematic diagram of the section of the conventional MCM type semiconductor device.

Claims (12)

A first wiring and a second wiring formed on the surface of the semiconductor chip via a first insulating film;
Bonded to a surface of the semiconductor chip on which the first and second wirings are formed,
A support having an opening exposing the second wiring;
A third wiring extending from a back surface of the semiconductor chip to a side surface of the semiconductor chip via a second insulating film and connected to the first wiring. A first semiconductor device, and a second semiconductor device disposed on the first semiconductor device;
The first semiconductor device includes a first wiring and a second wiring formed on a surface of a first semiconductor chip, and a surface of the first semiconductor chip on which the first and second wirings are formed. A support having an opening that exposes the second wiring and that is bonded to the third wiring and extends from a back surface of the first semiconductor chip to a side surface of the semiconductor chip and is connected to the first wiring; With wiring,
The second semiconductor device includes a second semiconductor chip, and a conductive terminal formed on a back surface of the second semiconductor chip, wherein the conductive terminal of the second semiconductor device is the first semiconductor. A semiconductor device which is connected to the second wiring through an opening of the device. The semiconductor device according to claim 1, further comprising a conductive terminal formed on the third wiring. 4. The semiconductor device according to claim 3, wherein the conductive terminal is a protruding electrode terminal. The semiconductor device according to claim 4, wherein the protruding electrode terminal is a solder bump or a gold bump. Preparing a semiconductor wafer having a plurality of semiconductor chips on which a first wiring and a second wiring are formed via a first insulating film;
Adhering a support to the surface of the semiconductor chip on which the first and second wirings are formed, extending from a back surface of the semiconductor chip to a side surface of the semiconductor chip via a second insulating film, Forming a third wiring connected to the first wiring;
Forming an opening exposing the second wiring in the support. 7. The method according to claim 6, further comprising a step of shaving the surface of the support. The method of manufacturing a semiconductor device according to claim 7, wherein the step of shaving the surface of the support is a step of dropping an etchant on the surface of the support and rotating the support. 7. The method according to claim 6, further comprising a step of cutting and separating the semiconductor wafer into a plurality of semiconductor chips. 7. The method according to claim 6, further comprising a step of forming a conductive terminal on the third wiring. 7. The semiconductor device according to claim 6, further comprising a step of forming a plating layer on the second wiring after the step of forming an opening exposing the second wiring in the support. Method. The method of manufacturing a semiconductor device according to claim 9, further comprising connecting a conductive terminal of another semiconductor device to the second wiring through the opening.

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