SU1647887A2 - Counting device with variable scaling factor - Google Patents

Abstract

The invention relates to a pulse technique and can be used in counters with a programmable counting factor and the number of bits. The purpose of the invention is to expand the scope. The counter with a variable counting coefficient contains a t-bit binary counter 1, the clock input of which is connected to the clock input 2 of the device, the first inputs 3i - Control C, outputs 4i - 4m (nm, n 1, 2, ...), control Repeaters 5i - 5P and shaper 6 delayed short pulses 2 Il.

Description

The invention relates to a pulse technique and can be used in counters with a programmable snow ratio and the number of bits.

The aim of the invention is to expand the field of application of the device.

FIG. Figures 1 and 2 show the block diagram of the counting device with a variable counting factor; examples of

A counting device with a variable counting coefficient contains a t-bit binary counter 1, the clock input of which is connected to the clock input 2 of the device, the first inputs 3i are control terminals, the outputs 4i are 4m (nm, n 1, 2, ...) controlled repeaters 5i - 5n and shaper 6 delayed short pulses, the output of which is connected to the enable input of the binary counter, the outputs n of the first bits of which are connected to the information inputs of the controlled repeater 5i - 5P, the outputs of which are connected to the information inputs of the corresponding bits binary counter. The outputs of the higher bits are connected to the information inputs of the corresponding m - n bits.

binary counter 1 The delayed pulse shaper 6 has a dynamic start input 7, and the device outputs are connected to the outputs of controlled repeaters 5 and to the outputs of the higher bits of the binary counter. Additional dynamic input 8 of the imaging unit 6 is connected to the input R of the zero setting of the binary counter 1.

The shaper 6 of the delayed pulses is designed in such a way that from its output to the input V of the preliminary recording of the binary counter 1 short pulses are received, appearing both after each of the clock pulses fed to the first input of the imager 6 and after each of the zero setting pulses at his second entrance. The corresponding values of m and r1, which determine the delay time of the output short pulse of shaper 5 relative to the leading edge of each clock pulse arriving at its first input, and the trailing edge of each of the zero setting pulses fed to the second driver input, respectively, are given by

SP

with

with

five

00

with

Vj

TO

rc-t-GP (1)

, (2)

where ts is the maximum delay time of a signal from the clock input of counter 1 to any of its outputs;

rp is the maximum signal delay time in controlled repeaters 5;

T is the minimum permissible period of repetition of clock pulses.

Consider the operation of the device with specific examples.

Suppose that all controlled repeaters 5 devices are in the on state, i.e. the output signals of all n minor bits of counter 1 through the corresponding controlled repeaters 5 are fed to its data inputs of the same name. Since the outputs and inputs of all the higher bits of counter 1 are also connected to each other, short pulses arriving at the input V of counter 1 cannot change the state of any of its bits. Therefore, in this case the counter 1 operates as a normal binary counter both in the counting mode and in the zero setting mode.

In this case, the input 7 of the imager can be connected both to the clock input C of the counter 1 and to the output of its low-order bit.

In order for a counter with a variable counting factor to have a width m - A (A can take any value from 1 to n), it is necessary to disable all those lower bits of the device (more precisely, the corresponding controlled repeaters 5) that are built on the bits of the counter 1, having weights of 2 °, 21, 2, leaving included

all other controlled bits of the device, built on bits with weights of 2A, 2,. , 2n 1

Consider the operation of the device when A 2, i.e. in the case when the low-order bits with weights of 2 ° and 21 are disconnected. This means that the control inputs of the controlled repeaters 5 of the first two low-order bits of the device receive a logic level that takes the repeaters to an off state. In this case, the information inputs of the first two lower bits of counter 1 from the outputs of the corresponding repeaters 5 receive the level of a logical unit. Let us analyze how the device works in this state in various modes of operation in the counting mode and in the installation mode.

0

five

0

five

0

five

0

five

0

five

Suppose that the device unit zero input level is a logical unit level. Then the level zero level is set at all the outputs of counter 1. After time hp after that, the information inputs of all bits of counter 1 (except the first two lower bits) receive a logic zero level, and the information inputs of the first two lower bits (as noted for case A-2) have a logical one level. If now the input voltage at the input of the device zero setting goes to the logical zero level, then according to

expression (2) after a time after that a short pulse repeats at the output of shaper 6 This pulse arriving at the input V of counter 1 records the level of a logical unit in its first two lower bits, leaving the level of logical zero unchanged in all other bits counter 1.

We will show that after setting the initial state of counter 1 in this way, it is not necessary to feed preparatory pulses to the input of clock pulses of the device.

Indeed, the very first pulse arriving at the input 2 of the device transfers the discharge of the counter 1 with the weight coefficient 2 to the state of logical 1.

The low bits of counter 1 with weights 2 and 2 go to the zero state for a short time, and then (at time r after the leading edge of the clock pulse) the output level of these bits is set to the level of the logical unit, and the device returns to the ready state for work in counting mode. In this case, the device starts up as a start-up section, built on the discharge of counter 1 with a weighting factor of 2, i.e. the device works with a counting factor of 2.

Similarly, the device operates with other values of the number A, which determines the number of disconnected bits.

Thus, it is possible to initialize the meter.

Claims (1)

Claims of the invention The counting device with a variable counting factor according to the auth. Fsfe 1531212, characterized in that, in order to expand the scope of application, the delayed short pulse shaper is made with an additional dynamic start input, which is connected to the input reset the counter and the additional control input of the device, and the dynamic start input of the driver short delayed pulses connected to the clock input of the counter or the output of his youngest bit.