SU1140233A1 - Pulse sequence generator - Google Patents

Abstract

An IMMULAR SEQUENCE GENERATOR, comprising a generator, of a reference frequency, the output of which is connected to a counting input of a frequency divider, characterized in that, in order to improve speed, a pulse counter, an OR-NOT element, and a decoder are entered, . The ment OR is NOT connected to the reset input of the frequency divider, the outputs of which are connected to the inputs of the depigraphor, the output of which is connected to the counting input of the pulse counter, and the input of the gating of the decoder is connected to the output of the reference frequency generator.

Description

The invention relates to a pulse technique and can be used in automation devices, tracking systems and in computer technology, as well as in control systems for stepper motors. A pulse generator is known that contains two control triggers, AND elements, OR elements, a delay line, a register, and a Cl3 reversible counter. The disadvantage of this generator is the low speed and nonlinearity of the generated frequency versus the control code. The closest to the proposed technical entity is a device for forming a series of pulses, containing a pulse generator, the output of which is connected via a serially connected controlled divider and trigger to the program control unit and to the first input of the element I, the second input of which is connected to the output The pulse generator outputs of the software control unit are connected to the inputs of the controlled divider C2. However, this device is characterized by a large delay in the formation of the first pulse of the stack, since after each installation of the new control code value in the program control unit, the first impulse at the output of the element I appears alternately in time equal to the pulse generator frequency period multiplied by division of the controlled divider. The aim of the invention is to increase the speed of the generator. The goal is achieved by the fact that a pulse counter, an OR-NOT element and a decoder are entered into the pulse sequence generator, which contains the reference frequency generator, the output of which is connected to the counting input of the frequency divider, and the pulse counter outputs are not connected to the reset input frequency divider, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the counting input of the pulse counter, and the gate input of the decoder is connected to the output of the reference frequency generator. The drawing shows the functional diagram of the pulse sequence generator. The pulse sequence generator contains a pulse counter 1, an OR-NOT 2 element, a frequency divider 3, a decoder 4, a reference frequency generator 5, and a clock frequency bus 6, a control code bus 7, and the information inputs of counter 1 are connected to bus 7, and the write input to the clock frequency bus 6, the outputs of the pulse counter 1 are connected to the inputs of the element OR NOT 2, the output of which is connected to the reset input of the frequency divider 3, the counting input of which and the reset input of the decoder 4 are connected to the output frequency generator 5, and exits divides L 3 frequency bitwise connected to inputs of the decoder 4, the output of which is the output of the generator. The device works as follows. Upon receipt of the next clock pulse frequency, bus 6 records the value of the control code in the pulse counter 1 operating in the pulse reading mode. If the value of the control code is different from zero, then at one or several outputs of the pulse counter 1 a high potential appears (logical unit), which through the OR-NOT element. 2 arrives at the reset input of the 3-frequency divider, thereby removing the forced zeroing of the divider 3 frequencies. The pulses of the reference frequency from the generator 5 are fed to the counting input of the divider 3 frequencies and to one of the inputs of the decoder 4. The divider 3 frequencies divides the reference frequency to the required frequency value. Decoder 4 selects a second reference frequency pulse (deciphering of which is due to possible clock and reference frequency non-synchronization), which is fed to the counting input of pulse counter 1 operating in the subtraction mode and decreasing the code value recorded in pulse counter 1 by one. After generating the number of pulses equal to the number recorded in the pulse counter 1, all its bits are set to the zero state, thereby prohibiting the further formation of output pulses, since the divider 3 frequencies are kept in the zero position. In this generator, the number of pulses in the clock period is always

E 11402334

strictly equal to the value controlling higher speed,

code, and the delay in forming the output - that is. reduced response time for upg

of the pulse can be reduced to the -fractive effect of the codes, and the negligibly small magnitude of the chosen frequency (the number of pulses

the value of the reference frequency. The period of the clock frequency is. Thus, the proposed genetically depends on the control

Ratio but Comparison with. Known obla-code.

Claims (1)

An IMMULATIVE SEQUENCE GENERATOR, comprising a reference frequency generator, the output of which is connected to a counting input of a frequency divider, characterized in that, in order to improve performance, a pulse counter, an OR-HE element and a decoder are introduced, and the pulse counter outputs through an electronic . OR-HE is connected to the reset input of the frequency divider, the outputs of which are connected to the inputs of the decoder, the output of which is connected to the counting input of the pulse counter, and the gating input of the decoder is connected to the output of the reference frequency generator. 1 1140233 2