SU1136161A1 - Microprogram control unit - Google Patents

Abstract

MICROPROGRAMMAN CONTROL DEVICE containing a microinstructor memory block, microinstructions register, address register, condition checker, clock generator, block register group of elements And the first And element whose output is connected to the installation input in "1 register of blocking and to the register recording input microinstructions, the group of outputs of the operation code of which is the first group of control outputs of the device, the outputs of the microoperations code of the register of microcommands are connected to the first direct inputs of the elements AND group, the stroke of the i-ro element of the AND group (i 1,2, ...., (p-1), where p is the width of the micro-operations code) is connected to the i-th inverse input of the first element I, with the i-th information input the lock register and with inverse inputs with (i + l) -ro on the n-th element of the AND group and is the i-th control output of the second group of the device, the output of the n-th element of the AND group is connected to the n-th inverse input of the first element And, with the nth information input of the lock register, it is the nth control output of the second group of the device, J, and the output (J 1,2, ..., n) of the lock register is connected to the second the direct input of the j-ro element AND group ,, group of outputs of the microcode register address code is connected to the first group of inputs of the condition checker, the second group of inputs of which is a group of logical condition inputs of the device; group of outputs of the condition checker is connected to the group of information inputs of the address register , the group of outputs of which is connected to the group of address inputs of the microinstructor memory block, the group of outputs of which is connected to the group of information inputs of the register of microinstructions, the input of which is set to zero Connected to the installation input in the "About address register" and is the input to the initial installation of the device, characterized in that, in order to extend the functionality of the device by implementing a variable tact of operation under logical conditions, it contains the second and third elements AND, the controlled frequency divider pulses and the first and second groups of the NAND elements, the first inputs of the AND – NOT elements of the first group and the first direct inputs of the AND – NE elements of the second group are connected to the output of the second AND element, the inverse input of which is It is connected to the output of a controlled pulse frequency divider, the clock input of which is connected to the output of the clock pulse generator and to the first input of the third And element, the remaining inputs of which are connected to the outputs of the AND –– elements of the first and second O5 groups and to the control inputs of the controlled Divider pulse frequency, the reset input of which is connected to the output of the third O5 of its element I, the input of the record of the address register and the synchronization input of the lock register, the information inputs of which are connected to the second inputs of the elements AND – H The E of the first group and the second direct inputs of the elements of the NAND of the second group, the third inputs of the elements of the NAND of the first group and the inverse inputs of the elements of the NAND of the second group are the inputs of the logical conditions of the device group, the direct input of the second element AND is connected to the output of the sign the mode of variable clock register microinstructions.

Description

The invention relates to automation and computing, in particular to firmware control devices, and can be used in digital computing systems, as well as terminal equipment.

A firmware control device is known that contains a microinstructor memory block, an address register, a microcommand register, a condition checker, a pulse generator, a group of elements AND, a lock register, and an element 1.

The disadvantage of this device is low efficiency, due to the fact that when implementing the standby modes in the microprogram memory, single microcommand is provided.

The closest in technical essence to the present invention is a firmware control device comprising a microinstructions memory block, a microinstructions register, an address register, a condition checker, a clock generator, a lock register, a group of And elements, and the first And element whose output is connected to the input setting the lock register to the unit and with the register entry of the microinstructions the group of outputs of the operation code of which is the first group of control outputs of the device, the outputs of the code of microoperations register and microinstructions are connected to the first direct inputs of the AND elements of the group, the output of the i-ro element of the AND group (i 1,2, ..., (n-1), where n is the code of the micro-operations code) connected to the iM inverse input of the first element And, with the iM information input of the lock register and with the inverse inputs with (i-bl) -ro through the n-th element of the AND group, i is the iM control output of the second group of the device, the output of the n-th AND group element is connected to the n-m the inverse input of the first element I, with the nth information input of the lock register, is the nth controlling output of the second group of Events, j-th output (jl, 2, ..., p) of the lock register is connected to the second direct input of the j-ro element of the I group, the output group of the microcommand register address code is connected to the first input group of the condition checker, the second group of inputs which is a group of inputs of logical conditions of a device, a group of outputs of a condition testing block is connected to a group of information inputs of an address register, a group of outputs of which is connected to a group of address inputs of a microcommand memory block, an output group of which is connected to a group of information the inputs of the register of microinstructions, the input of which is set to zero is connected to the input of the installation to zero of the address register. And is the input to the initial installation of the device 2.

A disadvantage of the known device is the impossibility of implementing a variable cycle of operation depending on the operating conditions of the control object.

The aim of the invention is to extend the functionality of the device by implementing a variable tact of operation according to logical conditions.

This goal is achieved by the fact that the firmware control device contains a microinstructor memory block, a microinstructions register, an address register, a condition checker, a clock generator, a lock register, a group of And elements, and the first And element whose output is connected to the installation input to "1 lock register and with the register entry of microinstructions, the group of outputs of the operation code of which is the first group of control outputs of the device, the outputs of the code of microoperations of the register of microinstructions are connected to the first by the inputs of the elements of the AND group, the output of the i-ro element of the AND group (1 1,2, ..., (p-1), where n is the digit of the micro-operations code) is connected to the iM inverse input of the first element I, with the 1st the information input of the lock register and with inverse inputs from the (i4-l) -ro ino n-th elements of the AND group and is the i-th control output of the second group of the device, the output of the n-th element of the AND group is connected to the n-th inverse input the first element I, with the nth information input of the lock register, is the nth control output of the second device group, the jth output (j 1,2, ..., p) of the register bl The group of outputs of the microcommand register address code is connected to the first group of inputs of the condition checker, the second group of inputs of which is the input group of logical conditions of the device, the group of outputs of the conditioner checker is connected to the group information inputs of the address register, the output group of which is connected to the group of address inputs of the microcomand memory block, the output group of which is connected to the group of information inputs of the register of microinstructions The first and second elements, AND, the controlled pulse frequency divider and the first and second groups of AND-NOT elements, the first inputs of the AND-NOT elements the first group .and the first direct inputs of the IS-NOT elements of the second group are connected to the output of the second element AND, the inverse input of which is connected to the output of the controlled pulse frequency divider, the clock input of which is connected to the output of the clock generator and the first input of the third And element, the remaining inputs of which are connected to the outputs of the NAND elements of the first and second groups and with the control inputs of the controlled pulse frequency divider, the reset input of which is connected to the output of the third And element, with the input of the address register and the synchronization input the lock register, the information inputs of which are connected to the second inputs of the NAND elements of the first group and to the second direct inputs of the NAND elements of the second group, the third inputs of the NAND elements of the first group and inverse inputs of the elements NANDs of the second group are the inputs of the logical conditions of the device group, the direct input of the second element I is connected to the output of the characteristic of the variable mode of the microcommand register. FIG. 1 shows the scheme of the proposed device; in fig. 2 is a diagram of the condition checker; in fig. 3 - time diagram of the device. The firmware control device contains a block of memory of micro-instructions, a register of 2 micro-commands, a register of 3 addresses, a condition checking block 4, a generator of 5 clock pulses, a lock register 6, a group of elements 7, an element 8, an element 9, an element 10, groups elements AND-NOT 11, and 12, controlled by the divider 13 pulse frequency, input 14 of the initial installation, input 15 conditions, the first 16 and the second 17 groups of outputs. The condition verification unit 4 (FIG. 2) contains AND 18 and OR 19 element groups. The time diagram of the device (FIG. 3) denotes the initial installation signal 20 at the device input 14, the pulses 21 at the generator output 5 pulses, the signal 22 at the element output And 9, the signal 23 at the output of the And / 8 element, the signals 24-26 of micro-orders at the outputs of the first, fifth and twelfth elements And 7, respectively, the signal 27 at the output of the divider 13 with a variable division factor. The firmware control device operates as follows. To bring the device back to its original state, input 14 is given a signal 20, as a result of which the micro-command register 2 and the address register 3 are set to zero; At the zero address from the block 1 of the memory of micro-commands, the initial micro-command is selected and enters the information inputs of the register of 2 micro-commands. So, the contents of register 2 micro-instructions is zero, the outputs of all elements And 7 present zero signals, as a result, signal 23 is selected, according to which the lock register 6 is set to the initial single state, and micro-command is entered into register 2 micro-commands. Each microinstruction consists of three parts, an address, an operation code and a micro-operation code. In addition, the microcommand contains 1 bit of the variable clock mode flag. In the address part of the micro-command, in addition to the direct address of the next micro-command, there is 1 bit of the transition flag (conditional and unconditional). For example, to execute a microcommand contained in the register 2 microcommands, three micro tacts are needed, and during the first, second and third microtacts a single signal must be present, for example, at the output of the first, fifth and twelfth elements AND 7. Then, at the outputs of the first, n The one and twelfth control outputs of the register 2 micro-instructions are single signals, and the rest are zero. The output of the first element And 7 produces a signal 24, as a result of which all subsequent elements And 7 are closed. For example, according to the value of the signal condition generated from the operating circuits as a result of the issuance of the first micro-order, a variable tact mode should be organized. Then, the signal 24 selects one of the elements of the NAND groups of the elements of the NAND 11 or 12, to the input of which a signal of the appropriate condition is received. The inputs of the groups of elements AND-NOT II and 12 are connected to the signals of only those conditions according to which the variable beat mode is organized. If, as a result of issuing a micro-order, a zero value of the condition is expected, the condition is connected to the input of one of the AND-NOT elements of the N-11 element group. Since the microcommand specifies the variable clock mode (the bit flag of the variable clock mode is equal to one), then a single signal arrives at the input of the AND 10 element from the register 2 microcommand output. Element AND 10 is opened with a zero signal from the output of divider 13, as a result of which a single signal from the output of element AND 10 opens groups of elements AND-NAND AND 12. If the value of the condition signal arriving at the input of the selected element IS-NOT groups of elements IS-NOT 11 and 12, is different from the expected, the zero signal from the output of the corresponding element IS-NOT element groups AND NOT 11 and 12 closes the element AND 9. The signal 22 takes a zero value, as a result of which the device stops and the divider 13 starts counting the time inte shaft 21. The momentum dividing ratio of the divider 13 has a different value while waiting for the various conditions. The division factor is given by a zero signal from the output of the corresponding element of the groups of elements NAND AND 12. For example, in the first micro-tact the expected condition is confirmed before divider 13 counts the time interval allocated for waiting for this condition. The corresponding element of the IS-NOT groups of the elements IS-NOT 11 or 12 is closed, as a result of which the element AND 9 is opened. In the second micro-clock, by the signal 22 and in the presence of a single signal at the first installation input, the first bit of the lock register 6 is set to zero. The signal 22 is set to zero and the divider 13. The first element And 7 is closed, thereby opening all subsequent elements And 7. But, since the second, third and fourth elements And 7 are closed with zero signals from the control outputs of the register 2 microinstructions, the single signal 25 is selected at the output of the fifth element AND 7. For example, the condition expected by this micro-order is not confirmed for the allotted time interval counted by the divider 13. Signal 27 is generated, which causes the element 10 to close and, accordingly, close Groups of elements AND-NOT 11 and 12 are opened. And element 9 is opened, as a result of which signal 22 is generated. In the third micro-clock, signal 22 is set to zero five bits of lock register 6. As a result, the fifth element And 7 is closed, and a signal 26 is produced at the output of the twelfth element And 7. The waiting mode for this micro-order is organized as described. In the next micro-signal, signal 22, the twelfth bit of lock register 6 is set to zero, which closes the twelfth element AND 7. "." 17 J7 ,, At the outputs of all And 7 elements, there is no single signal, since zero signals are present on all subsequent after the twelfth control outputs of the register 2 microinstructions. A signal 23 is generated, according to which all bits of the lock register 6 are set to one. At the same time, the next micro-instruction is entered into the register of 2 micro-instructions. The address of this micro-command is formed by the address part of the previous micro-command. Depending on the sign of the transition indicated in the address part of the microcommand, the address of the next microcommand is calculated unconditionally or depending on the value of the conditions received at the inputs 15 of the device. The sign of the transition goes to the inputs of the And 18 elements. If the value of the sign of the transition is zero, the outputs of all the elements of And 18 have zero signals and the address of the next microcommand is determined directly from the address part of the previous one. If the sign of the transition is equal to one, the signals of the logical conditions from the inputs 15 of the device arrive at the outputs of the elements of elements 18 and the address of the next micro-command is formed depending on the value of these conditions. On signal 22, the microcommand address is entered into the 3 address register; as a result, from the micro-command memory block 1, the corresponding micro-command is read, which is prepared in advance. In microcommands that do not use the variable clock mode, the bit of the variable clock mode is zero. In this case, the device operates with a “hard clock” defined by a generator of 5 clock pulses. Thus, the proposed device, as compared with the known, can operate with a variable tact, which is regulated by an external control object, which indicates a broader functionality.

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Claims (1)

A MICROPROGRAM CONTROL DEVICE containing a micro-memory block, micro-register, address register, condition checking block, clock, block register group of elements And I am the first element And, the output of which is connected to the installation input in “1” of the lock register and to the register entry micro-commands, the group of outputs of the operation code of which is the first group of control outputs of the device, the micro-operation code outputs of the micro-command register are connected to the first direct inputs of elements And groups, i-ro output element And groups (i = 1,2, ...., (η — 1), where η is the bit depth of the microoperation code) is connected to the i-th inverse input of the first element And, with the i-th information input of the lock register and with inverse inputs from (i + l) -ro along the ηth element of the AND group and is the ith control output of the second group of the device, the output of the pth element of the AND group is connected to the ηth inverse input of the first AND element, with η- m. the information input of the lock register and is the η-th control output of the second group of the device, the j-th output (j - 1,2, ..., p) of the register. blocking is connected to the second direct input of the j-ro element AND group ,, the group of outputs of the microcode register address code is connected to the first group of inputs of the condition checking unit, the second group of inputs of which is the group of inputs of the logical conditions of the device, the group of outputs of the condition checking unit is connected to the group information inputs of the address register, the group of outputs of which is connected to the group of address inputs of the micro-command memory block, the group of outputs of which is connected to the group of information inputs of the micro-command register, input the zero of which is connected to the installation input in “0” of the address register and is the input of the initial installation of the device, characterized in that, in order to expand the functionality of the device by implementing a variable clock cycle under logical conditions, it contains the second and third AND elements, controlled the pulse frequency divider and the first and second groups of β AND-NOT elements, with the first inputs of AND-NOT elements of the first group and the first direct inputs of AND-NOT elements of the second group connected to the output of the second AND element, inverse the first input of which is connected to the output of the controlled pulse frequency divider, the clock input of which is connected to the output of the clock pulse generator with the first input of the third AND element, the remaining inputs of which are connected to the outputs of the AND-NOT elements of the first and second groups and with the control inputs of the controlled pulse frequency divider the reset input of which is connected to the output of the third AND element, the input of the address register record and the synchronization input of the lock register, the information inputs of which are connected to the second inputs of the element s AND — NOT the first group and the second direct inputs of the AND elements NOT the second group, the third inputs of the AND elements NOT the first group and the inverse inputs of the AND NOT elements of the second group are inputs of the logical conditions of the device group, the direct input of the second AND element is connected to the output sign of the regime of a variable clock register microcommands. SU „„ 1136161