SU1383463A1 - Device for forming pulse train - Google Patents

Abstract

The invention can be used in digital computing and measuring devices for realizing the temporary coupling of an asynchronous signal to a clock frequency. The purpose of the invention is to expand the functionality. The device contains triggers 1-3, the elements And 4 and 5, the counter 6 pulses. The introduction of the sensor 7 of the code, the driver of the 8 pulses, the element OR 9 and the formation of new functional connections provide a programmatic change in the number of pulses in a packet while simultaneously expanding the range of durations of the control signal. 2 Il.

Description

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The invention relates to a pulse technique and can be used in various devices of digital computing and measuring technology to effect a temporary assignment of an asynchronous signal to a clock frequency and, moreover, to form a series of pulses.

The purpose of the invention is to expand 10 functionality by providing a software change: the number of pulses in a burst while simultaneously expanding the range of control signal durations. 15

Figure 1 shows the functional diagram of the device; FIG. 2 shows timing diagrams explaining his work. A device for forming a series of pulses contains the first 1, second 20 2 and third 3 flip-flops, with the direct output of the third flip-flop 3 being connected to the R input of the first flip-flop 1, elements 4 and 5, a pulse counter 6, the counting input of which is connected to the output - 25 And 5, the sensor 7 code, the outputs of the bits of which are connected to the corresponding information inputs of the pulse counter 6, the pulse shaper 8, the element OR 9, the first input 30 of which is connected to the output of the pulse shaper 8 and the write input of the counter 6, and second entrance - exit lane nasal counter 6, bus 10 and clock 11 of steering pulses, the first 2, second 13 and third output buses 14.

The output of the element OR 9 is connected to the C-, I-, K-inputs of the third trigger 3, the direct output of which is connected to the dO R-input of the trigger 2. 1-input of the trigger

1 is connected to the C-input of the trigger 2 and the first inputs of the elements AND 4 and 5. The direct output of the trigger 1 is connected to the 1-input of the trigger 2 and the second input of the 5 element I 4, the direct output of the trigger

2 is connected to the second input of the element And 5, and the inverse output to the third input of the element 4, the K-inputs of the flip-flops 1 and 2 and the R-input of the counter 6 and pulses are connected to the common bus 15.

A device for forming a series of pulses operates as follows.

In the initial state on bus 11, the signal level is low, the output driver is 8 pulses and both of the inputs of the element OR 9 are high and the output level is low. At the direct output of trigger 3, a low signal level is established by initial installation of it at the R input.

A low level at the direct output of the trigger 3 sets the triggers 1 and 2 to the zero state. A low level at the direct output of flip-flop 1 blocks AND 4 and flip-flop 2 at its 1-input. A low level at the direct output of flip-flop 2 blocks element 5. The clock pulses arriving at bus 10 (fig. 2a) do not affect the state of triggers 1 and 2 and the appearance of these pulses at the output tires 12 - 14, where the output voltage level remains high. A code corresponding to the required number of pulses in a burst is established using a code sensor 7 at the information inputs of the pulse counter 6.

The input asynchronous pulse (Fig. 26) of arbitrary duration is converted by the shaper 8 into a short trigger pulse (Fig. 2c), which is inverted through the OR 9 element (Fig. 2d). It enters the trigger inputs 3 and sets it to the decay state as one ( figd). The same pulse, arriving at the input of the record of the counter 6, with its front, writes the code set at the sensor outputs of the 7 codes into this counter.

A high level at the R-inputs of the triggers 1 and 2 allows these triggers to work.

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A jerv clock drop after receiving the resolution translates trigger 1 into a single state (Figure 2e) and this opens element And fc4 trigger 2 at its 1-input.

The next clock pulse, acting on the first input element And 4, passes through it to the output bus 12 (Fig.2zh). In addition, the decay of this pulse, which arrives at the C input of trigger 2, sets it to one state. A high level at the direct output of flip-flop 2 removes blocking from AND 5, and a low level at the inverse output blocks And 4, preventing the passage of subsequent pulses to the output bus 12.

Subsequent clock pulses confirm the single states of the flip-flops 1 and 2 and, through the element 5, enter the counting input of the counter 5 and the output bus 13.

After arrival of the number of pulses specified by sensor 7, the pulse appears at the input of counter 6 at the transfer output of the latter, which arrives at the output bus 14 and at the second input of the element OR 9. The output pulse of the element OR 9 receives a positive pulse (Fig. 2d) to the inputs of trigger 3 and, with its decline, returns it to its original state. A low level at the direct output of flip-flop 3 transfers the triggers 1 rt 2 to zero and blocks their operation. Low levels at the direct outputs of the flip-flops 1 and 2 block the operation of the elements I 4 and 5, preventing these pulses from passing to the output buses 12 and 13 and to the counting input of the counter 6.

When the next control pulse arrives, the device's cycle of operation repeats,

Claims (1)

Invention Formula A device for forming a series of pulses containing three flip-flops, two And elements and a pulse counter, the counting input of which is connected to the first output bus and the output of the first And element, the first input of which is connected to the first input of the second pulse, C-pulse the input of the first trigger and the C input of the second trigger, the direct and inverse outputs of which are connected to the second inputs of the first and second elements, respectively, the output of the last of which is connected to the second output bus and the output of the third trigger is connected With the R-input of the first trigger, in order to expand its functionality, a code sensor, an IL element and a pulse shaper are inputted into it, the input of which is connected to the control signal bus, and the output is connected to the pulse counter recording input and the first element input OR, the second input of which is connected to the third output bus and the output of the pulse counter, and the output is connected to the I-, C- and K-inputs of the third trigger, the output of which is connected to the R-input of the second trigger, 1-input of which is connected to the third input of the second email ment and AND output of the first flip-flop, one input of which is coupled with its C-input and the K input connected to the common bus, the K-input of the second latch and output reset pulse counter, whose data inputs are connected to the sensor output code.  “TJlJTrLrLrLrU-LrL.