SU1485223A1 - Multichannel data input unit - Google Patents

Description

The invention relates to automation and computing and can be used in devices

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information sharing. The purpose of the invention is to increase the reliability of the device. The device contains in this channel the first 1 and second 6 triggers and the first 2 and second 4 elements AND, as well as the element OR 5, the counter 6 and the delay element 7. The device ensures reception of input signals and generates synchronous pulses of positive and negative polarity at the outputs, the duration which is proportional to the digit capacity of the counter and does not depend on the duration of the input signals, while not losing information that came during the time of output of the pulses. 1 il.

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The invention relates to automation and computing and is intended for use in devices for the exchange of information.

The aim of the invention is to improve the reliability of the device.

The drawing shows a functional diagram of the device.

The device contains the first trigger 1, the first element And 2, the second trigger 3, the second element And 4, the element OR 5, the counter 6, the delay element 7, the input tires 8, the output tires 9, the output inverse tires 10, the synchronization input 11.

The device works as follows.

When the power is turned on, there are low voltage levels at the device inputs, corresponding to the absence of input signals, and low-voltage output levels at the trigger outputs 1. Triggers 3 are in the initial state, i.e. Low voltage levels are set at their direct outputs, and high ones at inverse outputs. High voltage levels from the inverted outputs of the flip-flops 3 keep the counter 6 through the element OR 5 in the zero state, the low voltage level from the output of the counter 6 goes to the K-inputs of the triggers 3. The high voltage level from the output of the element OR 5 through the delay element 7 also goes to the second the inputs of the second elements And 2 and allows the passage of information from the direct outputs of the first trigger 1 to the L inputs of the second trigger 3. A low voltage level from the outputs of the first elements And 2 goes to the first inputs of the second elements 4. The outputs of the second elements 4 and a low voltage level is supplied to the quads of the first triggers 1. The device is in the initial state.

When the input signals to the input bus 8 triggers 1 cocked on the leading edge of the input signals. High levels from the outputs of the triggers 1 through the first elements And 2 arrive at the L inputs of the second triggers 3. On the falling edge of the clock pulses of positive polarity, the information from the L inputs of the second triggers 3 is copied to their outputs. The direct outputs of the second trigger 3 are set

high voltage levels, and on inverse low ones. High voltage levels through the second elements And 4 arrive at the K-inputs of the first triggers 1 due to the presence of high potential at the first inputs of the second elements And 4 and return the triggers 1 to the initial state. At their outputs, a low voltage level is formed, which passes through the first element I 2 to the L input of the second trigger 3 and to the first input of the second element I 4. As a result, a low voltage level forms at the output of the second element I 4, which goes to K- first trigger input 1. The first trigger is in the initial state and is ready to receive new information. Thus, there is no loss of information during the output of the output signal.

If the K-inputs of the second triggers 3 receive low voltage levels from the counter output, the second triggers 3 do not change their states upon the arrival of the clock frequency pulses from the input 11 of the device synchronization. Simultaneously with the high voltage levels on the direct outputs of the second triggers 3, low voltage levels are formed on the inverse outputs of the second triggers 3, which through the OR 5 element arrive at the K-input of the binary counter 6 and allow its operation. At the same time, the low voltage level through the delay element 7 after the delay time falls on the second inputs of the first elements 2 and prohibits the passage of single information from the outputs of the trigger 1 to the L inputs of the second trigger 3 for the duration of the signals. This ensures that information on the output buses 9 and 10 is synchronous. The time constant of the delay element is chosen to be greater than or equal to the rise time of the synchronization pulse edge, but should not exceed a duration of 0.5 sync pulse period.

The use of the delay element is necessary to eliminate the influence of the variation of the response times of the applied elements on the operation of the device. properties. Counter 6 allows you to set the desired duration of the output pulses. Choosing his bit,

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It is possible to choose in advance the duration of the output signal necessary for the operation of subsequent devices. On the leading edge of the ηth pulse of the clock frequency, the counter 6 is filled. A high voltage level from the output of meter 6 enters the K-inputs of the second trigger 3. On the trailing edge of the clock frequency pulse, low voltage levels are recorded into the second trigger 3. On the direct trigger outputs 3, low voltage levels are set, and inverse voltages are high. High voltage levels through the element OR 5 reset counter 6 and a low voltage level at its output prepares for. further work on K-inputs second triggers 3. After the delay time, a high voltage level falls on the second inputs of the first elements And 2, thereby allowing the passage of information from the outputs of the first triggers 1 to the L-inputs of the second triggers 3.

If there is information recorded in the first triggers 1, during the output of the output pulses on the trailing edge of the clock pulses, the incoming signals are issued. If this does not turn out to be the case, then when the next input signals arrive on the buses 8, the device begins to generate output pulses of the required duration at the output.

Thus, when the input signals arrive, the device allows to generate at the outputs pulses of positive and negative polarity, the duration of which is proportional to

The nationality is the digit capacity of counter 6 and does not depend on the duration of the input signals, and in the process of operation the information that came to the input of the device at the time of formation of the output pulses is not lost.

Claims (2)

Multi-channel device for 10 information inputs containing the OR element, the counter and in each channel the first and second triggers, the clock inputs of the first triggers are the information inputs of the device, and the outputs 15 second triggers are informational outputs of the device, the inverse outputs of the second triggers are connected to the inputs of the OR element, the output of which is connected to the reset input of the counter, 2o the output of which is connected to the K-inputs of the second triggers, the synchronous inputs of the second triggers and the counter are the synchronous input of the device, characterized in that 25 increase the reliability, a delay element is introduced into the device, and the first and second elements I are entered into each channel of the device, the first inputs of the first elements I are connected respectively to the outputs of the first triggers, and the outputs of the first elements I with the 3 inputs of the second elements And , the second inputs of which are connected to the direct outputs of the second triggers, respectively, and the outputs of the second elements And are connected to the reset inputs of the first triggers, respectively, the second inputs of the first elements And connected through the delay element ki to the counter reset input.