SU1695283A1 - Controlled n-bit pulse distributor - Google Patents

Abstract

The invention relates to computing and can be used, for example, to turn on digital indicators through an encoder or to form verbal visual information on a scoreboard. A distinctive feature of the distributor is that it has a regular structure with a constant number of inputs and elements per channel. The aim of the invention is to simplify the device. The goal is achieved through the introduction of AND elements and new links. 2 Il.

Description

The invention relates to computing and can be used, for example, to turn on signals from digital indicators through an encoder or to form verbal visual information on a scoreboard.

The purpose of the invention is to simplify the distributor.

FIG. 1 shows the distribution diagram; in fig. 2 - time diagrams of his work.

The device contains bits 1, each of which contains an AND-HE 2 element, an H E 3 element, a trigger 4, in addition, the distributor contains a delay element 5, And 6 elements, inputs 7 for specifying the operation mode, outputs 8, a clock input 9.

The distributor works as follows.

If at all inputs 7, which set the distribution program, there are logical zero signals, then at the outputs of the AND-NO 2 elements of each bit 1i a potential of a logical unit is formed. At the same time, at the input of the delay element 5, the potential of a logical unit, which, passage through

delay element 5, keeps all triggers 4 in the state of logical output unit.

There are no pulse distribution signals in all channels.

If there is a signal that determines the expansion of the formation of the corresponding channel pulse, at the input of the first bit 11, a logical one signal appears at the information input of the trigger 4 of the first bit 1i and, accordingly, at the first distributor output.

At the same time, the logical zero level signal at the output of the NAND element 2 bit 1i shunts the input of the NAND element 2 of the subsequent bit 12 directly and through the And 6i element of the positive logic shunts the inputs of all subsequent NAND elements 2. At the same time, the signal is also taken from the setup inputs of the triggers 4, since at the input of the delay element 5 the signal received the value of the logic level zero. Upon the arrival of the first pulse at the clock input 9, the trigger 4 of the first bit 11 is activated, and a signal appears at its output

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with

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logical zero, which shunts the input element AND-NOT 2 of the first bit 1h. Accordingly, the formation of the output pulse of the first channel ends and the prohibition is removed from the input of the AND-NOT element 2 of the subsequent bit 1a. At the same time, if the potential of the logical unit is at the input of the second bit 12, the process of switching on the trigger 4 of the second bit 12 is repeated in the same way and a distribution pulse is generated at the output of the second channel, which through the AND-b element of the shunt inputs the AND-NOT elements of the next 2 bits 1z-p- Etc to a certain j-ro bit 1j, at the input of which there is a potential of logical zero. Trigger 4 of this bit does not work, since a logical zero signal is present at its information input. The impulse in the j-th channel is not successful, but the signal from the output of the AND-HE element 2 of the specified bit 1 will provide, through the element AND 6 (j - 1), the resolution for the element AND-NOT 2 of the subsequent bit 1 0 + 1) - AND etc. to the next channel with the potential of a logical unit at the input of bit 1, where the processes are repeated with the formation of a channel distribution pulse. After all the triggers of 4 bits 1i are triggered, the inputs of which have the potential of a logical unit, the outputs of the elements AND-NO 2 bits 1 | will have the potential of a logical unit. At the same time, in the remaining bits} at the output of the elements AND-HE 2 there will also be the potential of a logical unit due to the presence of the potential of a logical zero on their input buses. Thus, at all inputs of all elements And b there will be potentials of a logical unit that form a pulse passing through delay element 5 and setting all triggers 4 to the initial state (potential of the logical unit at the output). The falling edge of this pulse at the output of the element 6p-1 is formed by the moment of switching to the initial state of the first of the flip-flops 4

and is determined by the speed of the element base. The delay element 5 is intended to reliably set the triggers 4 to their initial state due to the finite speed of the element base.

 For a clearer understanding of the operation of the distributor, consider FIG. 2, where given for the case of the device with n 4, the logical unit of 1.2,

4th control inputs (input 7) and a logical zero on the 3rd control input.

Claims (1)

Invention Formula A controlled n-bit pulse distributor containing n 1K-flip-flops, n I-NOT elements, n NO elements and a delay element, and the IK-flip-flops synchronous inputs are combined and connected to the clock input of the distributor, the first inputs of the NAND elements are respectively the inputs for setting the operation mode of the distributor, the output of the 1st element of the NAND is NOT connected to the input of the 1st element NOT (I 1, ..., p) and is the th output of the distributor, the output of the i-ro element is NOT connected to the 1st input of the 1st IK flip-flop, the inverse output of which is connected to the second input of the 1st I-NE element, the installation inputs to About all IK-flip-flops are combined and connected to the output of a delay element, the K-inputs of IK-flip-flops are combined and connected to a zero potential distributor bus, characterized in that, in order to simplify, n-1 elements AND are entered into it, and the output of the first element AND-NOT is connected to the first input of the first element AND and to the third input of the second element AND-NOT the output j-ro 0 1p-2) of the element AND is connected to the first input of (j + 1) -th element AND with the third input of (j + 2) -th element AND-NOT, the output of (j + 1) -th element AND-NOT connected to the second input of j-ro element AND, output n-th element AND-NOT connected to the second input (n - 1st element I. whose output is connected to the input of the delay element