SU1374234A1 - Device for interfacing telegraph communication line with digital computer - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to interface a telegraph line with a digital computer in information processing systems. The purpose of the invention is not to increase the reliability of the reception of information. The device contains a parcel decoder 4, a pulse counter 2, a reversible counter 5, three elements AND 6, 10 and 11, an OR element 7, which allow you to integrally estimate the duration of the incoming package and ensure reliable operation of the device with interference in the communication channel in the form crushing. The device also contains a shift register 8, a parcel counter 9 and a buffer register 12, which allow the input information symbols to be generated. 3 il. from 5

Description

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The invention relates to computing and can be used in remote data processing systems for interfacing a telegraph link with a digital computer.

The aim of the invention is to increase the reliability of receiving information.

Figure 1 shows the block diagram of the device; FIG. 2 is a functional diagram of the polarity descrambler of the parcel; on fig.Z - timing charts of the device.

The device contains (Fig. 1) a clock input 1, a pulse counter 2, an information input 3 of communication with a line, a decoder 4 of the polarity of a parcel, a reversible counter 5, an element AND 6, an element OR 7, a shift register 8, a counter 9 of parcels, elements Both 10 and 11, buffer register 12, information output 13, initial setup input 14, output 15 of the signal accompanying information.

Figures 1 and 2 denote the high-order pulse output 16, summing 17 and subtracting 18 inputs of the reversing counter, output 19 of the element AND 10, output 20 of the element And 6 output 21 of the sign bit of the reversing counter, output 22 of the element OR 7, output 23 of transfer of counter 2, exit 24 of transfer of counter 9, installation input 25 of the first discharge of counter 9, elements AND 26 and OR 27.

Before starting work, the initial setup impulse arrives at input 14, which zeroes counter 2, reversible counter 5, register 8, and counter 9.

The device works as follows.

To the input 3 of the device yo of the telegraph line from the remote terminal, the symbol-by-information transmission is performed by the start-stop method. Each symbol consists of a set of bits, the value of a bit is transmitted along the line of a unipolar or bipolar infusion. The symbol is accompanied by start and stop bits.

The starting parcel arrives at the input of the decoder 4, to the other inputs of which the most significant bit of the counter 2 pulses from input 1 arrives. The frequency of the clock pulses fed to the input 1 of the device correlates with the frequency of polarity change of the input parcels as (t 1), where m is counter length 2, g When receiving the first half of the starting parcel, output 16 of the higher bit counter 2 is in the state O, If the parcel is received - O polarity, the clock pulse goes to summing input 17, if 1 - to the subtracting input 18 reversible counter 5. The number of bits down counter 1 m + 1 - greater than the number of bits of the counter 2 and 5 thus obtained that the leading bit of the down counter 5 is a significant discharge parcels received. If the received parcel is bipolar, after a time equal to 0 half of the board, its polarity and polarity of the higher bit of output 16 of counter 2 change, and reversible counter 5 counts pulses on the same input as the first half of the 5 parcel.

When receiving the starting set, the state of the counter 9 O and the inverse outputs of its bits arriving at the AND 10 element give 1 at the output 19. 0 If at the same time the parcel is received not of the starting (O) polarity, at 21, the sign digit reversible counter 5 1. The coincidence of these signals generates a reset, which after 5 element OR 7 from output 22 resets counter 2, the reversible counter 5, and the search for the start begins again.

If the parcel of the starting polarity, at the output 21, the sign bit 0 has the value O, the element AND 6 is closed and the counter 2 counts until overflow, at the moment of which the transfer pulse is output on the code 23 as a shift pulse to the register 8, the counting pulse the counter 9 and the reset pulse through the element OR 7 to the counter 2 and the reversible counter 5. At the same time, the state of the counter 9 changes and the element 6 is locked to the output. 0 de 19 - O,

After receiving the starting parcel after every N pulses, the register 8 records the current state of output 21 and advances its contents, and the state of the package counter 9 increases until it overflows. At this point, a transfer pulse is generated at output 24 to allow overwriting the contents re-

8 into the buffer register 12; and the current value of the sign bit of the reversible counter 5, corresponding to the polarity of the stop parcel at that moment, through the And 11 element to the installation input 25 of the parcel counter.

The contents of register 8 are transferred to the buffer register 12. At the same time, if the received information is reliable, output 21 and input 25 have 1. By a transfer pulse, the counter 9 of the parcels is reset to the state O If the stop parcel is O, the input

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The stop is taken as the starting point, and further sign analysis is performed. Thus, when synchronization is lost at the start, the circuit automatically searches for it.

The inverse output of the transfer signal of the counter 9 is the output 15 of the signal of the information support, which signals the digital computer that the next character on the buffer register 12 is ready.

If at the moment of waiting for the starting parcel a disturbance of the order of a quarter of the sequence arrives, after an interval of time equal to its duration, the counter of 2 pulses and the reversible counter 5 is reset, and a false start of the circuit, which can lead to a distortion of information, will not occur. If a short-term disturbance occurs at the moment of receiving the information package, the sign of this package is estimated integrally over the interval of the package and will be of the polarity that prevails.

In a real communication line, when subjected to interference in the form of crushing for less than 5 ms, which are before the starting message and taken as the start, a distorted symbol can be obtained as a result of digital integration when analyzing packages using a series of N quantizing pulses.

When a starting parcel is set, the device analyzes the state of the reversible counter 5 for each quantization pulse, which excludes the possibility of a false start set in the presence of interference in the form of crushing for less than 5 ms, which

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Claims (1)

These are before the starting package. In addition, in the case of receiving an invalid character, when the start is at the place of the stop, the starting package is offset in the device if it was received at the place of the stop. Invention Formula A device for interfacing a telegraph line with a digital computer containing a parser polarity decoder, the first and second outputs of which are connected respectively to the summing and subtracting inputs of a reversible counter, a buffer register and a shift register, the output of which is connected to the information input of the higher-order buffer register, This means that, in order to increase the reliability of receiving information, a pulse counter, a parcel counter, three AND elements and an OR element are entered into the device, with the first input of the first element connected to the output of the second element I, whose input group is connected to the group of inverse outputs of the parcel counter, the installation input of the first bit and the transfer output of which are connected respectively to the output and the first input of the third element I, the second inputs of the first and third elements I are connected to the output of the older one the bit of the reversible counter, the information input of the shift register and the information input of the lower bit of the buffer register, the control input connected to the transfer output of the package counter, the count input otorrhea pulse counter coupled to the transfer output, the control input of the shift register and the first input of the OR gate, a second input connected to the output of the first AND gate, and ; output - to the reset inputs of the reversible counter and pulse counter, the first information input is decrypted. parcel polarity is the input of the device for connecting to the telegraph line, the second information input of the polarity descrambler is connected to the high-end output of the pulse counter, the counting input of which is connected to the sync polarizer of the parcel and is the clock input of the device reset inputs for the parcel counter and re. 5137A2346 the shift horn is connected to the third connection to the input signal by the accompaniment of the OR element and is the input of the information of the digital computer, the output of the initial setup of the device, the encoder register is the output The versatile transfer output of a posi-counter for connecting informals is the output of a device for in- formation of a digital computer. Start Zntmnforn. Stop Interference Start