SU1113792A1 - Interface for linking computer with alphanumeric video display units - Google Patents

Abstract

DEVICE FOR PAIRING ELEGGONAL COMPUTING TTSHY. with ALPHABET-DIGITAL DISPLAYS, J containing a synchro expander a register whose input group is the first group of information inputs of the device, and the group of outputs through the transmitter node is connected to the first group of information outputs of the device and the inputs of the first OR element, the output connected via the first pulse shaper to the first setup input of the first trigger and the first reset input of the counter modulo twelve, and the receiver node, whose input group is the second group of information inputs of the device, and the output group is connected to the second group information outputs of the device and the inputs of the second element OR, the output connected through the second pulse shaper with the second installation input of the first trigger and the second input a modulo twelve axis, the counting input of which is connected to the output of the first element AND and the installation input of the second trigger, the output of which is the interrupt output of the device, is distinguished by the fact that, in order to increase the capacity of the device, six elements are entered into it, NOT, two elements OR, three triggers, and the output of the clock generator is connected to the first inputs of the second, third and fourth elements AND (L and through the element NOT to the first input of the fifth element AND, the fourth and third outputs its elements And are connected respectively to the installation inputs of the third and fourth flip-flops, the outputs of which are connected respectively to the first inputs of the first and sixth elements AND, To the ambient input of the sixth element And connected to the output of the delay element; o and the first input of the seventh element N0 AND, the second input and the output of which is connected respectively to the output of the first trigger and the first input of the third element OR, the output connected to the second input of the first element AND, and the second input to the output of the frequency divider, clock input D of which is connected to the output of the second element I, the input of the expander of the clock pulses and the reset input of the third trigger, the reset input of the second trigger is connected to the input

Description

House of interrogation of communication lines of the device and the second one by the inputs of the third and fifth elements AND, the output connected to the first input of the fourth, OR element, the second input of which is connected to the reset input of the fourth trigger and the output of the fourth element

And, and the output - with the setup input of the fifth trigger, the reset input of which is connected to the output of the first element I, and the single and zero outputs - respectively to the second inputs of the fifth and second elements I.

The invention relates to computing technology and can be used to interface computers, for example, a BESM-6 type computer, with a group of alphanumeric displays. It is known a device for matching a subscriber station with a digital computer, containing a group of elements AND, an element OR, a buffer register, two decoders, a register of the terminal number, a counter and a trigger for the presence of GO.- I The disadvantage of this device is in low bandwidth. Close to the proposed technical entity is a device for interfacing a computer with displays, containing one-bit buffer registers, the group of inputs of which is the first group of information inputs of the device, and the outputs are connected to the inputs of nodes the transmitters whose outputs are the first group of information outputs of the device and are connected to the inputs of the first OR element, the output of which is connected to the input of the first pulse generator, and the output of the latter to the single input of the first trigger and the reset input of the counter modulo twelve, the element I, the first input of which is connected to the single trigger output, and the output - to the single input of the second trigger and to the counting input of the counter modulo twelve, the output of which is connected to the zero input of the first trigger, generator sync pulses connected to the sync pulse spreader inputs, frequency divider and delay element whose output is connected to the second input of the And element and the polling input of the frequency divider whose output is connected to the single input of the second trigger, the output of which is the interrupt output of the device, receiver node, group of inputs and the outputs of which are respectively the second groups of information inputs and outputs of the device, the groups of outputs are connected to the inputs of the second OR element, the output of which is connected to the input the second pulse generator, the output connected to the single input of the first trigger and the reset input of the counter, say twelve, a group of pulse shapers- connected through lines of communication to the output of the sync pulse extender. The issuance of information bits from the display is performed under the control of the sync pulses received from the sync pulse. In this case, the start bit of information enters the device and sets the mode for issuing delayed clock pulses to the computer interrupt system, which is necessary for receiving all bits transmitted from the display to the start-stop combination. If immediately following this information message follows, then the issuance of the delayed clock pulses to the interrupt system continues. If there is no following for the transmitted symbol, the device stops the delayed clock pulses into the interrupt system. In the case of computer information, the frequency divider introduces the delayed clock pulses into the computer interruption system. When the issuance information array is ready, the service program interrupts the drive dispatch for compliance.

On the first register, the start bit that acts on the device is similar to the mode of dispensing from the display and it permits the passage of the delayed sync pulses into the computer jamming system, which is necessary for retrieving the entire symbol 2 from the computer.

The disadvantage of the device is its low bandwidth capacity, which is simply due to the device during periods of allowable service waiting time, and if the service waiting time exceeds the allowable one, then the information bit is perceived

wrong.

The purpose of the invention is to increase the capacity of the device by reducing the cycle time of the user.

The goal is achieved by the fact that in a device containing a sync pulse expander, the output of which is the sync output of the device, a sync pulse generator connected to the output via a delay element with a polling input of the frequency divider, two triggers, the first And element, two pulse formers, and a counter twelve The buffer register, the group of inputs of which is the first group of information inputs of the device, and the group of outputs through the node, of the transmitters is connected to the first group of information in the output of the device and the inputs of the first OR element, the output connected via the first pulse shaper to the first setup input of the first trigger and the first reset input of the counter modulo twelve, and the receiver node, the input group of which is the second group of information inputs of the device, and the output group is connected to the second a group of information outputs of the device and the inputs of the second element OR, the output connected through the second pulse shaper with the second installation input of the first trigger and the second a reset counter modulo twelve, the counting input of which is connected to the output of the first element AND and to the installation input of the second trigger, the output of which is the output of the interrupt device.

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six AND elements are introduced, the NOT element, two OR elements, three triggers, the output of the clock generator connected to the first inputs of the second, third and fourth elements AND, and through the element NOT to the first input of the fifth element AND, the outputs of the fourth and third elements. And connected respectively to the installation inputs of the third and fourth triggers, the outputs of which are connected respectively to the first inputs of the first and sixth elements And the second input of the sixth element And connected5, is not connected to the output of the delay element and the first input of the seventh element And, the second input and output of connected respectively to the output of the first trigger and the first input

0 of the third OR element, the output connected to the second input of the first element AND, and the second input to the output of a frequency divider, the clock input of which is connected to the output

5 of the second element I, the input of the sync pulse extender and the reset input of the third trigger, the reset input of the second trigger connected to the polling input of the communication lines of the device and the second inputs of the third and fifth AND elements, the output connected to the first input of the fourth OR element, the second input of which is connected with the reset input of the fourth trigger, pa and the output of the fourth element I, and the output with the installation input of the fifth trigger, the reset input of which is connected to the output 1 of the first element I, and the single and zero output Q respectively the second inputs of the second and second elements I.

The drawing shows the functional diagram of the device. I

The device contains a generator 1

5 sync pulses, element NOT 2, second 3, third 4, fourth 5 elements AND, delay element 6, seventh element AND 7, frequency divider 8, sixth element AND 9, fourth element OR 10, fourth trigger t1, inputs 12 the first group of information inputs of the device, the buffer register 13, the node 14 of the transmitters, the outputs 15 of the first group of information 55 on the outputs of the device, the first

element OR 16, the first driver 17 pulses, the first trigger 18, the counter 19 modulo twelve.

51

the third element OR 20, the first element AND 21, the second trigger 22, the fifth trigger 23, the third trigger 2D, the expander of 25 clock pulses, the synchronizing output 26 of the device connected through the lines 27 of communication with the imagers 28 display pulses device bridges, the fifth element AND 30, the device interrupt output 31, the inputs 32 of the second group of information inputs of the device, the receiver node 33, the outputs 34 of the second group of device outputs, the second element OR 35, the second pulse shaper 36.

The device works as follows.

When information is received in a computer, generator 1 in the zero state of trigger 23, through element 3, flushes trigger 24, and through expander 25 and output 26 and further along lines 27 issues sync pulses to the inputs of drivers 28, from whose outputs they enter displays.

/

Under the influence of clock pulses, coming from the output of the formers 28, the display provides information that enters the input of the node 33. The display gives a start-stop combination, which has a contact division with a small waiting time in the priority system (11 for the KOI-7 code or 12 for the PDA) . The first bit of the information combination provided by the display is the start bit. From the corresponding output, this bit passes through the element OR 35 and the leading edge of the driver 36 sets the trigger 18 to state 1 and the counter 19 to switch O. Trigger 18 allows the release sync pulses delayed by delay element 6, through elements AND 7, OR 20, and 21 in the zero state of trigger 24 and resetting state 1 of trigger 22, a single state of which causes the computer to interrupt to receive the received bit of information . After that, according to the interrupt processing program, the code of the information bit, c. the corresponding outputs of the node 33 are read into the computer. At the same time, the pulse from the output of the element 21 sets to position 1 the trigger 23 and increases by one the state of the counter 19. When it is detected

2

The information bits from B1) 1solving uula 33 at the input 29 appears pulse. If this impulse occurs before the next pulse of generator 1, then through element I 30, to another input of which permission is allowed to level from element HE 2, through element AH 10, the trigger 23 is set to state O.

The zero state of the trigger 23 permits the passage of the next clock pulse of the generator 1 through the element 3, which causes similar actions.

If the polling pulse at input 29 appears after the next pulse of generator 1, then the next pulse of generator 1 does not pass through element 3, to the second input of which the prohibition is given for a single state of flip-flop 23, but passes through element 5, to which resolution at single state of flip-flop 23, and sets trigger 1 to state 1. The next delayed clock pulse from the output of delay element 6 passes through rags And 7 and, OR 20, but is blocked by AND 21, which is banned from Trigger trigger 24.

Thus, the blocking of the transmission of the generator 1 clock to the displays and the delayed

sync pulse trigger 22. The device in this case is in the waiting mode for processing the interrupt. This mode lasts as long as the input 29 is non-spinning pulse,

which returns the device to its original state. This pulse sets the state of the trigger 22 and, the passage is usually through the elements AND 30, OR 10 sets to

state O trigger 23, which permits the passage of the next sync pulse of generator 1 through element 3 and its transfer to the displays, as well as from the output of element 3

sets trigger 24 to O, which permits the passage of the corresponding delayed clock pulse through AND 21 and setting c. state 1 of the trigger 22. The operation cycle of the device is repeated.

If the polling pulse at input 29 coincides in time with the sync pulse, it sets element 1 to trigger 11 through element 4. As in the previous case, the transfer of this sync pulse to displays is blocked by a single state trigger 23 and set to state 1 flip-flop 24 through the element AND 5. The corresponding delayed sync pulse passes through the elements AND 9, OR 10 and sets the state 23 to the trigger 23, and passing it through the element 21 and 21 is blocked by the single state of the trigger 24. The next sync pulse Step 1 enters the displays and sets the trigger 24 in О, preparing the passage of the delayed clock pulse.

When information from a computer is received for certain programs, an array of data is prepared, but the output from the computer can be started only after interruptions from trigger 22. Frequency divider 8 through the elements OR 20 and 21 outputs the delayed sync pulse and sets it to state 1 trigger 22. When the unavailability of the issue array, the chipping service subroutine blocks the output of information to the inputs 12, so that the stop code is stored on all outputs 15 and output lines from the computer.

When the issue array is ready, the interrupt service routine issues to the corresponding inputs of the buffer register 13 the start bit of information that appears on the corresponding outputs 15 and through the communication lines connecting these outputs

with the displays, the information inputs of the respective displays, as well as the OR 16 element, from which output the shaper 17 5 selects the leading edge of the start and sets the trigger 18 to one and the zero position to the zero position, arrive at the zero position.

Simultaneously with the issuance of the start-up bit from the computer, an impulse appears at the input 28, which establishes in the state O a trigger 23 that permits the passage of a sync pulse through the IZ element, the expander 25

5 and the driver 28. Under the control of this clock pulse, the corresponding display receives the start bit. Further, the scheme works in the same way as receiving information with the only difference

0 that instead of the element OR 35, the element OR 16 works.

If only one character is issued or received, then when the counter 19 overflows, the transfer signal

5 of the counter sets trigger O to position 18. In this case, the output of interruptions to the computer is stopped, and the clock of generator 1 is transmitted to the displays.

0 Thus, the device ensures correct two-way transmission of information at a speed when the waiting time in a priority system can exceed the follow-up period.

5 sync pulses of the generator 1 due to blocking the output of sync pulses into the displays and the delayed sync pulses into the interrupt system during an unserved previous interrupt.

Claims (1)

ELECTRONIC COMPUTER MACHINE DEVICE WITH ALPHA-DIGITAL DISPLAYS, 1 containing a clock expander, the output of which is the synchronizing output of the device, a clock generator connected by the output through the delay element to the polling input of the frequency divider, two triggers, the first element And, two pulse shapers, a counter modulo twelve, a buffer register, the input group of which is the first group of information inputs of the device, and the group of outputs through the node of the transmitters is connected to the first group of information outputs of the device and the inputs of the first element OR, the output m connected through the first pulse shaper to the first installation input of the first trigger and the first counter reset input modulo twelve, and the receiver node, the input group of which is the second group of information inputs of the device, and the group of outputs is connected to the second group of information outputs of the device and the inputs of the second element OR , the output connected through the second pulse former with the second installation input of the first trigger and the second input of the counter reset modulo twelve, the counting input to otorochno connected to the output of the first AND element and the installation input of the second trigger, the output of which is the interrupt output of the device, characterized in that, in order to increase the throughput of the device, six AND elements are inserted into it, an NOT element, two OR elements, three triggers, the output of the clock generator is connected to the first inputs of the second, third and fourth elements And and through the element NOT to the first input of the fifth element And, the outputs of the fourth and third elements And are connected respectively to the installation in the odes of the third and fourth triggers, the outputs of which are connected to the first inputs of the first and sixth elements And, respectively, the sixth input of the sixth element And is connected to the output of the delay element and the first input of the seventh element And, the second input and output of which are connected respectively to the output of the first trigger and the first the input of the third OR element, the output connected to the second input of the first AND element, and the second input to the output of the frequency divider, clock * 4 "·. 'the input of which is connected to the output of the second element And, the input of the clock expander and the reset input of the third trigger, the reset input of the second trigger is connected to the input SU,. ”1113792 house for interrogating communication lines of the device and the second inputs of the third and fifth elements AND, the output connected to the first input of the fourth, OR element, the second input of which is connected to the reset input of the fourth trigger and the output of the fourth element And, and the output - with the installation input of the fifth trigger, the reset input of which is connected to the output of the first element And, and the single and zero outputs - respectively, to the second inputs of the fifth and second elements I. R