GB2101457A - Data communication system - Google Patents

Abstract

A data communication system is described in which data processing stations communicate over a common channel. Before sending a message, each station, when it detects that the channel is idle, sends a warning pulse over the common channel, and then listens for a time equal to at least the round-trip time to the furthest station in the system, in case any other station has also sent a warning pulse. If no pulse is received, the station proceeds with sending its message. If a pulse is received the station, e.g. after a random delay, restarts the message sending cycle. <IMAGE>

Description

SPECIFICATION Data communication system Background to the invention The invention relates to data communication systems. More specifically, the invention is concerned with a data communication system comprising a communication channel which interconnects a plurality of stations, wherein each station is capable of sending messages over the channel to other stations and receiving messages over the channel from other stations.

In such a system, only one of the stations should be allowed to use the channel at any given time: if two stations attempted to send a message at the same time the messages would interfere with each other, resulting in an error. One way of overcoming this problem is to provide a central control unit which supervises the use of the channel. Whenever a station has a message to send, it must first make a request to the control unit, and is allowed to send its message only when it has been granted permission by the control unit. One disadvantage of such an arrangement, however, is that if the central control unit fails the whole communication system is incapacitated.

To avoid this difficulty, the central control unit may be replaced by a plurality of communications controllers situated at the individual stations, such that if any one of the controllers fails, the other controllers can still communicate and the system does not fail completely. One such system is described in British Patent Specification No.

1,517,566. In that system, whenever one of the communication controllers has a message to send, it first listens to the channel to find out whether the channel is free. If the channel is busy, the controller waits. When the channel is free, the controller starts to send its message. While the message is being sent, the controller compares the transmitted message with the signal which actually appears on the channel: any discrepancy indicates that there has been a "collision", i.e.

another controller has started to send its message at the same time. If a collision is detected, the controller aborts the transmission, and tries again at some later time.

One object of the present invention is to provide an alternative to the above system, in which it is not necessary to detect collisions, or to abort the transmission of messages.

Summary of the invention According to the invention, there is provided a data communication system comprising a communication channel and a plurality of communication controllers connected to the channel, each controller being capable of sending messages over the channel to the other controllers and receiving messages over the channel from the other controllers, wherein:: (a) each controller, when it has a message to send, waits until the channel is inactive and then sends a warning signal over.the channel, (b) the controller then waits for a period of time at least sufficient for a signal to propagate over the channel to the furthest controller in the system and back again, and (c) if no other warning signal is detected on the channel during that period, the controller sends its message over the channel, whereas, if a warning signal is detected during that period, the controller returns to step (a) above.

Preferably, there is a delay line interposed between each controller and the channel, having a delay period at least equal to the length of the warning signal. The purpose of these delay lines will be explained later.

Brief description of the drawings One data communication system in accordance with the invention will now be described by way of example with reference to the accompanying drawings of which, Figure 1 shows a distributed data processing system embodying a data communication system in accordance with the invention; Figure 2 is a block circuit diagram of one of the communication controllers; and Figure 3 is a sequence chart of the operation of the controller.

Outline of the system Referring to Figure 1 , the distributed data processing system comprises a plurality of user devices 10 interconnected by a data communication system 11. The user devices 10 may for example be computers, intelligent terminals or other devices capable of producing and receiving messages. Details of the user devices form no part of the present invention and they will not be described further in this specification.

The communication system 11 comprises a communication channel 12 which may, for example, be a co-axial cable or a twisted pair of wires. Preferably, the channel is completely passive so that it has no active components which are liable to failure. The channel may typically be of the order of 1 kilometer in length.

The user devices 10 are connected to the channel 1 2 by way of respective communications controllers 1 3. One of these controllers is shown in detail in Figure 2.

Communications controller Referring to Figure 2, the controller has a shift register 20 which receives a data byte in parallel over a multi-wire path 21 from the associated user device. A clock 22, when enabled, produces a series of clock pulses which shift the data out of the register 20, one bit at a time. In the present example, the frequency of the clock 22 is typically 10 million bits per second.

When the register 20 is empty, a detection circuit 23 produces an EMPTY signal on line 24, informing the user device that it may now supply the next byte over path 21. In this way, a message from the user device, in the form of a string of bytes, is converted into a serial string of bits.

The serial output of the shift register 20 is fed to the input of a transmitter 25, where it is modulated on to a carrier signal. The output of the transmitter 26 is connected by way of a delay line 26 and an isolation relay 27 to the channel 12.

The isolation relay is controlled by the user device, and permits the device and the controller to be completely isolated from the channel in the event of a fault, so as to ensure that they cannot corrupt the rest of the system.

Signals appearing on the channel 12 pass through the relays 27 and delay line 26 to the input of a receiver 28 which demodulates the signals from the carrier. The output of the receiver is fed to a clock separator circuit 29 which extracts clock pulses from the signal. The output of the receiver 28 is also fed to the input of a shift register 30 which is clocked by the output of the circuit 29. In this way, the incoming data signals are shifted one bit at a time into the register 30. When the register 30 is full, a detector circuit 31 produces a FULL signal on line 32. This informs the user device that a byte of data has now been assembled in the shift register 30 and that it may be read in parallel over a multiwire data path 33.

The output of the receiver 28 is also connected to a re-triggerable timer 34. This comprises a counter 35 which is pre-set to a predetermined initial value whenever it receives any input signal, and then counts down at a fixed rate until it reaches zero (unless it is pre-set again by a further input signal). The output of the counter 34 is fed to a decoder 36 which produces an INACTIVE signal when it detects a zero output from the counter, and otherwise produces an ACTIVE signal (i.e. the complement of the INACTIVE signal).

Thus, it can be seen that the INACTIVE signal indicates that the channel has been inactive (i.e.

free from any signals) for a time period T equal to the time required for the counter to count down from the predetermined initial value to zero.

When the communication controller is idle (i.e.

has no message to send), a bistable 37 is set. The output of this bistable is fed to two AND gates 38, 39 in series. The first gate 38 is controlled by a REQUEST signal on line 40 from the user device, while the second gate 39 is controlled by the INACTIVE signal from the timer 34. The output of the AND gate 39 therefore indicates that a REQUEST is present and that the channel has not been active for at least a period T.

The output of the AND gate 39 resets the bistable 37 and also activates a pulse circuit 41 so as to produce a pulse of short duration (typically 50 nanoseconds), which is fed to the input of the transmitter 25. The output of the AND gate 39 is also fed to a delay circuit 42 having a delay period T (i.e. the same as the period of the timer 34). Conveniently, this circuit consists of a pre-settable counter similar to the counter 35 and a decoder for detecting when the count reaches zero.

The output of the delay circuit is fed to two AND gates 43, 44 which are controlled by the INACTIVE and ACTIVE signals respectively. Thus, at the end of a period T following the sending of a pulse from the pulse circuit 41, if the channel has been inactive for all that period the AND gate 43 will be enabled, whereas if any signal has been received during that period, the AND gate 44 will be enabled.

The output of the AND gate 43 sets a bistable 45, causing a SEND signal to be produced on line 46, which in turn enables the clock 22, initiating the transmission of the byte in register 20. The output of the AND gate 44 is applied to the input of a delay circuit 47, the output of which is fed back to the AND gate 39. The delay circuit 47 conveniently also comprises a pre-settable counter similar to the counter 35, and a decoder for detecting when the count reaches zero.

However, the delay produced by the circuit 47 is generally not the same as that produced by the timer 34, but is longer.

The bistable 45 can be reset by means of an END OF DATA signal on line 48 from the user device. This signal also enables an AND gate 49, which causes the bistable 37 to be set again.

Operation The operation of the communication controller will now be described.

When the user device has a message to send, it places the first byte of the message in the shift register 20 and sends a REQUEST signal over line 40. If the channel is busy, nothing happens, since the AND gate 39 is disabled. The controller waits until the INACTIVE signal occurs, whereupon the AND gate 39 is enabled and a pulse is produced by the circuit 41.

This pulse is transmitted on the channel to all the other controllers, and serves as a warning signal, informing the other controllers that this controller intends to send a message on the channel. The other controllers, when they receive the warning signal, have their timers 34 re-set, and hence will be prevented from issuing their own warning signals.

However, it is possible that another controller may already have sent a warning signal before it receives the warning signal from the first controller. In the worst case, the other controller may issue the warning signal only just before receiving the warning signal from the first controller. Therefore, it is necessary for the controller to wait for a period of time sufficient for a signal to propagate to the furthest controller in the system and back again before it can be sure that no other controller has also issued a warning signal. The required waiting period is therefore equal to 2L+4D+R where L is the time required for a signal to propagate along the channel from the point of connection of the controller to the furthest end of the channel; D is the delay time of the delay line 26; and R is the resolution time of the logic devices in the controller.This time is sufficient for a signal to propagate from the controller, through the delay line 26, along the channel to the most distant controller, through the delay line 26 of that controller, and then back again over the same path.

The delay times T of the timer 34 and the delay circuit 42 are therefore both arranged to be equal to this required waiting period.

At the end of this waiting period, if no warning signal from another controller is detected, the AND gate 43 is enabled and the bistable 45 is set, initiating the transmission of the message on the channel.

However, if a warning signal from another controller is detected during the waiting period, the AND gate 44 is enabled at the end of the period, indicating that the controller may not send its message yet, without risk of collision with a message from another controller. After a delay period determined by the delay circuit 47, the input of the AND gate 39 is again activated and, as soon as the INACTIVE signal re-appears, another warning signal is sent. The controller thus repeatedly attempts to send its message, until eventually it is able to do so without risk of collision.

The delay produced by the delay circuit 47 is preferably arranged to be different in each controller, or is selected on a random basis, so as to avoid the possibility of the same two controllers repeatedly attempting to gain control of the channel at the same time, each being prevented from sending their messages by the warning signal from the other.

The delay is arranged to increase with each unsuccessful attempt to send the message, in order to reduce the overheads of failed messages clogging the system in heavy traffic conditions.

When the last byte of the message has been placed in the shift register 20 and transmitted, the user device sends the END OF DATA signal on line 48. This indicates to the controller that the message is complete, and returns the'controller to the idle state, with the clock 22 disabled.

The operation of the system is summarised in the form of a sequence chart in Figure 3.

Delay line 26 The reason for the inclusion of the delay line 26 between the controller and the channel is to ensure that there is a minimum transmission time (2D) between any two adjacent controllers, even in the case where they are connected to the same point of the channel. If these delay lines were not present, the transmission time between two such adjacent controllers would be very short and, if the two controllers sent warning pulses simultaneously their warning pulses would overlap and neither controller would detect the warning pulse from the other. This would lead to 3 collision, since both controllers would wrongly assume that they could proceed with sending their messages.

The delay D should be at least equal to the length of the warning signal pulse, and is typically chosen to be approximately twice that length.

Typical values The following are typical values for the various delay times, and are given by way of example only: L=10 microseconds D=100 nanoseconds R=100 nanoseconds Hence T=20.5 microseconds Some possible modifications In the system described above, the controller waits until the channel has been inactive for a predetermined period before sending a warning signal. In the described system, this predetermined period is determined by the timer 34 and is equal to T; i.e. it is the same as the waiting period between the sending of a warning signal and the transmission of the message.

However, these two periods are not necessarily the same, and in a modification of the invention a separate timer could be used to determine the length of the period of inactivity before sending a warning signal.

Although the timer 34 and delay circuits 42, 47 have been described as comprising presettable counters, other forms of delay device may be used e.g. shift registers or delay lines.

Another possible modification is that data may be transmitted over the channel directly, without modulating it onto a carrier. In this case, the transmitter 25 and receiver 38 would simply be amplifier circuits, rather than modulator and demodulator.

It will be appreciated that many other modifications are possible without departing from the spirit and scope of the invention.

Claims (6)

Claims

1. A data communication system comprising a communication channel and a plurality of communication controllers connected to the channel, each controller being capable of sending messages over the channel to the other controllers and receiving messages over the channel from the other controllers, wherein: (a) each controller, when it has a message to send, waits until the channel is inactive and then sends a warning signal over the channel, (b) the controller then waits for a period of time at least sufficient for a signal to propagate over the channel to the furthest controller in the system and back again, and (c) if no other warning signal is detected on the channel during that period, the controller sends its message over the channel, whereas, if a warning signal is detected during that period, the controller returns to step (a) above.

2. A system according to Claim 1 further including a delay line interposed between each controller and the channel, each delay line having a delay at least equal to the length of said warning signal.

3. A system according to Claim 2 wherein said period of time is equal to 2L+4D+R where L is the time required for a signal to propagate along the channel from the point of connection of the controller to the furthest end of the channel. D is the delay of said delay line, and R is the resolution time of the logic devices in the controller.

4. A system according to any preceding Claim wherein, if a warning signal is detected at step (c), the controller returns to step (a) after a random delay.

5. A data communication system substantially as hereinbefore described with reference to the accompanying drawings.

6. A communication controller for a data communication system, substantially as hereinbefore described with reference to the accompanying drawings.