SU1228247A1 - Device for delaying signal - Google Patents

Abstract

The invention relates to a pulse technique. It can be used to form delayed signals. The purpose of the invention is to improve noise immunity by ensuring insensitivity to short impulse noise. To achieve this goal, a logical element (LE) OR NONE 4 is introduced into the delay device. The device also contains a pulse generator, ow 1, register 2, LE I 3, and RS9 type trigger code 5. In the presence of short impulse noise, the duration of which is shorter than the delay time, zero or one state will not be formed at the bit outputs of register 2. As a result, the state of output trigger 5 will not change, which ensures the insensitivity of the device to such interference. i SL Butl Bti.t IND 00 io Wml

Description

The invention relates to a pulse technique and can be used to form a signal delay with synchronization of all information.

The purpose of the invention is to increase noise immunity due to insensitivity to short impulse noise.

The drawing shows the functional diagram of the device.

The signal delay device contains a generator of 1 pulses, a shift register 2, logic gates AND 3, and OR-NOT 4, and an output trigger of 5RS type.

The output of the pulse generator 1 is connected to the clock inputs of the shift registers 2. The bit outputs of the shift register 2 are connected to the inputs of the AND 3 and OR-NOT 4 logic gates, the outputs of which are connected to the single and zero inputs of the trigger 5, respectively.

The device delay signal works as follows.

If in the initial state on the input glane is set to O, then by; Signals from the pulse generator 1 will be sequentially set to all the bit outputs of the shift register 2.

respectively, at the inputs of the AND 3 and OR-NO 4 gates, O. will be established. Coincidence of all the inputs of the OR-NOT 4 gates gives at its output 1, which sets the trigger 5 to the zero state. When installed on the input bus 1, sequential recording occurs

Editor M.Tovtin

Compiled by A.Titov Tehred I.Veres

Order 2296/57. Circulation 816

VNII1Sh State Committee of the USSR

for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

228247

in all bits of register 2 shift, which is fixed by logical

to

 one

element 3, at the output of which one appears and trigger 5 is set to one. The delay time of the signal is equal to the period, the sequence of the clock pulses, multiplied by the number of bits of the register 2 shift.

With short impulse noise, the duration of which is shorter than the delay time, the zero outputs of register 2 will not generate a zero or one state on all outputs, and therefore, the state of the output trigger 5 will not change. This ensures the insensitivity of the device to such interference.

formula of invention

A signal delay device containing an output trigger, an AND logic element, the inputs of which are connected to the bit outputs of the shift register, whose information input is connected to the input bus and the clock input to the output of the common generator

impulses, characterized in that, in order to increase noise immunity due to insensitivity to short impulse noise, an OR-NOT logical element is input to it, whose inputs are connected to the bit outputs of the shift register, and the output to one of the output trigger outputs whose other input is connected to the output of the logic element I.

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Claims (1)

Claim A signal delay device containing an output trigger, a logical element And, the inputs of which are connected to the bit outputs of the shift register, the information input of which is connected to the input bus, and the clock input is connected to the output of a common pulse generator 30, characterized in that, in order to increase the noise immunity for account of insensitivity to short impulse noise, an OR-NOT logic element is introduced into each channel, the inputs of which are connected to the bit outputs of the shift register, and the output to one of the inputs of the output trigger, d whose other input is connected to the output of the logical element I.