SU1302436A1 - Bipolar code converter - Google Patents

Abstract

This invention relates to automation. Its use in digital information transmission systems improves the noise immunity of the conversion. The bipolar code converter contains a differential block 1, selectors 2, 3 pulse fronts, element OR 5, triggers 8, 12, and element 13 of delay. Introduction of 4 impulses, counters. 6, 7, element 9, elements OR 10, 11 ensure the operation of the converter with pulses of any duration, regardless of the stability of the supply voltages and the changes in the amplitude parameters of the input signal. 3 sludge. iplti.i

Description

. The invention relates to automation and can be used in digital information transmission systems.

The purpose of the invention is to increase the noise immunity of the conversion.

Figure 1 presents the functional diagram of the Converter; 2 and 3 are timing diagrams explaining its operation.

The bipolar code converter contains differential block 1, first 2 and second 3 pulse front selectors, shaper 4 pulses, first element OR 5, first 6 and second 7 counters, first trigger 8, element 9, second 10 and third 11 elements OR, second trigger 12, delay element 13. In Fig.1 marked the first 14 and second 15 inputs, the first 16 and 17 second outputs.

The differential unit 1 is made on a differential amplifier, which provides an increase in the input resistance compared to the transformer cascade.

On. 2 and 3 are indicated: a - signals at the first input 14 of the converter; b - signals. at the output of the first selector 2 pulse fronts (output 17); (c) signals at the output of the second selector of 3 pulse fronts; g - signals at the output of the first element OR 5; d - signal at the output of the driver 4 pulses; e - signals at the output of the element 13 delay; W - signal at the output of the first trigger 8; 3 - signal at the output of the element And 9; and, k - signals at the outputs of the first and second counters 6 and 7, respectively; l, m - signals, respectively, at the R- and S-inputs of the second trigger 12; n - signals at the output of the second trigger 12 (output 16),

The triggering output of the trigger 8 is in the lo state. The converter operates by the next 45 gic-1, and delays it with a switch.

The signals of the bipolar code arrive at the inputs 14 and 15 of the converter in the general case as a sequence of n-bit words, separated from one another by a time interval in m periods T of the transmission frequency of information bits, during which the voltage of both signals is double-polar code equals zero in the ideal case.

Thus, the transfer of one information word takes a time interval pt, and the interval between words is tT, where m is positive, an 50

This trigger 8 is enough for the first impulse from the output of the element OR 5 to pass through the open element AND 9 and at the same time has a duration sufficient to trigger the trigger 12.

The pulse shaper 4 serves to detect the end of the transfer of the information word 55. At the end of the p-bit input word, after the zero level at the output of the SHSh 5 element, the driver of 4 pulses through time

positive and integer numbers. In the differential block 1, there is a mutual subtraction of the input signals, which allows to supply common-mode noise,

which may occur in the input signal. The signal is then fed to the selector inputs 2 and 3 of the pulses, the pulses at the outputs of which are formed j, respectively, along the positive and negative edges of the input signal. The duration of the pulses generated at their outputs is set depending on the speed of the element base on which the converter is realized.

The pulse duration at the output of the second selector 3 should ensure the stable operation of the counters 6 and 7 and the trigger 12, and at the output

the first selector 2, which forms the clock pulses at the output 17, also exceeds the signal propagation time along the path: the input of the element OR 5 is the output of the trigger 12. This choice of the duration of the clock pulses ensures a stable attachment of their decay to the signal at the output 16, which is significantly for further processing of the converted signals, for example

to convert serial data to parallel.

The pulses from the output of the first selector 2 pulse fronts trigger the shaper 4 pulses and through

the delay element 13 is fed to the R-input of the trigger 8, set at its output logical O.

In this case, the delay element 13 performs two functions: it delays the appearance of a pulse at the R input of the trigger 8 until the pulse shaper 4 is activated and the level at the S input does not disappear while holding

This trigger 8 is enough for the first impulse from the output of the element OR 5 to pass through the open element AND 9 and at the same time has a duration sufficient to trigger the trigger 12.

The pulse shaper 4 serves to detect the end of the transfer of the information word 55. At the end of the p-bit input word, after the zero level at the output of the SHSh 5 element, the driver of 4 pulses through time

(1-3) T generates at its output a logic level 1, which sets the logic level 1 at the output of the trigger 8, and the logic level O at the output of the trigger 12. In this state, the triggers 8 and 12 are held until. as long as the next information word does not come to the inputs 14 and 15 of the converter.

If logical 1 is transmitted at the beginning of the next information word, the first pulse appears at the output of the first pulse edge selector 2 (FIG. 2), which produces an output pulse along the positive edge of the input signal. This pulse, the passage through the element OR 5, starts the pulse shaper 4, and through the open element 9 and the element

OR 10 sets the level of logic 1 at the output of trigger 20. At the output of the driver of 4 pulses with a delay relative to the input pulse, a level is formed

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O. In this case, the trigger 8 on S-BXO-25 (3 or 2) is formed in addition two times, and the trigger 12 on the R input has a pulse. These pulses are located with released., Between two adjacent pulses, the time determined by the elements, which are formed according to the 13th delay, the same pulse appears at the R input of the trigger 8, is set at its output logic level O, which locks the element And 9 and blocks the passage of pulses through it. Since the logical O at the output of the driver of the 4 pulses is preserved until the end of the word being transformed, then the AND 9 element is locked all this time. After triggering the first bit of the information word, the trigger 12 is controlled by 40 gic. 0. (1), then the counters 6 and 7 change through the OR elements or no trigger 12, 10 and 11.

If logical O is transmitted at the beginning of the information word, then the first at the output of block 1 is from a forward two impulsive front of the pulse, and therefore, at the output of the rum at the output of the second selector 3 counters 7 (6) does not appear to generate a pulse. This pulse, a logical signal leading through the element OR 5, triggers the formation of a change in the state of trigger 12. At the output of 4 pulses, and through element 50 of the output of trigger 12, a delay delay 13 is saved sets the output level of the logic a level that prohibits the passage of pulses through an element 9. In addition, this impulse sets counter 55 to the initial state 55 and increases by one the number in counter 7. Because after the end of the preceding information front selectively de torus 30 2 or 3. At the output of the counter 7 (6) is an active logic level which, through the OR gate 11 (10) sets the flip-flop 12 to a logical D (1).

If in the input information there is no change in the data transmitted, i.e. Continuously for several bits of information, the paddle is transmitted between two adjacent pulses arriving at the installation input of the counter 7 (6) at the counting input of the previous bit of information.

The output transformed data is reliable at the moments of the ends of the pulses at the output of the first selector 12 pulse fronts. In this case, the pulse duration of the input signals can be any.

The trigger word 12 was set at the foot of the word from the pulse generator 4 output to the logical O state, its state does not change, and the logical O is saved at the output.

After receiving the first bit of the information word, trigger control 12 is performed by counters 6 and 7, which generate control signals at the moments when input information changes from logical O to 1 — counter 6, assertive 1 to O counter 7. At the outputs of counters 6 and 7, a change in the logic state if two counting pulses come between adjacent pulses of the installation.

If the input data changes the transmitted data

 0 to 1 (from 1

on

from logical

O), then at the output of differential 5 of block 1, two identical fronts are formed successively one after the other (FIG. 3). At the output of the corresponding selector

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 Settings that are formed according to the corresponding 40. (1), then no change of trigger 12 occurs,

corresponding front at the output of the selector 30 or 2 or 3. At the same time, the output of the counter 7 (6) is the active logic level, which through the element OR 11 (10) sets the trigger 12 to the logical state O (1).

If in the input information there is no change in the data transmitted, i.e. continuously for several bits of information is transferred to the lotovki, which are formed by the appropriate .0 (1), then no change of the trigger 12 occurs,

There are no two pulses occurring and, therefore, the output of counter 7 (6) does not produce an active logic signal leading to a change in the state of trigger 12. At the output of trigger 12, a logical the level that was formed

Since between two adjacent pulses arriving at the input of the installation of the counter 7 (6), two impulses cannot appear at the counting input and, therefore, an active logical signal does not appear at the output of the counter 7 (6) leading to a change in the state of trigger 12. At the output of trigger 12, a logical level is maintained, which is formed

when receiving the previous bit of information.

The output transformed data is reliable at the moments of the ends of the pulses at the output of the first selector 12 pulse fronts. In this case, the pulse duration of the input signals can be any.

The selectors 2 and 3 of the pulse fronts also provide a threshold for the rise rate of the input signal, which depends on the requirements for the front and decay of the two-pole signal, as well as a threshold of the order (15-20%) of the maximum permissible amplitude of the bipolar signal. This threshold is set by selecting the selector mode 2 and 3 and provides additional resistance to possible antiphase interference. The stability of the threshold for the operation of the converter is immaterial.

Since the output signals (outputs 16 and 17) are formed from the differences in the input bipolar signals, they do not depend on the stability1; and the supply voltage of the converter and the change in the amplitude parameters of the converted signals, and therefore the stability of the conversion increases

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Claims (1)

Invention Formula A bipolar code converter containing a differential module, the first and second inputs of which are the corresponding inputs of the converter, the output is connected to the inputs of the first and second pulse edge selectors, the outputs of which Beginning of informational c / iofa The moments of the SocmofepHocmu are preoperated and the data of FIG. 2 connected to the corresponding inputs of the OR element, the output of which through the delay element is connected to the R input of the first trigger, the second trigger whose output is the first output of the converter, characterized in that, in order to improve the robustness of the conversion, counters are inserted into the converter , AND element, second and third OR elements and pulse shaper, whose input is connected to the output of the first OR element, counting input of the first and installation input of the second 15 counters and the first input element And are combined and connected to the output of the first selector of the pulse fronts and the second output of the converter, the counting input of the second and stationary input 20 of the first counters are combined and connected to the output of the second pulse edge selector, the outputs of the counters are connected to the first inputs of the second and third elements respectively 25 OR, the outputs of which are connected respectively to the S and R inputs of the second trigger, the output of the pulse former is connected to the second input of the third OR element and the S input of the first 30 trigger, the output of which is connected to the second input element And the output of which is connected to the second input of the second element OR. Editor A. Shandor Compiled by O. Revinsky Tehred L. Oleinik Order 1225/56 Circulation 902 Subscription VNIIPI USSR State Committee for inventions and discoveries 113035, Moscow, Zh-35, Raushsk nab., 4/5 Production and printing company, Uzhgorod, st. Project, 4 Proofreader S. Shekmar