SU1297244A1 - Synchronizing device - Google Patents

Description

The invention relates to radio engineering and can be used for synchronization in discrete information transmission systems during short communication sessions.

The aim of the invention is to improve the noise immunity of synchronization when operating in the mode of short communication sessions.

Figure 1 shows the structural electrical circuit of the device; Fig. 2 shows timing diagrams of signals explaining the operation of the device.

The synchronization device contains shift registers 1, keys 2, comparison blocks 3, control signal drivers 4, OR-NOT 5 element, reference clock generator 6, reference generator 7, and delay line 8 with N taps.

The control signal formers 4 contain AND 9 elements and pending multivibrators 10.

The synchronization device operates as follows.

During a communication, a sequence of characters is transmitted (Fig. 2a) consisting of a synchronization sequence and information symbols transmitted following the synchronization sequence. The input sequence of characters, distorted by noise (Fig. 2b), is fed to the informational inputs of the input signal processing channel and N additional input signal processing channels, each of which consists (Fig. 1) of series-connected carav- block; The driver 4 and the key 2, as well as the register 1, whose bit outputs are connected to the corresponding first inputs of the comparison unit 3, and the output of the first register I register are connected to the information input of the key 2, and the information and clock inputs of the register 1 are respectively informational and so10

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The sequence in registers 1 is carried out by various pulsations, by it, the 1CIMI pulse period is equal to T, and shifted one relative to another in T / N + (where T is the symbol duration). This is achieved by the fact that at the clock in dyes of registers 1, the pulse sequences are received respectively from the output of the reference generator 7 and about the delay line 8.

On fig.2c, d, d, the shifted sequences of pulses are presented in the case of N 2.

In each register 1, the mutual position of the character boundaries of the received sequence arriving at the information input and the pulse sequence arriving at the clock input from the communication session to the ansu may vary, but during each individual communication session (in short sessions ) this mutual arrangement in all registers 1 remains unchanged. Thus, due to the presence of pulse sequences that are shifted in time during a short communication session in one of the registers 1 during the entire session, the construction of the received sequence occurs near the middle of the symbol (near the signal maximum) which ensures a lower probability of 35 than the other registers 1, in which the construction of the received sequence is carried out at unfavorable times (near the minimum from the currency). The synchronization sequences written in registers 1 are sent to the first inputs of the corresponding comparison units 3, the second inputs of which are; a reference synchronization sequence is received from the output of the imaging unit 6. In the event that the indicated sequences coincide (i.e., in the case of an error-free reception of the synchronizing sequence

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input inputs of the corresponding capacity) corresponding block 3

la processing the input signal. When a pulse arrives at the clock input of register 1, a new information is recorded in register 1 (or

the comparison generates a matching signal (high potential) at the output, which is an indication of synchronization. A coincidence signal in different sessions 0 depending on the level of input-5-5 sakh communication can be formed in the signal) and at the same time a shift to the right of any block 3 coincidences. But in each previously recorded information. The house has a separate session. Its probing Strobe (write) the characters of the attack are more in the processing channel.

five

0

five

The sequence in registers 1 is carried out by various impulse factors, having a period of impulses following, equal to T, and shifted relative to each other in time by T / N + 1 (where T is the symbol duration). This is achieved by the fact that the pulse inputs of registers 1 receive pulse sequences respectively from the output of the reference generator 7 and the taps of the delay line 8.

On fig.2c, d, d, the shifted sequences of pulses are presented for the case of N 2.

In each register 1, the mutual arrangement of the character bounds of the received sequence arriving at the information input and the pulse sequence arriving at the clock input may vary from session to session, but during each individual session (for short sessions) this is mutual the location in all registers 1 remains unchanged. Thus, due to the presence of pulse sequences shifted in time during short sessions in one of the registers 1 during the entire session, the gating of the received sequence is carried out near the middle of the symbol (near the signal maximum), which ensures a lower probability of 5 characters than in other registers 1, in which gating of the received sequence is performed at adverse times (near the minimum of the signal). The synchronization sequences recorded in registers 1 are sent to the first inputs of the corresponding comparison units 3, to the second inputs of which; the reference synchronization sequence comes from the output of the former 6. In the case of the coincidence of the indicated sequences (i.e., in the case of an error-free reception of the synchronizing sequence

0

five

0 values) corresponding block 3

the comparison generates a matching signal (high potential) at the output, which is an indication of synchronization. A match signal in different sessions can be formed in any block 3 matches. But in each individual session, the probability of its occurrence is more in the processing channel.

3

the input signal or in one of the N additional channels of processing the input signal, in which the sequence gating is performed near the middle of the symbol (near the signal maximum). The coincidence signal, first detected during a communication session at the output of Comparison Channel 3, processes the input signal or one of the N additional input signal processing channels, through the corresponding AND 9 element, to trigger the corresponding pending multivibrator 10, which generates a positive-pulse. lnness. This pulse, the duration of which is equal to the transmission time of information symbols, unlocks the corresponding key 2, ensuring the passage of information symbols from the output of the first digit of the corresponding register 1 to the output of the synchronization device and simultaneously arrives at the OR-NOT 5 element, the pulse from whose input blocks through the second inputs all elements And 9, preventing the launch of all pending multivibrators

10 during the reception of information

t

characters. After termination of the pulse generated by the corresponding waiting multivibrator 10 (in the pauses between communication sessions) at the output of the OR-NOT 5 element, and consequently, at the second inputs of all And 9 elements,

high potential is present, allowed to be connected to the corresponding outputs

The arrival of the next match signal for triggering the waiting multivibrators is 10.

Claims (1)

Invention Formula A synchronization device comprising a reference oscillator, a reference clock generator and an input signal processing channel, which consists of a series-connected comparison unit, a control signal generator and a key, as well as a shift register, the bits of which are connected to the corresponding first inputs of the comparison unit , while the clock input of the shift register is connected to the output of the reference oscillator, the second f5 W 972444 The inputs of the comparator are connected to the corresponding outputs of the generator of the reference synchronization sequence, the information input of the shift register and the output of the key are the input and output of the device, respectively, characterized in that, in order to increase the noise immunity of the synchronization during short sessions the input signal, the output of the first bit of the shift register is connected to the information input of the key, and in addition, N additional channels are introduced for processing the input signal input signal identical to the input channel, as well as a delay line with N taps and an OR-NOT element, the combined information inputs of the shift registers and the combined key outputs of the N additional input signal processing channels are connected respectively to the information, the shift register input and the output of the processing channel key input signal, clock inputs shift registers N additional input signal processing channels connected to the corresponding taps of the delay line with N taps, the input of which is connected to the output of the reference generator, the second inputs of the blocks compare the N additional channels of processing the input signal 20 25 thirty 40 45 50 the generator of the reference synchronization sequence, and the outputs of the control signal drivers of the input signal processing channel and N additional input signal processing channels are connected via the OR-NOT element to the second inputs of the input signal processing channel control signal drivers and N additional input signal processing channels This signal consists of a series-connected element AND and a stand-by multivibrator, the output of which is an output. The control signal threads and the first and second inputs of the And element are respectively the first second inputs of the control signal drivers. ABOUT I 1 -9 t 1st  g 3. about P with e. Editor N.Shvyschka Compiled by V.Orlov Tehred L. Serdyukova Order 797/62 Circulation 639Subscription VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035 Production and printing company, Uzhgorod, st. Project, 4 - € Phage.2 Proofreader S. Shekmar