SE316805B - - Google Patents

Abstract

1,105,959. Transversal equalizers. WESTERN ELECTRIC CO. Inc. 2 June, 1966 [2 June, 1965], No. 24537/66. Heading H4R. The settings of the multipliers in a transversal equalizer are established during normal message transmission using the apparatus of the Figure in which the output from the equalizer, comprising delay line 12, multipliers 15A to 15E and summer 16, is sampled at intervals equal to the reciprocal of the data transmission rate in the sampling gate 17. The resulting samples are fed to one input of a subtractor 32 and to a binary slicer 18 which recovers the binary message stream which is applied to the data utilization device 19 and to the other input of the subtractor 32. The subtractor, being fed with signal samples and with regenerated received binary signals derived from those samples, produces, at its output, an error signal stream which corresponds only to the distortion products, as modified by the existing setting of the equalizer. The error signal is passed through a delay 30, equal to half the total delay of line 12, to one input of each of the multipliers 23A to 23E, to the other input of which is fed the regenerated received binary stream from slicer 18 after feeding through one or more stages of shift register 24A to 24E which has a stepping rate equal to the repetition rate of the received binary stream. The output of the multipliers at any sampling instant is equal to the sum of two terms, one the product of a regenerated digit and the effect of that digit at the particular line tap corresponding to that multiplier, and the other the product of that digit and the effect of other digits through that and other taps. The first of these terms will always be of a sign dependent only on the error of adjustment of the equalizer multiplier on that tap, while the second term will have a sign dependent on the actual digit stream received and will vary randomly. The output of the multipliers is passed through respective low-pass filters 22A to 22E which remove the second term referred to above leaving only a signal which represents the multiplier adjustment required. This signal is gated, via gate 21, at intervals to slicers 20A to 20E to adjust the multipliers, or attenuators, 15A to 15E, in a manner to reduce the distortion products as described in Specification 1,105,958. It is suggested that multilevel data sequence systems may be equalized in a similar way by making slicer 18 multilevel and duplicating shift register 34, multipliers 23, filters 22, gates 21, and slicers 20 for each slicing level.