DE1294431B - Circuit arrangement for obtaining the optimal settings of the damper elements of a cross-equalizer for digital data pulse signals - Google Patents

Description

The invention relates to a circuit transmission over the communication channel arrangement for obtaining the optimal settings, transmit a series of test pulses that are increased by several linder Attenuators of a cross equalizer, which separate the pulse rate time intervals from one another, distortion of digital pulse signals sent by a These test pulses are used in the context of a

Data source via a distorting transmission ⁵ step-by-step procedure taking place adjustment channel with predetermined pulse repetition of the attenuator counters are transmitted to their optimal frequency, compensated. (The values are used. For the sake of brevity above, the term "re-automatic equalization can use the prefix rate" is simply referred to as "rate".) Font (the algorithm) for setting the attenuation

When transmitting information via a ^{post-10-multiplication} factors fung member through this Zährichtenkanal often found that to be the entfern- ler easily detected. Signals received after traversing each end of the channel are distorted test pulses by the distorting messages. This distortion is caused by the non-linear channel and the transverse filter, the resulting out-transmission properties of the transmission channel input pulse at intervals that are the same as a function of the frequency. These * 5 are the reciprocal of the predetermined pulse rate, nonlinear properties affect the amplitude and phase of the received signals. It is increased by one increment step if the knowledgeable that this distortion is negative by inserting an initial sampling, and in order to compensate for an incremental distortion in the transmission channel. step humiliated if that is positive. Even if such equalizer can only be a finite number attenuators are operated frequency range for the so-called frequency ^20, that is, it may be an adjustment are available, the resultant will have Vierpolnetzwerk whose transmission distortion by this algorithm optimal properties as a function of the frequency practically reduced.

the mirror image of the transmission properties of the The disadvantage of this well-known automatic de-

are to be equalized channel, or the equalizer ² 5 zerrers is that that a series of test pulses before the can be operated in the so-called time domain. Transmission of the actual data signals via signals in the time domain must be carried with their frequency. In addition to the area counterparts resulting from the Fourier-Trans reduction in the useful time, this anformation pair is linked. The time domain counter-order does not mean that the transmission part of the frequency response of a filter 3 ° properties of the communication channel can change in the verist the impulse response of a filter, that is, during a data transmission. In this case, the response behavior to the excitation would receive distorted signals, the Dirac's δ or "" function. A complete of the known automatic equalizer without understanding the time domain analysis is, however, for which a further series of test pulses not correcting understanding of the present invention are not necessary.

agile. Suffice it to say that the analysis and object of the invention is therefore to provide an auto-

Build the design of equalizers by using a matic equalizer that does not test the Time domain method is facilitated. pulse series required and the changes in the

If the transmission properties transmitted over the message channel are during reception Signals are digital signals that respond to predetermined 40 of data signals.

Pulse rate are transmitted, it is also advantageous for the circuit to design the equalizer in such a way that the equalization arrangement of the type described in the introduction erinrung can be effected in the time domain. This duly characterized by a scanning gate, Construction enables the response behavior that occurs at the pulse repetition frequency (pulse des The equalizer also to compensate for rate of change 45) samples the output amplitude of the equalizer, gen the properties of the message channel after the signals enter the channel and the equalizer to deliver. This is particularly advantageous if one has happened to the output of the equalizer if the equalizer is used in conjunction with a remote-connected detection circuit (binary limiter) message switching network is to be used to obtain a signal that is to be used as the digital pulse which it is impossible to judge the characteristics of the 5 ° signal representing a subject Predict communication path or tracer that leads to an overall distortion to be obtained calculate the difference between the outputs for each individual switched component binding is needed. of the sampling gate and the detection circuit forms,

One form of equalizer that utilizes multiplication circuitry to operate in the time domain uses a cross filter. A traversing 55 of the current distortion component filte is a network that has several outputs with successive outputs of the locking handles having provided delay line. The circuit, an integrating circuit arrangement for further with each tap of the delay is separate integration of the multiplying line an adjustable attenuator connected. Circuitry deriving from successive-finally is a summing circuit for combining 6o lowing products via a plurality of data internals of such attenuated outputs of all valle and a limiter circuit arrangement for Taps provided. Control the setting of the attenuators in

A well-known, automatically adjustable attenuator- inverse relationship to the polarity of the separated Fungelement comprises a cross filter of the above-mentioned outputs of the integration circuit arrangement. described structure and a reversible electrical 65 In the drawing is the block diagram of a niche digital counter attached to an ohmic damping automatic equalizer of the invention, manager with a large number of discrete attenuators fation growth steps is coupled. Before the data, a correlation between the samples of the

The output of the transverse equalizer and the received one has a delay line 12 which, in the case of 13 data signals, terminates the polarities of the interference composition without reflection and is provided with a plurality of single-pulse impulse response taps 14, 4 to 14, which are equidistant from the transmission channel and uses this polarity - At intervals corresponding to the reciprocal of the syntäts for determining the direction of one another, the chronological data symbol rate to which the delayed incremental settings of the line 12 are connected. A plurality of adjustable taps of the equalizer assigned attenuable attenuator elements ISA to 15 E are located on the elements. In the embodiment shown, 14, 4 to 14 E of the delay line 12. The data signals are formed by binary polar signals. A summing circuit 16 serves as a common element, but is not limited to this. OK connection for the outputs of all attenuators

The aforementioned interference components 15. Between the output of the summing circuit th are intersymbol interference components, and the data sink is a sampling gate 17, the d. i.e., when digital data is actuated via a distorting at appropriate sampling times, and Message channel are transmitted, caused the detection circuit a binary limiter 18 to Channel a temporal dispersion of the various detection and reconstruction of standardized Mar-Fourier frequency components each digital pulse and distance data bit. The data sink 19 is ses so that when the rate at which these pulses any data consumer, e.g. B. a computer, are transmitted, is sufficiently high, the Im- an office machine or a telecommunications recording pulse tend to interfere with each other, voltage device.

That is, a pulse can be subject to interference with the preceding 20 The cross filter, as is known, causes the outgoing and subsequent pulse distortion of a distorting channel by adjusting, whereby the decision whether the reference tap attenuator is such that the one pulse in a given time slot In fact, the main pulse-to-pulse response may or may not be present, extremely difficult to maintain, and by adjusting the side tap hit is. 25 attenuators in such a way that a compensation of the inter-The inter-symbol interference component of the generating component in the sense of a reduction of the effective impulse response behavior of the over- to minimum values at the sampling times of the transmission channel is chosen here as an example. The equalizer according to the invention is intended for use in a system for the th case of the transmission of polar binary data, in which a cross filter of finite length judges a distortion of a transmission channel by sampling the analog output of the cross filter with an equalizer at a rate that corresponds to the rate under which the data can be transmitted over the channel by determining the polarity of the samples, by limiting these samples to the outputs at each tap and by determining the received data sequence, by counter-rotating, incremental pre- or subtracting the current standardized emp 35 Downgrading the attenuator settings on each captured data symbol from the current analog tap. All output samples result from the output sample value to determine an existing impulse response behavior of the transmission error component by correlating the channel to individual impulses which are fed to the transmission error component with the earlier, now channel, specifically for test purposes. It and later received data bits within the 40 have now been found that these same principles of the equalizer range can be applied to obtain a series of adaptable pro, ie product terms corresponding to successive components, which are equivalent to sampling times for the single pulse response behavior and by averaging several sol product terms can be used over a number of sampling intervals during normal comparing. The polarity of these mean values will then be judged and determined by a limiter circuit. Finally, it appears expedient at this point to set the attenuators at each tap of the equalizer incrementally, to be precise against it. It is assumed from the data source 10 that these polarity determinations are in progress. that it generates a random synchronous sequence of data. A data source 10 generates polar, synchronous 50 symbols a " binary message data based on baseband generated in T-second intervals. This data is transmitted via the medium of a transmitted message. These data symbols are to be supplied to the data sink 19 on a transmission channel 11 either on a baseband basis. Each individual or after previous modulation with a carrier symbol a _n can with the same probability be entfrequency to a distant point above, neither positive nor negative. Carrying each symbol a _n and there on a baseband basis or according to one would form a demodulation to a consumer circuit in an ideal transmission channel, i.e. a time sequence χ (ί), where t = nT and η is all a "data sink" 19 supplied. Should the frequency- integer values between + and - be infinitely dependent on the attenuation characteristic of the over-. Only in the case of n = 0 does χ (ί) have a large carrying channel 11 that does not run flat or should have a value other than 0. For all other values the phase characteristic is not linear with the frequency of η χ (ί) = 0. Therefore, a sequence will depend on data, then the message signals delivered to the data sink 19 symbols a _{n will} not interfere with the η Τ , if they are missing When passing through a non-ideal overdistortion of a temporal dispersion and a counterbalance channel 11, the ideal pulse-dependent interference is subjected. 65 speed χ (t) into a non-ideal dependency h (i) trans- To eliminate the distortion, a transverse formation is used in which, in addition to the equalizer filter other than 0, between the transmission channel 11, the main component at n = 0 is most likely and the data sink 19 is used. The cross filter is a meaningful component different from 0 for both

5 6

lei with the sign occur with other values of η . and that the output of the limiter 18 is therefore standardized, the uniform amplitudes occurring at the times η Γ is standardized, the data symbols a _{n of} a sequence is to a certain extent signal on the line 29 the product h _Q a ₂ alone mutually interfere with one another. equivalent to. The signal on line 28 is y ₂ , the

The cross-filter delay line 12 provides a 5 which also contains the term h ₀ a ₂ , among other things, a practical means of separating the main component. Pulse representation h (t) at its output taps therefore has the error part of the equation for 14yi to 14E, the second sampling time at intervals of T seconds. The subtracting circuit 32 may be located apart from each other. The attenuators io expediently have an inverter whose 15 A to 15JE of each tap 14 ^ 4 to 14E can input to the line 29 is connected, as well as individually so that they the tap an effect amplifier, one input with outputs with factors multiply that lie between the inverter and its other input with the +1 and -1. That the main component to line 28 is connected. The output of the arranged attenuator 15 C at the reference tap 14 C is 15 stronger then the output of the subtraction shell is preferably set so that the amplitude of the device.

Main momentum component h _{0 the} same at all times - The error terms of the equation can be seen-

is shaped. The other attenuators are borrowed in such a way that when the error antenna is multiplied by a ₃ that it becomes the secondary components of the radio, the next following data symbol, the term tion h (i) for n = 0 within the range of the ao Zi _-1 O _{3 will have} the sign of h_ _x , equal delay line 12 present number of valid whether a _{3 is} positive or negative. Reduce each of the remaining taps to 0. In the drawing, however, terms have the same probability, for the sake of clarity, only five taps to be positive or negative, there be. The summation of the individual outputs sign is determined jointly by the attenuator elements 15 ^ 4 to 15 E in the summing 25 sign of the interference component and the circuit 16 when the main function composite sign of the data symbol. It can therefore be centered at tap 14 C and if it is concluded that, if the products of the pre-attenuator are optimally set, Zi ₀ plus existing error with the next following data, a minimal residual component because of the end symbol is continuously taken and over be a reasonable borrowed length of delay line. 30 timespan, the core h _ _t

The attenuator settings can be isolated on the basis of the impulse function. The basis of measurements of single pulse functions remaining error terms, which are arbitrary, will be made h (t) , according to the invention each will tend to cancel, but these attenuator settings are adaptable to hand.

From measurements of the superimposed pulse functions 35 products of the error present at the output of the h (t) in a normal message data sequence makes subtraction circuit 32 with others in the vicinity. In the case of a sequence of overlapping pulse data symbols, the other terms of the functions h (i), the overall function will generate an analog pulse function. The remainder of the figure shows its signal, which is to be denoted by y (t) , where an arrangement for generating these products and for each individual sample y _m equal to the sum of 40 mean values.

of the separated products of consecutive data- The error output of subtracter circuit 32

Symbols a _m _ _n and the components of the individual is in an ordinary delay unit 30 impulse function K _n . For a specific case, the number of sampling times between the center tap 14 C of the delay line 12 and 12 is obtained for any second sampling time

(m = 2) for the summation the following expression: 45 the last tap 142? delayed. For one with five

y = h_α + h α + h α + h α + h α taps provided delay line is the for

^{2 2 i} ~ ^{12 02} * * ² ° ' the delay unit 30 required delay

This summation is found at the output of the tion equal to twice that between

Sampling gate 17 at the arbitrarily selected two adjacent taps on the delay line 12.

th sampling time. 50 The purpose of the delay unit 30 is to provide a

The main stream, the largest of the equation, is effective correlation between past and

h _o a ₂ . To enable the remaining terms and the other, non-future functional components.

are error components that make the successive data symbol assessments in the

represent the entire intersymbol interference at the observed output of the limiter 18 on the line 29 sampling instant. The first requirement for 55 to be in the individual stages 24 ^ 4 to 24 E of a determination of the attenuator settings is that the usual shift registers are stored. The content

Isolate error terms. These are generally these stages will be from right to left below the small compared to the main term. An assessment control of appearing on a line 27

of the data symbol is shifted by limiting the shift pulse. A clock generator 25

The output of the sampling gate at each sampling time in 60 generates clock pulses on line 27 at intervals

binary limiter 18 obtained, a threshold value of T seconds in the usual way, and its circuit of any known type. The loading operation can, if necessary, be synchronized with transitions in the limiter output signal is the data symbol a _m , the received signal wave.

can be either positive or negative. This becomes the one saved in the intermediate level 24 C.

Symbol is given to data sink 19 and 65 data symbol is considered the current symbol,

also available on a line 29. then those who are in stages 24 A and

Assuming that the main components h ₀ 24 B are stored, the penultimate or last sym-

the impulse function from symbol to symbol constant bol and those in stages 24 D and 24 E

are saved, the next two future symbols. Since the error signal on the line 31 has been delayed by two time units, a multiplication of this error signal by the contents of the shift register center column 24 C represents a correlation between the current data symbol and the current error signal. Averaging a sequence of such products leads to a good one Assessment of the main component Zi _{0 of} the momentum function. Similarly, it can be seen that the correlation between the contents of the other shift register stages on the error signal on line 31 provides judgments for other impulse function components.

Accordingly, conventional multiplier circuits 23 A to 23 E are connected to the outputs of the corresponding shift register stages 24 ^ 4 to 24 E. The other inputs of the multiplier circuits are common to the conductor 31, which carries the error signal. Since the quantities stored in the shift register are only signed, the multiplier circuits can be inverting amplifiers which are switched into or removed from the circuit, specifically in accordance with the sign of the contents of the shift register stage. Successive products are averaged out in low-pass filters 22.4 to 22 E which are connected to the outputs of the corresponding multiplier circuits 23/4 to 23 E. The low pass filters integrate successive inputs in a well known manner.

A plurality of binary limiter 2OA to 20 E form the means for determining the sign of the impulse function assessed components. The outputs of these limiters can be used to control corresponding reversible step counters (not shown) that are assigned to the attenuators 15 A to 15 E.

The time over which the averaging of the products between the error signals and the data symbols occurs is determined by a counter 26 and a gate 21. The counter 26 is from the clock generator 25 controlled and provides an output signal when a preset count value is reached. To the show of the counter output signal, the switches 21 ^ 4 to 21E within the gate 21 are actuated. These switches are indicated schematically in the drawing by crosses. The contents of the low-pass filter 22 are therefore given periodically to the limiters 20.

The setting of the attenuator 15 C at the reference tap 14 C is dependent on a correlation between the present error and the present data symbol. Therefore, the setting of this attenuator maintains the main component h _{0 of} the pulse shape from symbol to symbol at the same value and maintains the earlier assumption that the output of subtracter 32 is the error signal containing only interference components of the channel pulse function.

On the other hand, the settings of the remaining attenuators 15 depend on correlations between the present error signal and past or future data symbols. Hence look for this Attenuators automatically adjust the individual intersymbol interference components to be reduced to minimum values at sampling intervals in the error signal.

The time over which successive samples must be averaged, and consequently the The value of the count preset in the counter 26 is a comparatively complicated function of the size the incremental steps provided in the attenuators 15 and the degree of distortion and Noise in the transmission channel 11. For transmission over average data transmission lines at a transmission rate of 2400 symbols per second it was found that the counter 26 for the illustrated has five taps Equalizer should be set to count to around 20. A longer delay line will be deliver less residual distortion. A shorter averaging time tends to result in incorrect attenuator settings to create. A longer averaging time increases the setting time without a corresponding one Gain in accuracy. The setting time refers to the interval that is required to move the equalizer from a reference state to its optimal settings bring up the point in time at which all attenuators are in a random gear (freewheeling state). Any changes in the properties of the transmission channel that occur over time after the initial Correction of distortion occurs automatically.

The illustrative embodiment is described for use with binary data sequences. the However, the invention is equally applicable to a multi-level data sequence. In the multi-level case, should Provision is made for assessments of the momentum function components at each level of subdivision occur. The limiter 18 would then be multi-stage and quantized samples of the Supply analog output of the equalizer. There would also be a digital to analog converter between the line 29 and the subtracting circuit 32 are to be used to guide the determination of the error signal. A shift register 24 would be required for each stage level. Similarly, the rest would of the circuit, the multiplying circuits 23, the filters 22, the switches in the gate 21 and the binary Limiter can also be multiplied.

Claims (4)

Patent claims: 1. Circuit arrangement for obtaining the optimal settings of the attenuators of a cross-equalizer, which compensates for the distortion of digital pulse signals that are transmitted from a data source via a distorting transmission channel at a predetermined pulse repetition frequency, characterized by a sampling gate (17) which, at the pulse repetition frequency, the output amplitude of the Equalizer (12, 13, 14/4 to 14 E, ISA to ISE) scans after the signals have passed the channel (11) and the equalizer, a detection circuit connected to the output of the equalizer (binary limiter 18) to obtain a signal which is judged to represent the digital pulse signals, a subtracter (32) which forms the difference between the outputs of the sampling gate (17) and the detection circuit (18) to obtain a total distortion component, a multiplier circuit arrangement (24 A to 24 E, 30, 23 A to 23E) to multiply the current one 909 519/104 Distortion component with successive outputs of the detection circuit (18), one Integrating circuit arrangement (22 ^ 4 to 22JS) for separately integrating the from the multiplier circuit arrangement resulting successive products over a plurality of data intervals and limiter circuitry (20 ^ 4 to 20 E) to control the setting of the attenuators (15 ^ 4 to 15 E) in reverse Relationship to the polarity of the separate outputs of the integrating circuitry (22 ^ 4 to 22E). 2. Circuit arrangement according to claim 1, characterized in that the following components are provided in the multiplier circuit arrangement: a shift register with several stages (24 ^ 4 to 24E), a delay element (30) of fixed delay which delays the total distortion component from the subtracter (32), to enable the correlation between the current output of the sampling gate (17) and earlier, present and later output signals of the sampling gate (17), and a plurality of multiplying circuits (23 ^ 4 to 23E) connected to the delay element (30) in common, and to one stage (z. B. 24 E) of the shift register (2AA to 24 E) are switched on individually, the content of the shift register stage (eg 24E) determining whether the common input signal is effectively multiplied by plus or minus one. 3. Circuit arrangement according to claim 1, characterized in that for controlling the setting of each of the attenuators (15.4 to 15 E) the multiplier circuit arrangement has a corresponding plurality of multiplier circuits (23 ^ 4 to 23 E) and shift register stages (24 Λ to 24 E) , the integration circuit arrangement has a corresponding plurality of low-pass filters (22 ^ 4 to 22 E) and the limiter circuit arrangement has a corresponding plurality of limiter circuits (20A to 20 E) . 4. Circuit arrangement according to claim 1, characterized in that a clock generator (25) operating at the pulse repetition frequency is provided, further a counter (26) which, under the control of the clock generator, counts a predetermined number of digital pulses and thereby determines the sampling interval and a gate circuit (21) which, under the control of the counter (26), connects the integrating circuit arrangement (22A to 22E) and the limiter circuit arrangement (20 ^ 4 to 20E) to one another at the end of the sampling interval. 1 sheet of drawings