RU2108659C1 - Adjustable digital delay line - Google Patents

Abstract

FIELD: pulse engineering; radars, radio navigation, telemetering, pulse radio communications, measurement technology, and compute engineering. SUBSTANCE: delay line has clock generator, variable-ratio frequency divider, input, output, and code buses; newly introduced in delay line is random-access memory; in addition, clock generator is provided with second output connected to resolution input of random- access memory whose write/read input is connected to first output of clock generator and to clock input of variable-ratio frequency divider whose data inputs are connected bit-by-bit to code buses while output of each bit of this frequency divider is connected to respective address input of random-access memory whose data input is connected to input bus and output, to output bus. EFFECT: improved resolving power and simplified design of line. 1 dwg

Description

 The invention relates to a pulsed technique and can be used in radar, radio navigation, telemetry and pulsed radio communications, in measuring and computing.

 Known digital adjustable delay line, selected as a prototype, containing a clock pulse generator (GTI), two AND elements, two counters, AND element, register, buses: code, initial settings, input and output (ed. St. N 1661966 , A1 H 03 H 9/30, H 03 K 5/153, 07/07/91).

 The code bus is connected directly to the information inputs of the register and one of the counters, and through the register to the information inputs of the second counter. In both cases, the counters are used as frequency dividers with variable division factors (DPKD).

Along with the advantages (multifunctionality), the adjustable delay line also has disadvantages:
the period of the input signal cannot be less than the delay time. After setting the delay code in the counters and the register (setting the initial state) and applying the input pulse until the counters and the register complete the work cycle and are not set back to the initial state, the second pulse cannot be given. The device does not respond to the input signal, which means that the device has a limited resolution;
the input pulse is fed by a logic zero and the delay operation depends on the duration of the input pulse. If the pulse duration is longer than the delay time, then this pulse will be shorter than the input pulse, i.e. information is distorted;
relative complexity of the circuit.

The objective of the invention is to increase the resolution while simplifying the device
The problem is solved in that in a digital adjustable delay line containing a GTI, a frequency divider with a variable division coefficient of the DPKD, a random access memory (RAM) is introduced, the input of which chip is connected to the first output of the GTI, the recording input is connected to the second output of the GTI and clock input DPKD, the information inputs of which are connected to the control bus, and the output of each trigger DPKD is connected bitwise with the address inputs of RAM, the information input and output of which are the input and output of the line rzhki respectively.

 Functional diagram of the device shown in the drawing.

The device consists of a clock generator GTI 1, DPKD 2, RAM 3, control bus 4, information input 5 and output 6, and the first input 7 of the GTI 1 is connected to the input "Crystal selection" RAM 3, the second output to the input "Record" RAM 3 and the clock input DPKD 2, the information inputs of which are connected to the control bus 4, and the output of each trigger DPKD 2 is connected to the input addresses of the rows and columns of RAM 3 bit, information input 5 and output 6 of RAM 3 are the input and output of the controlled delay line, respectively
Comparative analysis shows that the claimed technical solution differs from the prototype in that instead of two control counters (frequency dividers with a variable division coefficient - DPKD), one is used, the register is replaced with RAM, two And elements are excluded, the And element is NOT and the initial installation bus, changed communications.

 Therefore, this technical solution meets the criterion of "novelty."

 When comparing the claimed solution not only with the prototype, but also with other technical solutions in science and technology, no solutions were found that have similar characteristics.

 The scheme works as follows.

 The signals to the inputs "Crystal Choice" and "Record" must be generated and applied in accordance with the technical specifications for a specific type of RAM. If RAM with three output states is used, it is necessary to use an information storage element (for example, trigger, capacitor, etc.) at the output of the delay line.

 Consider the duty cycle of the delay line, which is determined by the division coefficient (N) DPKD 2.

 After setting the division coefficient in the DPKD 2, the level of the logical unit at input 8 reads the information recorded by the first pulse in the previous cycle of operation, and the level of the logical zero records the information received at input 5 for reading by the first pulse in the second cycle. The level of the logical unit of the second pulse coming in at input 8 reads the information recorded by the second pulse in the previous work cycle, and the level of the logical zero records information coming in at input 5 for reading in the second cycle, etc. The level of the logical unit of the last N-th pulse of reading information recorded by the last pulse in the previous cycle, and the level of the logical zero records information for reading the last pulse in the next cycle. At the same time, in the DPKD 2, the former (if there were no code changes on the control bus 4) is set to the division coefficient.

In parallel with the arrival of each write pulse in RAM 3 from the DPKD 2, a new address code is received via bus 9, and a signal for selecting a chip in RAM 3 is received through input 7. Thus, the signal delay in RAM 3 will be proportional to the period of the write pulse T _s and the division ratio DPKD 2
t = T _s • N.

 By changing the division ratio, it is possible to obtain a signal delay at output 6 relative to input 5 from one recording frequency period to N, the upper value of which is determined by the RAM capacity.

A continuous pulse sequence with any duty cycle can be fed to the delay input, and at the output each pulse will be delayed relative to its input by T _s • N.

 To exclude the appearance of distorted information at the output, the frequency of the recording pulses should be at least 2 times higher than the frequency of the input pulses.

 When implementing a delay line on 533, 564, and 537 series microcircuits, the input pulse sequence with a frequency of up to 1 MHz can delay m units of microseconds up to hundreds of milliseconds.

Claims (1)

 A digital adjustable delay line containing a clock generator, a frequency divider with a variable division coefficient, input, output and code buses, characterized in that a random access memory is inserted in it and the clock generator is equipped with a second output that is connected to the resolution input of the random access memory the write / read input of which is connected to the first output of the clock generator and to the clock input of a frequency divider with a variable division coefficient, inform translational bitwise inputs are connected to word lines, and each bit output of the frequency divider with a variable division ratio connected to a respective address input of the random access memory, an information input of which is connected to an input bus and an output connected to the output bus.