SU1251185A1 - Analog storage - Google Patents

Abstract

The invention relates to the field of computing, in particular to the technique of storage devices, and can be used for storing single electrical signals. The purpose of the invention is to increase speed and reliability by achieving a ram, a counter and a prohibitor, and their connection to a device containing a pulse generator, a comparison element, a linearly varying voltage gaiter, an AND element and a delay element. mi with known blocks and elements. 1 il.

Description

The invention relates to the numerical technique, in particular, to the technique of memory devices, and can be used for nominal single electrical signals,

The purpose of the invention is to increase the speed and reliability of the device.

The drawing shows a functional diagram of the proposed device.

The device contains a generator 1 of pulses, a generator 2 of a linearly varying voltage g, a comparison element 3, an element AND 4 a prohibition element 5, a RAM block 6, a counter 7 and a delay element 8. The drawing also indicates the control input 9, the information input 10 and the output AND device.

Analog storage device operates as follows.

A high potential is applied to the input 9, which determines the mode of recording (storing) of a single process. The cleaning of block 6 and the counter 7 are effected by, for example, applying signals to their wrapping inputs. This causes an erasure of a previously memorized single process. A single electrical process to be memorized is fed to the input 5 10 connected to one of the inputs of the comparison element 3.

To the other input of element 3 comparison I)

. A linearly varying voltage is supplied from the output of generator 2. When equality reaches the voltage ethos, an information pulse appears on the output of a comparison element 3 through an open element I. 4 Enter the control input of block 6. Prohibition element 5 at this time is closed. On ps the front edge of this pulse, information is written to the reversible counter 7 at the outputs, and the accumulator b on the rear edge shifts it by one bit to the right. Keeping in the delay element 8 for a time sufficient for recording information in block b, this pulse arrives at one of the control inputs of counter 7 and zeroes it by writing the front information of the imp block 6 through the information inputs. An information pulse resets a linearly varying voltage at the output of generator 2. As soon as it ends, generator 2 immediately forms

,,

A new linearly varying voltage, which is also reset, as compared to the voltage of a single process. Thus, at the output 11 of the device receives a single process, composed of triangular pulses.

The points of the vertices of these pulses display a single process on the screen of an oscilloscope connected by a signal input to the output 1 1 (bypassing the vertices of the triangular pulses can be distinguished, for example, using a peak detector connected between the output 11 and the oscilloscope input). Interval: the time between informational impulses carries information about the amplitude of triangular impulses. Generator 1 runs uninterruptedly. The pulses arriving at the counting input of counter 7 cause it to be directly counted. The logical states of the outputs change until the next information pulse a comes.

Thus, by the end of each time interval, limited by the moment of arrival of the information pulse (before the arrival of the information pulse), a binary code is set at the outputs of the revolving counter 7, corresponding to the ear of this interval, which is written in block 6 perpendicular to the front information pulse

When the block 6 is filled, the low potential j is given at the input 9, which prohibits the passage of pulses through the element 4 and the permit for the passage of pulses from one of the outputs of the reversing switch 7 through the element 5 of the ban, and also switches the reversible counter 7 to the counting mode. The device enters the storage process of a single process, in which there is a continuous circulation of information from one of the outputs to. one of its inputs through the reversible counter 7.

At one of the outputs of counter 7, an impulse appears at the moment it reaches the zero (initial) value. This impulse is an information impulse of a memorized single process. From the element of the prohibition element 5, it goes to the second input of the counter 7 and through the delay element 8 to the control input of the block 6. As a result, the recording

3

the binary code from the outputs of block 6 to counter 7. At the outputs of counter 7, this stroke is set, after which a pulse appears at the output of delay element 8 allowing the code to be written from the outputs of counter 7 to block 6. Signs of zero sign of output of element 5 through element 8 resets the linearly varying voltage generated by generator 2.

The time intervals between pulses coming from the control output of counter 7 when circulating in block 6 are equal to the corresponding time intervals between information pulses coming from the output of comparison element 3 when memorizing a single process.

As a result, the output of the device 11 periodically repeats the memorized single process composed of triangular pulses.

Thus, block 6 operates at the frequency of quantization of time intervals between information pulses (as in the prototype), and at the frequency of the information pulses themselves, which follow less frequently than quantizing pulses. Therefore, at the same speed and accuracy of displaying a single process, the proposed device uses block 6 at a lower frequency than the prototype and requires less information capacity.

So, if there are 256 time quanta between two informative pulses (pulse repetition periods, quantizing time interval), in the prototype, 256 bits of block 6 are required to memorize this time interval, and in the proposed device only 8 bits (one bit in each shift register of the block 6). In order to memorize this time interval, block 6 in the prototype carries out 256 information shifts, while the proposed device for the same time is only one, i.e. The performance of the proposed device is higher.

To eliminate the possibility of recording in the block 6 transients of the counter 7, the output of the generator 1 is connected to the synchronization input of the generator 2 of a linearly varying voltage. In p

As a result, the voltage at the output of generator 2 varies discretely (in steps) and synchronously with the output pulses of generator 1. For example, counter 7 counts on the positive edge of the pulse from generator output 1, and generator 2 changes its output voltage by negative . Therefore, the pulse at the output of element 4 cannot appear at the moment of transient processes at the outputs of counter 7.

Element And 4 and element 5 of the ban made in the form of keys.

Claims (1)

Analog memory device comprising a pulse generator, a comparison element, the first input of which is the information input of the device, a linearly varying voltage generator whose output is the output of the device and connected to the second input of the comparison element, the output of the comparison element is connected to the first input element And, the second input of which is the control input of the device, the output of element AND is connected to the first input of the generator of linearly varying voltage, the delay element, characterized in that, in order to increase the speed and reliability of the device, an RAM block, a reversible counter and an inhibition element, the first input of which is connected to the second input of the AND element and the first control input of the reversible counter, are entered into it, the output of the prohibition element is connected to the input of the delay element and the second control input of the reversible counter, the information inputs of which are connected to the outputs of the RAM block, the output of the pulse generator is connected to the second input of the generator linearly changing Directing to the w and with the third control input of the reversible counter, the input of the delay element is connected to the output of the element I and to the control input of the main memory unit, the information inputs of which are connected to the information outputs of the reversible counter, the second input of the prohibition element is connected to the control output reversible counter.