RU2023288C1 - Combination adder of structural codes - Google Patents

Abstract

FIELD: automatics, computer engineering. SUBSTANCE: combination adder has stages each consisting of three-input one-stage binary adder, majority element, four OR gates, four AND gates, two IMPLICATION elements, inhibition element. Second and third stages have one additional OR gate. EFFECT: increased speed of response of adder thanks to simultaneous summing of three numbers presented in binary excess minimal numbering system. 3 dwg, 1 tbl

Description

 The invention relates to automation and computer technology and can be used for parallel summation of multi-bit binary numbers.

 A device for adding numbers represented in a binary redundant number system containing a series-connected logical nodes and three-input single-digit binary adders (1) is known. The disadvantage of this device is its low performance.

, где n - разрядность операндов) подключены, соответственно, к первому и второму входам первого элемента ИЛИ и первого элемента И i-го разряда, выход первого элемента И данного разряда соединен с первым входом второго элемента ИЛИ i-го разряда, второй вход которого соединен с выходом второго элемента И i-го разряда, первый вход которого соединен с первыми входами третьего элемента ИЛИ, третьего элемента И, пятого элемента ИЛИ данного разряда и выходом переноса трехвходового одноразрядного двоичного сумматора (i+1)-го разряда, второй вход второго элемента И i-го разряда соединен со вторым входом третьего элемента ИЛИ i-го разряда и выходом переноса трехвходового одноразрядного двоичного сумматора (i-2)-го разряда, выход третьего элемента ИЛИ i-го разряда подключен к первому входу четвертого элемента ИЛИ данного разряда, выходы первого и четвертого элементов ИЛИ i-го разряда соединены соответственно с первым и вторым информационными входами трехвходового одноразрядного двоичного сумматора данного разряда, вход переноса которого подключен к выходу второго элемента ИЛИ i-го разряда, третий вход которого подключен к выходу третьего элемента И i-го разряда, второй вход которого соединен со вторым входом пятого элемента ИЛИ i-го разряда и выходом переноса трехвходового одноразрядного двоичного сумматора (i-3)-го разряда, третий вход пятого элемента ИЛИ i-го разряда соединен с выходом переноса трехвходового одноразрядного двоичного сумматора (i-5)-го разряда и третьим входом третьего элемента И данного разряда, четвертый вход которого соединен с входом разрешения суммирования в минимальной и оптимальной системах счисления и первым входом четвертого элемента И i-го разряда, второй вход которого соединен с выходом пятого элемента ИЛИ i-го разряда, а выход - со вторым входом четвертого элемента ИЛИ данного разряда, третий вход второго элемента И i-го разряда соединен со входом разрешения суммирования в "Фибоначчиевой" системе счисления.Closest to the invention is a combinational adder (2) containing in each category a three-input single-bit binary adder, four AND elements, five OR elements, the input buses of the first and second operands of each i-th digit (i = (i =

, where n is the length of the operands) are connected, respectively, to the first and second inputs of the first OR element and the first AND element of the i-th category, the output of the first AND element of this discharge is connected to the first input of the second OR element of the i-th category, the second input of which is connected with the output of the second AND element of the i-th category, the first input of which is connected to the first inputs of the third OR element, the third AND element, the fifth OR element of this category and the transfer output of the three-input single-bit binary adder of the (i + 1) -th discharge, the second input is second the AND element of the i-th discharge is connected to the second input of the third OR element of the i-th discharge and the transfer output of the three-input single-bit binary adder of the (i-2) th discharge, the output of the third OR element of the i-th discharge is connected to the first input of the fourth OR element of this discharge , the outputs of the first and fourth OR elements of the i-th category are connected respectively to the first and second information inputs of a three-input single-bit binary adder of this category, the transfer input of which is connected to the output of the second OR element of the i-th category, the third input of which is connected to the output of the third AND element of the i-th category, the second input of which is connected to the second input of the fifth OR element of the i-th category and the transfer output of the three-input single-bit binary adder (i-3) -th category, the third input of the fifth element OR i -th category is connected to the transfer output of a three-input single-bit binary adder of the (i-5) -th category and the third input of the third element AND of this category, the fourth input of which is connected to the input of the summation resolution in the minimum and optimal number systems and the first input of the fourth element AND of the i-th category, the second input of which is connected to the output of the fifth element OR of the i-th category, and the output - with the second input of the fourth element OR of this category, the third input of the second element AND of the i-th category is connected to the permission input summation in the "Fibonacci" number system.

 The disadvantage of this device is its low performance.

 The purpose of the invention is to increase the speed of the adder due to the ability to summarize simultaneously three numbers represented in a binary redundant minimum number system.

(i) ,, где α_i ∈ {0,1}
Ψ(i) =

,1
Значение Ψ(n+2) определяет мощность минимального n-разрядного кода.Any natural number A in the binary minimal number system is represented as a polynomial
A =

(i) ,, where α _i ∈ {0,1}
Ψ (i) =

,1
The value Ψ (n + 2) determines the power of the minimum n-bit code.

 The minimum number system assumes the presence of at least four zeros after each unit.

+

(

(

-

$\genfrac{}{}{0ex}{}{\text{при}}{\text{при}}$ $\genfrac{}{}{0ex}{}{\text{3}}{\text{i}}$ $\genfrac{}{}{0ex}{}{\text{≅}}{\text{>}}$ $\genfrac{}{}{0ex}{}{\text{i}}{\text{5}}$ ^{≅ 5}
Следовательно, правило сложения имеет вид
0 + 0 + 0 = 0
0 + 0 + 1 = 1
0 + 1 + 0 = 1
1 + 0 + 0 = 1
0 + 1 + 1 = 100001 при 3 ≅ i≅ 5
0 + 1 + 1 = 10000001 при i > 5
1 + 1 + 1 = 101001 при 3 ≅ i≅ 5
1 + 1 + 1 = 10100001 при i > 5
Анализ выражения позволяет предположить, что операция сложения будет протекать с появлением в ряде случаев промежуточных сумм. Это обусловлено приходом сигналов переноса в разряды, в которых есть единица. Однако, учитывая, что минимальная форма представления числе предполагает наличие не менее чем четырех нулей после каждой единицы, видно, что при наличии единицы в двух или трех слагаемых данного разряда возможен приход сигнала переноса только из (i+5)-го разряда, при одном слагаемом - из (i+5)-го и (i-2)-го разрядов.The addition method is based on expressions arising from the recurrence relation

+

(

(

-

$\genfrac{}{}{0ex}{}{\text{at}}{\text{at}}$ $\genfrac{}{}{0ex}{}{\text{3}}{\text{i}}$ $\genfrac{}{}{0ex}{}{\text{≅}}{\text{>}}$ $\genfrac{}{}{0ex}{}{\text{i}}{\text{5}}$ ^{≅ 5}
Therefore, the addition rule has the form
0 + 0 + 0 = 0
0 + 0 + 1 = 1
0 + 1 + 0 = 1
1 + 0 + 0 = 1
0 + 1 + 1 = 100001 at 3 ≅ i≅ 5
0 + 1 + 1 = 10000001 for i> 5
1 + 1 + 1 = 101001 at 3 ≅ i≅ 5
1 + 1 + 1 = 10100001 for i> 5
An analysis of the expression suggests that the addition operation will proceed with the appearance in some cases of intermediate sums. This is due to the arrival of transfer signals in the discharges in which there is a unit. However, taking into account that the minimal form of representing a number implies the presence of at least four zeros after each unit, it is clear that if there is a unit in two or three terms of this category, the transfer signal can only come from the (i + 5) -th category, for one term - from the (i + 5) th and (i-2) th digits.

Such an analysis shows that no more than four signals participate in the addition. In this case, the addition rule takes the following form:
1 + 1 + 1 + 1 = 1 0 1 0 11 0 1
Transfer to the (i-2) -th discharge is carried out without hindrance, when transferring to the (i-3) -th discharge, a transfer signal from the (j + 2) -th discharge (j = i-5) can come into it.

The table shows the signal values explaining the operation of the i-th single-bit adder
When compiling the table, it was assumed that the inputs of the three-input single-digit binary adder are fed signals of summable terms in this category a; b; c;
The table indicates: S is the signal of the sum of a three-input single-digit binary adder, P is the signal of the transfer of a three-input single-digit binary adder, Р _{i-2, i} , Pi _{+ 5, i} , Pi _{+ 2, i} , Pi _{+ 3, i} - transfer signals to the i-th digit of the adder, respectively, from the (i-2) th, (i + 5) th, (i + 2) th, (i + 3) th digits, S _i is the signal of the sum of a single-bit adder , Pi _{, i + 2} , Pi _{, i-5} , Pi _{, i-2} , Pi _{, i-3} are the transfer signals from the i-th digit of the adder, respectively, to the (i + 2) -th, (i- 5) th, (i-2) th, (i-3) th digits.

 Based on this logic, a combinational adder is constructed for three terms.

 Consider the example of adding the numbers A, B, and C.

B and CA = B = 00001000010000100001000
C = 00100000010000000100000
To add the numbers A, B, and C and minimize the sum code, 11 measures were required.

 The invention consists in the implementation of expressions (2), (3) in accordance with the table.

 In FIG. 1 shows a block diagram of a combinational adder for three terms; in FIG. 2 is a functional diagram of the pth discharge of the adder (p = 1,3,5-n); in FIG. 3 is a functional diagram of the qth discharge of the adder (q = 2.4).

 The combinational adder for three terms contains n (where n is the length of the operands) of bits 1, having outputs 2, 3 transfers, input buses of the first 4, second 5 and third 6 terms, the bus of the sum 7.

 Each pn bit 1, having inputs of 8-11 transfers, contains a three-input single-bit binary adder 12 with outputs 13, 14 of the sum and transfer, a majority element 15, four elements or 16-19, four elements AND 20-23, two elements IMPLICATION 24, 25, item BAN 26.

 Each qth discharge contains, in addition, an OR element 27 and carry inputs 28, 29, 30.

 Bit 1 is intended for summing the bits of terms and transfer signals entering this bit and outputting the value of the sum of this bit to the output bus 7 and transfer signals from this bit to neighboring ones.

 The OR element 27 is designed to generate a transfer signal from the fifth, sixth and seventh digits to the second and from the eighth and ninth digits to the fourth, respectively.

 Three-input single-bit binary adder 12 is designed to sum the bits of the terms and output values for further summing with transfer signals.

 Elements OR 16, OR 17 are designed to give a signal of the presence of transfer to this category.

 The majority element 15 is designed to provide a signal in the presence of two transfer signals in this category.

 The elements IMPLICATION 24, 25, PROHIBIT 26, the elements AND 21, AND 22 and the element OR 18 are designed to sum the signals from the three-input single-bit binary adder 14 and the transfer signals to this bit and output the value of the sum of this bit to the sum bus G.

 Elements AND 20 and OR 19 are intended for generating transfer signals from a given discharge to the (i + 2) th and (i-5) th digits.

 Element I 23 is intended for generating transfer signals from a given discharge to the (i-2) th and (i-3) th digits.

The device operates as follows:
Signals of the bits of the terms are fed to the inputs of a three-input single-bit binary adder 12. Depending on the values of the bits, signals are formed for further summing with the signals of transfer or output of the signal through the elements IMPLICATION 24, AND 21, 22, OR 18 to the sum bus 7.

 If there is “1” in this category, a single signal is generated in one of the terms at the output 13 of a three-input single-bit binary adder 12, which is fed to the inputs of the I 20 element and the I 22 element, the second input of which receives a signal from the IMPLICATION 24 element, indicating the absence of signals transfer to this category. From the output of AND element 22, the signal through the OR element 18 passes to the sum 7 bus. If there is a transfer signal to this bit, it goes through the OR element 17 and the PROHIBIT 26 to the inverse input of the IMPLICATION 25 element and locks it - the sum signal of this discharge is not generated. At the same time, the transfer signal to this discharge through the AND 20 and OR 19 elements passes to the transfer output 13 to the (i + 2) th and (i-5) th digits. Using "1" in one of the terms and two transfer signals to a given digit, the PROHIBIT 26 element is locked, the IMPLICATION 25 element is opened, a signal of the sum of this discharge and a transfer signal in the (i + 2) -th and (i-5) -th are generated discharges.

 If there is “1” in the two terms in this category, the signal from the output 14 of the three-input single-bit binary adder 12 passes through the OR 19 element to the transfer output 3 to the (i + 2) -th and (i-5) -th bits.

 With one transfer signal to a given discharge, it passes through the elements OR 17 and PROHIBIT 26 to the input of the element And 21, at the second input of which "1" from the output of the element IMPLICATION 24.

 With two transfer signals to this category, they are transferred through the majority element and OR 19 element to the transfer output 3 in the (i + 2) -th, (i-5) -th category.

 The presence of “1” in three terms leads to the formation of a signal of the sum of this discharge and transfer signals in the (i + 2) -th, (i-5) -th bits. The arrival at this time at a given bit of the transfer signal from the (i + 5) th discharge causes the formation of 23 transfer signals in the (i-2) th and (i-3) th bits from the transfer output 2 in the And element 23.

Claims (1)

COMBINATION SUMMER OF STRUCTURAL CODES, containing in each i-th digit ((i =

), where n is the length of the operands) a three-input single-bit binary adder, four AND elements and four OR elements, and the output of the first AND element of the i-th category is connected to the first input of the first OR element of this discharge, the second input of which is connected to the output of the second AND element of this discharge, the first inputs of the second OR element and the third AND element of this discharge are connected to the transfer output from the (K + 5) th discharge (k ∈ i, k =

, the output of the second OR element of the i-th discharge is connected to the first input of the fourth element AND of this discharge, the output of which is connected to the first input of the third OR element of this discharge, the transfer output from this discharge is connected to the inputs of transfers (j - 2) -th and (j - 3) th, (j ∈ i, j =

) discharges, characterized in that the OR elements, the majority element, two IMPLICATION elements, the PROHIBIT element, and two OR elements, respectively, in the second and fourth digits of the adder, the input buses of the first, second, and third operands of this bits are connected respectively to the first, second and third inputs of a three-input single-bit binary adder of the i-th category, the output of the sum of which is connected to the second inputs of the third and fourth elements And this discharge, to the first input of the second element AND of this discharge and to the inverse input of the first element IMPLICATION of this discharge, the output of which is connected to the first input of the first element AND of this discharge, the second input of which is connected to the output of the element BAN and the inverse input of the second element IMPLICATION of this discharge, output which is connected to the second input of the second AND element of the i-th discharge, and the direct input is connected to the second input of the third OR element of this discharge, the inverse input of the BAN element of this discharge and the output is major the first element of the i-th category, the first input of which is connected to the output of the fourth OR element of this category and the second input of the second OR element of this category, the output of which is connected to the direct input of the element of the PROHIBITION of the i-th category, the transfer output of the three-input single-bit binary adder of this category is connected to direct input of the first element IMPLICATION of this category and to the third inputs of the third elements AND and OR of this category, the output of the first element OR of this category is the output of the sum of the i-th category, the output of the third And element of each j-th category is connected to the first input of the fourth element OR (j - 2) -th category and the second input of the fourth element OR (j - 3) -th category, the output of the third element And the second category is connected to the first input of the fourth element OR the first bit, the output of the third element OR of each l-th bit (l ∈ i, l =

) is connected to the second input of the majority element of the (l + 2) -th category and to the third input of the second element of the (l + 2) -th category, the first, second and third inputs of the fifth element of the second category are connected respectively to the outputs of the third elements of the fifth , the sixth and seventh digits, the first and second inputs of the fifth OR element of the fourth category are connected respectively to the outputs of the third OR elements of the eighth and ninth digits, the inputs of the fifth OR elements of the second and fourth digits are connected to the third inputs of the majority elements with respectively of the second and fourth digits and to the first inputs of the second OR element and the third AND element of the second and fourth digits, the third OR element of each k-digit is connected to the third input of the majority element of the (k - 5) th category.

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