RU2251144C1 - Device for multiplication of numbers in "1 of 4" code - Google Patents

Abstract

FIELD: computer science.

SUBSTANCE: device, containing partial multiplication results block, adders block and control block, also has quaternion displacement register and result register in code "1 of 4", while partial multiplication results block has n+1 assembly of partial multiplication results in "1 of 4" code, where n - number of quaternary item bytes, adders block has n+1 adder in "1 of 4" code, result register in "1 of 4" code has 2n quaternion of quaternary bytes, control block has 2n "1 of 4" code control nodes.

EFFECT: higher trustworthiness.

4 dwg, 3 tbl

Description

The invention relates to computer technology and can be used to build computer systems with increased reliability of the issued data.

A device for multiplication is known (USSR AS No. 1024906, MKI 6 G 06 F 7/49, claimed 14.08.81, publ. 23.06.83) containing the registers of the multiplier and the multiplier, the result register, the sign analysis unit, the multiplication unit, the combinational adder and summing unit in a redundant number system. The device provides operations in a redundant number system.

The disadvantage of this device is that in the operating mode does not check the correctness of the issued data, which, in turn, does not make it possible to increase the reliability of the issued results.

The reasons that impede the achievement of the required technical result are the lack of tools that provide the ability to verify the correctness of the issued data code.

A device for multiplying numbers modulo is known (RF patent No. 2143723, MKI 7 G 06 F 7/52, claimed July 29, 1998, publ. 12/27/99), containing the first and second binary code converters for the first internal module, the first and second converters binary code for the second internal module, from the first to sixth blocks of AND elements, a table computer, unitary code converters for the first and second modules, and an adder for the module. The device provides multiplication of numbers in the system of residual classes for two modules.

The disadvantage of this device is that it does not check the correctness of the issued data, which, in turn, does not make it possible to increase the reliability of the issued results.

The reasons that impede the achievement of the required technical result are the lack of tools that provide the ability to verify the correctness of the issued data code.

A device for adding in the code “M from N” is closest to the claimed one, which allows one to obtain the product code of numbers in the code “M from N” in the form of a partial product and hyphenation value (USSR AS No. 1015372, MKI 6 G 06 F 7/49 , claimed July 17, 81, published April 30, 83) containing the registers of the first and second operands, a control unit, an addition matrix and a multiplication matrix, the first and second groups of outputs of the operand registers connected to the inputs of the addition matrix, the third groups of outputs of the operand registers connected respectively with first and second entrances a control unit, the first and second outputs of which are connected to the outputs of the device error signal, the outputs of the addition matrix are connected to the outputs of the sum of the device and the first inputs of the multiplication matrix, the second inputs of which are connected to the third outputs of the control unit, the outputs of the partial products and the outputs of the transfer signals of the multiplication matrix corresponding device outputs. In the embodiment of the device described in the description, a technical solution for multiplication in the hexadecimal code “2 of 4” is presented.

The first disadvantage of this device is that in order to obtain the final value of the product, it is necessary to convert partial works and carry signals on additional equipment.

The reasons that impede the achievement of the required technical result are that only partial works and hyphenation signals are outputted from the device.

The second disadvantage of this device is that it monitors the codes of the input operands, but there is no control of the result.

The reasons that impede the achievement of the required technical result are that the device lacks means to control the result of the multiplication operation.

The task to which the proposed technical solution is directed is to build computing systems with increased reliability of obtaining results and even distribution of energy during operation, which is especially important when implementing system equipment in the form of VLSI.

The technical result achieved by the implementation of the invention is to increase the reliability of the output while providing bitwise control of the result of the operation of multiplying numbers and uniform distribution of energy over the discharges during operation, which is especially important when implementing system equipment in the form of VLSI.

The essential features that match the prototype and the claimed device are as follows: the addition matrix in the prototype performs the functions of the adder block in the claimed device, the multiplication matrix in the prototype performs functions similar to the partial works block in the claimed device, the control block in the prototype performs functions similar to the control block in the claimed device.

The claimed technical result is achieved by the fact that in the device for multiplying numbers in the code “1 of 4”, containing a block of partial works, a block of adders and a control unit, the outputs of the control unit are connected to the outputs of the error indicator of the device, the notebook shift register and the result register are entered the code “1 of 4”, and the inputs of the four-digit bits in the code “1 of 4” of the first device factor are connected to the information inputs of the corresponding notebooks of the notebook shift register, the outputs of the lower notebook of which are connected to by the moves of the first group of the partial product block, the inputs of the second group of which are connected to the inputs of the quadruple bits in the code “1 of 4” of the second device factor, the outputs of the partial products block are connected to the inputs of the first group of the adder block, the inputs of the second group of which are connected to the outputs of the senior quadruple bits group the result register in the code “1 of 4”, the outputs of the groups of the lower and upper four-digit bits of which are connected to the inputs of the control unit, the outputs of the adder block are connected to the information inputs and four-digit bits of the result register in the “1 of 4” code, the installation input of which is connected to the device recording input and the notebook shift register entry, the tetrad shift input of which is connected to the result register record input in the “1 of 4” code and the device shift clock input , the input of the constant 0 in the “1 of 4” code is connected to the inputs of the constant 0 of the partial product block and the adder block, while the partial product block contains n + 1 partial product nodes in the “1 of 4” code, where n is the number of four of the total digits of the factors, the inputs of the quadruple digits in the code “1 of 4” of the first and second factors from the first to the n-th nodes of partial products in the code “1 of 4” are connected to the inputs of the corresponding digits of the first and second groups of the block of partial products, the outputs of which connected to the outputs from the first through the (n + 1) th nodes of partial products in the code “1 of 4”, the inputs of the four-digit bits in the code “1 of 4” of the first and second factors of the (n + 1) th node of the partial works in the code “1 of 4” is connected to the input of the constant 0 of the block part works, the outputs of the first and second transfers of the i-th node of partial works in the code “1 of 4”, where i = 1,2, ..., n, are connected to the inputs of the first and second transfers of (i + 1) -go, respectively of the partial product node in the “1 of 4” code of the partial product block, the adder block containing n + 1 adder in the “1 of 4” code, the inputs of the four-digit bits in the “1 of 4” code of the first term from the first to (n + 1) -th adders in the code “1 of 4” are connected to the inputs of the corresponding bits of the first group of the adder block, the outputs of which are connected to the outputs with first in the (n + 1) -th adders in the “1 of 4” code, the input of the four-digit discharge of the second term of the (n + 1) -th adder in the “1 of 4” code is connected to the input of the constant 0 of the adders block, the transfer output is i- adder in the code “1 of 4”, where i = 1,2, ..., n, is connected to the transfer input of the (i + 1) -th adder in the code “1 of 4”, the inputs of the four-digit bits of the second term from the first on the n-th adders in the code “1 of 4” are connected to the inputs of the corresponding bits of the second group of the block of adders, while the result register in the code “1 of 4” contains 2n tetrads of four-digit bits, outputs and naming inputs from the nth to the 2nth tetrad of quadruple digits of the result register in the code “1 of 4” are connected respectively to the outputs of the highest group of quadruple digits and, respectively, from the first to (n + 1) th information inputs of the quadruple digits of the result register in the code “1 out of 4”, information inputs from the first to (n-1) tetrads of four-digit bits of the result register in the code “1 of 4” are connected to the outputs of the four-digit bits, respectively, from the second to n-th tetrads of the four-digit bits of the result register in the code “ 1 out of 4 ”, with the block the role contains 2n nodes of the control code “1 of 4”, the inputs and outputs of which are connected respectively to the corresponding four-digit bits of the inputs and outputs of the control unit.

The possibility of data control is based on the fact that the quaternary code “1 of 4” always contains only one unit (all possible combinations of this code 0001 = 0; 0010 = 1; 0100 = 2 and 1000 = 3) and, therefore, out of the total number of possible erroneous combinations for a 4-bit word equal to 15, the number of unidentified errors will be only 3. Thus, the claimed device provides recognition of 80% of errors.

Of the possible options for the codes “M of N”, the code “1 of 4” is most effective. First, the operation of converting a binary code to the code “M from N” and vice versa, characteristic of digital processing systems containing a number of subsystems, for M ≠ 1 and N ≠ 2 ^m , where m = 1, 2, ..., requires analysis of the entire sequence of binary code digits, which leads to very large equipment costs during implementation. For example, when constructing such a code converter for a 32-bit binary number using a memory block, it will take from 5 to several tens of megabytes. The circuitry implementation of such converters will require equipment, the volume of which will significantly exceed the volume of equipment of operating devices.

On the other hand, to convert the “1 out of 2 ^m ” code, you need D / m (D is the bit depth of the binary code) decoders for the binary code conversion and the same number of encoders for the inverse transformation. This is due to the fact that the conversion is bitwise. For example, for a 32-bit binary, the code converter is “1 out of 2”, “1 out of 4”, “1 out of 8”, etc. will require respectively 32 single-input, 16 two-input, 11 three-input, etc. decoders and as many encoders for the inverse transform. Such a circuitry solution requires a minimum amount of equipment and is effectively implemented when building systems on VLSI or FPGA crystals.

Secondly, the implementation of circuitry solutions for codes “1 of 2”, “1 of 4”, “1 of 8”, etc. also has varying effectiveness. This is due, on the one hand, to a different number of recognized errors and, on the other hand, to a different excess of the amount of required equipment for processing compared to binary code. Therefore, to assess the effectiveness of using one or another “1 of 2 ^m ” code, it is advisable to consider the ratio of the percentage of detected errors to the excess of the required equipment with respect to the binary code.

, тогда количество необнаруживаемых ошибок составит

-1 (одна верная комбинация). Количество всех возможных ошибочных кодов, очевидно, равно 2^N-1. Тогда доля обнаруживаемых ошибок Q определяется соотношениемIn general, the number of combinations for the code “M of N” is equal to

then the number of undetectable errors will be

-1 (one valid combination). The number of all possible error codes is obviously 2 ^N -1. Then the proportion of detected errors Q is determined by the ratio

.

.

=2^m, тогдаFor codes “1 of 2 ^m ”, the value

= 2 ^m , then

.

.

.The excess of the required equipment K for the codes “1 of 2 ^m ” is obviously equal to

.

Then the efficiency of using the code “1 of 2 ^m ”

Table 1 shows the calculated data for the codes “1 of 2 ^m ” for various values of m.

Table 1 Bit depth m Corresponding code “1 of N” Percentage Detected Q errors Equipment coefficient K Efficiency E 1 “1 out of 2” 0.67 2.00 0.33 2 “1 from 4” 0.80 2.00 0.40 3 “1 out of 8” 0.97 2.67 0.36 4 “1 from 16” 0.99 4.00 0.25 5 “1 from 32” ≅ 1 6.40 0.16 6 “1 from 64” ≅ 1 10.67 0.09

From the data given in table 1, it can be seen that the code “1 of 4” having the maximum value of the efficiency indicator E = 0.40 has the highest efficiency.

In addition, the energy distribution during data input, storage and output in the “1 of 4” code is always the same for all bits of the data code, because structurally, each quadruple discharge contains strictly one high and three low potentials. This property is especially important when creating devices and systems based on VLSI crystals.

Figure 1 presents a functional diagram of a device for multiplying numbers in the code “1 of 4”; figure 2 presents an embodiment of a partial work unit in the code “1 of 4”; figure 3 shows an implementation option of the adder in the code “1 of 4”; figure 4 shows the timing diagrams of the control signals.

A device for multiplying numbers in the code “1 of 4” (Fig. 1) contains a notebook shift register 1, a partial product block 2, an adder block 3, a result register in a code “1 of 4” 4, a control unit 5, and a notebook shift register 1 implements a shift to the lower digits one notebook at a time and contains n tetrads of quadruple digits in the code “1 of 4” 1 ₁ -1 _n , where n is the bit depth of the quadruple code of factors, the block of partial products 2 contains n + 1 node of partial products 2 ₁ -2 _{n + 1} , adder block 3 contains n + 1 adder in code “1 of 4” 3 ₁ -3 _{n + 1} , the register of result 4 in the code “1 of 4” contains 2n tetrads of four-digit bits in the code “1 of 4” 4 ₁ -4 _2n , the control unit 5 contains 2n nodes of the control code “1 of 4” 5 ₁ -5 _2n .

A possible variant of the partial works node in the code “1 of 4” 2 _i (Fig. 2) contains from the first to the fourth group of elements AND 6-9, the first group of elements OR 10, the fifth group of elements AND 11, the second group of elements OR 12, s the first through third elements are NOT 13-15, the first through fourth elements OR 16-19, the first and second elements AND 20 and 21.

A possible adder in the code “1 of 4” 3 _i (Fig. 3) contains from the first to the fourth group of elements AND 22-25, the first group of elements OR 26, the fifth group of elements AND 27, the second group of elements OR 28, the element NOT 29 and element OR 30.

A device for multiplying numbers in the code “1 of 4” works as follows.

The numbers X and Y are represented in the quaternary system

n is the number of quaternary digits.

The device works according to the standard algorithm:

where x _i and y _{i are} represented in the code “1 of 4”, the summation of partial products is carried out according to the corresponding weights of the four-digit digits. Table 2 gives the codes for converting input values to output when multiplying the four-digit bits of the factors in the code “1 of 4” and the conditions for the occurrence of one transfer of P and two transfers of PP to the next four-digit discharge.

table 2 Quaternary code 0 1 2 3 Multipliers “1 out of 4” 0001 0010 0100 1000 0 0001 = 0001 = 0001 = 0001 = 0001 1 0010 = 0001 = 0010 = 0100 = 1000 2 0100 = 0001 = 0100 = 0001 + P = 0100 + P 3 1000 = 0001 = 1000 = 0100 + P = 0010 + PP

Obviously, the occurrence of one or two transfers from the previous discharge does not necessitate the formation of an additional signal of the third transfer, because the maximum value of the partial product code with an active signal even of two transfers from the current discharge is 0010 and, therefore, even two transfers from the previous discharge will give a result of 1000 without the need to generate an additional transfer signal.

Table 3 gives the codes for converting input values to output when summing the four-digit bits of the terms in the code “1 of 4” and the conditions for the occurrence of transfer P.

Table 3 Quaternary code 0 1 2 3 The terms “1 of 4” 0001 0010 0100 1000 0 0001 = 0001 = 0010 = 0100 = 1000 1 0010 = 0010 = 0100 = 1000 = 0001 + P 2 0100 = 0100 = 1000 = 0001 + P = 0010 + P 3 1000 = 1000 = 0001 + P = 0010 + P = 0100 + P

Obviously, the occurrence of transfer from the previous discharge does not necessitate the formation of an additional transfer signal, since the maximum value of the sum code with the active transfer signal from the current bit is 0100 and, therefore, the transfer from the previous bit will give the result 1000 without transfer.

A device for multiplying numbers in the code “1 of 4” works as follows. First, a Write pulse is applied to the input of the device (Fig. 4), on the trailing edge of which the operand of the factor Y is recorded in register 1 of the tetrad shift and the result is set to zero in the code “1 of 4” of register 4. Each of the quadruple digits of _i is represented by the code “1 of 4” y _0i y _1i y _2i y _3i and occupies the ith tetrad of register 1 of the tetrad shift. The output of the lower notebook of register 1 is connected to the inputs of all nodes 2 _{i of} partial works in the code “1 of 4” of block 2 of partial works. The other inputs of nodes 2 _i are supplied with the four-digit bits of the second factor in the code “1 of 4” x ₀₁ X ₁₁ X ₂₁ X ₃₁ - X _0n X _1n X _2n X _3n , which are held during the entire calculation process. For this purpose, an external register (not shown in FIG. 1) can be used, the recording in which can be performed by the same pulse as in the register 1 of the notebook shift. The nodes of partial products 2 _{i of} block 2 are combinational, therefore, after the transition process, at the output of the nodes of partial products 2 _i, in accordance with the algorithm, the value y ₁ × 4 ⁰ (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ). The number of nodes of partial products 2 _{i of} block 2 is one more than the number of bits of the factors n, because a situation of the occurrence of one or two transfers to the (n + 1) -th discharge is possible. A similar situation occurs with adders 3 _i block 3 adders, which are also n + 1.

The adders 3 _i in the code “1 of 4” of the adder block 3 are also combinational, the inputs of which are supplied the codes of partial products corresponding to the weights of the quadruple digits from the corresponding nodes 2 _i and the values of zeros from the result set to zero in register 4. At the outputs of the adders of block 3, after the transition process, the value of the partial sum of products y ₁ × 4 ⁰ (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ), which is on the leading edge, will be set SI clock (Fig. 4) will be entered in the corresponding bits of the register of result 4. On the trailing edge of the same pulse, a shift is made by one quadruple digit in the tetrad shift register. Thus, the value of ₂ appears at the inputs of the first group of block 2 of partial products, and the code of partial product of ₂ × 4 ¹ (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ), which is added up bitwise at adders 3 _i with the accumulated partial sum code shifted by one quadruple toward the lower digits in the result register 4. Thus, at the output of adder block 3, the next partial sum code is generated at ₂ × 4 ¹ ( x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ) + y ₁ × 4 ⁰ (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ), which is entered in the register 4 results second pulse of SI. In this case, the least significant bit of the partial sum of ₁ × 4 ⁰ × x ₁ × 4 ⁰ without summation is overwritten from the output of the n-th fourth digit of register 4 of the result to the (n-1) th digit. On the trailing edge of the second SI pulse, a shift is made by one four-digit discharge of the factor Y in register 1 of the tetrad shift.

In the future, the calculation process is cyclically repeated and after the supply of the nth SI pulse in the result register 4, the total sum of partial products X × Y = y _n × 4 ^n-1 (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ) + y _n-1 × 4 ^n-2 (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ) + ... + y ₂ × 4 ¹ (x ₁ × 4 ⁰ + x ₂ × 4 ¹ + ... + x _n × 4 ^n-1 ) + y ₁ × 4 ⁰ (x _l × 4 ⁰ + x ₂ × 4 ¹ + .. . + x _n × 4 ^n-1 ), which is located in 2n quadruple digits z ₁ -z _2n in the code “1 of 4”. The outputs of the quadruple discharges z ₁ -z _2n go to the inputs of the corresponding control nodes of the code “1 of 4” of the control unit 5, and if there is a discrepancy to this code in at least one discharge z _{i, an} error signal Osh _i will be output to the device. The design of the “1 of 4” code control units is known (see “Device for code control“ 1 of n ”patents SU 1195451, MKI 6 N 03 M 7/22; SU 1683178, MKI 6 N 03 M 7/22).

The combination nodes of the partial works in the code “1 of 4” 3 _i (FIG. 2) of the block of partial works work as follows. Each group of elements And 6-9 contains 4 elements And, forming a 4 × 4 matrix. At the first inputs of the elements And from the first to fourth groups the binary components of the four-digit discharge of the factor at _0i at _1i at _2i at _3i are fed, at the second inputs of the elements And from the first the fourth of each group contains binary components of the four-digit discharge of the factor x _0i x _1i x _2i x _3i . At 16 outputs of the matrix of elements And, obviously, only one “1” can appear, the remaining zeros (any other combination, passing through the logic elements of node 2 _i and the combinational adder 3 _i will cause an error signal at one of the outputs of the control unit 5) . The outputs of the elements AND groups 6–9 are connected to the inputs of the four elements OR of the first group 10 in such a way that the necessary result of the partial product is realized at their outputs in accordance with Table 2. At the same time, at the output of the OR element 16 and the OR element 18, a signal of the sign of the first transfer P $\genfrac{}{}{0ex}{}{\text{one}}{\text{i}}$ , at the output of the OR element 19, a signal of the sign of the second transfer P is formed $\genfrac{}{}{0ex}{}{\text{2}}{\text{i}}$ into the next quadruple.

и

. С помощью четырех элементов ИЛИ 12 второй группы формируется сдвиг кода с выходов элементов ИЛИ первой группы 10 в соответствии с уровнями сигналов

и

. При этом, если оба сигнала переноса

и

пассивны, то код с выходов элементов ИЛИ первой группы 10 поступит на входы элементов ИЛИ второй группы 12 без сдвига и будет выдан на выход узла частичного произведения. Если активен сигнал

, то будет произведен один сдвиг, если активны оба сигнала

и

(комбинация, когда активен только сигнал второго переноса не формируется), то осуществляется сдвиг на два разряда. Сдвиги осуществляются в кольцевом режиме и, при необходимости, на элементе ИЛИ 17 формируется сигнал переноса. При пассивном сигнале первого переноса на выходе элемента ИЛИ 16 открывается элемент И 20, а элемент И 21 закрыт. В этом случае при возникновении активного сигнала переноса на выходе элемента ИЛИ 17, на выходе элемента И 20 и выходе элемента ИЛИ 18 появится активный сигнал первого переноса в следующий разряд

. При активном сигнале первого переноса на выходе элемента ИЛИ 16 открывается элемент И 21, а элемент И 20 закрыт. Сигнал с выхода элемента ИЛИ 16, пройдя через элемент ИЛИ 18 сформирует сигнал первого переноса в следующий разряд

. При возникновении активного сигнала переноса на выходе элемента ИЛИ 17, на выходе элемента И 21 и выходе элемента ИЛИ 19 появится активный сигнал второго переноса в следующий разряд

. Наконец,, если в результате частичного произведения сформирован сигнал двух переносов, то активные сигналы поступают на входы элементов ИЛИ 18 и 19, формируя на выходе сигналы первого и второго переносов

и

, причем, как показано выше, на выходе элемента ИЛИ 17 не может возникнуть активного сигнала переноса при любых комбинациях сигналов переносов из предыдущего разряда

и

.The fifth group of AND 11 elements consists of twelve AND elements and forms a switchboard, which is controlled by NOT 13 and 14 elements, the inputs of which are connected to the inputs of the first and second transfers from the previous four-digit discharge

and

. Using four OR elements 12 of the second group, a code shift is generated from the outputs of the OR elements of the first group 10 in accordance with the signal levels

and

. Moreover, if both transfer signals

and

passive, the code from the outputs of the OR elements of the first group 10 will go to the inputs of the OR elements of the second group 12 without a shift and will be issued to the output of the partial product node. If a signal is active

then one shift will be made if both signals are active

and

(combination, when only the second transfer signal is active, is not formed), then a two-digit shift is performed. The shifts are carried out in a ring mode and, if necessary, a transfer signal is formed on the element OR 17. With a passive signal of the first transfer at the output of the OR element 16, the And element 20 opens, and the And 21 element is closed. In this case, when an active transfer signal occurs at the output of the OR element 17, at the output of the AND 20 element and the output of the OR element 18, the active signal of the first transfer to the next bit appears

. With the active signal of the first transfer at the output of the OR element 16, the And element 21 opens, and the And 20 element is closed. The signal from the output of the element OR 16, passing through the element OR 18 will form a signal of the first transfer to the next bit

. When an active transfer signal occurs at the output of the OR element 17, at the output of the AND element 21 and the output of the OR element 19, an active second transfer signal to the next bit appears

. Finally, if, as a result of a partial product, a signal of two transfers is formed, then the active signals are fed to the inputs of the OR elements 18 and 19, forming the signals of the first and second transfers at the output

and

moreover, as shown above, at the output of the OR element 17, an active transfer signal cannot occur for any combinations of carry signals from the previous discharge

and

.

The combiners in the code “1 of 4” 3 _i block adders 3 work in the same way, but implement the conversion according to table 3. Each group of elements And 22-25 contains 4 elements And, forming a 4 × 4 matrix. The binary components of the quadruple category of the term a _0i and _1i a _2i a _3i are fed to the first inputs of the elements And from the first to fourth groups, to the second inputs of the elements And with the first to fourth of each group are the binary components of the four-digit discharge of the factor b _0i b _1i b _2i b _3i . At 16 outputs of the matrix of AND elements, obviously, only one “1” can appear, the remaining zeros (any other combination, going through the logical elements of the adder 3 _i, will lead to the appearance of an error sign signal at one of the outputs of the control unit 5). The outputs of the elements AND groups 22-25 are connected to the inputs of the four elements OR of the first group 26 in such a way that the necessary result of the partial product is realized at their outputs in accordance with Table 3. At the same time, at the output of the OR element 30, a signal of a sign of transfer P _i to the next four-digit discharge is formed.

The fifth group of elements And 27 consists of eight And elements and forms a switch, which is controlled by the element NOT 29, the input of which is connected to the transfer input from the previous quaternary discharge P _i-1 . Using four OR elements 28 of the second group, a code shift is generated from the outputs of the OR elements of the first group 10 in accordance with the signal level P _i-1 . Moreover, if the transfer signal P _{i-1 is} passive, then the code from the outputs of the OR elements of the first group 26 will go to the inputs of the OR elements of the second group 28 without a shift and will be issued to the output of the adder. If the signal P _{i-1 is} active, then one shift will be made. The shift is carried out in a ring mode and, if necessary, a transfer signal is formed on the element OR 30.

Thus, the proposed device provides an increase in the reliability of the result of the multiplication of numbers due to bitwise control of the operation. This ensures the detection of 80% of errors.

Claims (1)

A device for multiplying numbers in the code “1 of 4”, containing a block of partial products, a block of adders and a control unit, the outputs of the control unit being connected to the outputs of the error indicator of the device, characterized in that a notebook shift register and a result register in the code “are entered into it” 1 out of 4 ”, and the inputs of the four-digit bits in the code“ 1 of 4 ”of the first device factor are connected to the information inputs of the corresponding notebooks of the notebook shift register, the outputs of the lower notebook of which are connected to the inputs of the first group of the block works, the inputs of the second group of which are connected to the inputs of the four-digit bits in the code “1 of 4” of the second device factor, the outputs of the partial works block are connected to the inputs of the first group of the adder block, the inputs of the second group of which are connected to the outputs of the group of senior four-digit bits of the result register in the code “1 of 4”, the outputs of the groups of the lower and upper four-digit bits of which are connected to the inputs of the control unit, the outputs of the adder block are connected to the information inputs of the four-digit bits of the reg the result stratum in the “1 of 4” code, the installation input of which is connected to the device recording input and the notebook shift register entry, the tetrad shift input of which is connected to the result register record input in the “1 of 4” code and the device shift clock input, constant input 0 in the “1 of 4” code which is connected to the inputs of the constant 0 of the partial product block and the adder block, while the partial product block contains n + 1 partial product nodes in the “1 of 4” code, where n is the number of four-digit bits of the factors, the inputs of the four-digit bits in the code “1 of 4” of the first and second factors from the first to the n-th nodes of partial products in the code “1 of 4” are connected to the inputs of the corresponding bits of the first and second groups of the block of partial products, the outputs of which are connected to the outputs with the first of the (n + 1) th nodes of partial products in the code “1 of 4”, the inputs of the four-digit bits in the code “1 of 4” of the first and second factors of the (n + 1) th node of the partial products in the code “1 of 4 ”Are connected to the input of the constant 0 of the block of partial works, the outputs are not the first and second transfers of the ith site of partial works in the code “1 of 4”, where i = 1,2, ..., n, are connected to the inputs of the first and second transfers of the (i + 1) -th site of partial works in code “1 of 4” of the block of partial products, and the adder block contains n + 1 adders in the code “1 of 4”, the inputs of the four-digit bits in the code “1 of 4” of the first term from the first to the (n + 1) -th adders in code “1 of 4” connected to the inputs of the corresponding bits of the first group of the adder block, the outputs of which are connected to the outputs from the first to (n + 1) -th adders in e “1 of 4”, the input of the four-digit discharge of the second term of the (n + 1) -th adder in the code “1 of 4” is connected to the input of the constant 0 of the adder block, the transfer output of the ith adder in the code “1 of 4”, where i = 1,2, ..., n, is connected to the transfer input of the (i + 1) -th adder in the code “1 of 4”, the inputs of the four-digit bits of the second term from the first to the n-th adders in the code “1 of 4 ”Are connected to the inputs of the corresponding bits of the second group of the adder block, while the result register in the code“ 1 of 4 ”contains 2n tetrads of four-digit bits, outputs and information inputs from the n-th to the 2-th t the tetrad of four-digit bits of the result register in the “1 out of 4” code are connected respectively to the outputs of the highest group of quaternary bits and, respectively, from the first to the (n + 1) -th information inputs of the four-digit bits of the result register in the code “1 of 4”, information inputs from the first in the n-1) th tetrad tetrad digits of the register of the result in the code “1 of 4” are connected to the outputs of the quadruple digits, respectively, with the second to the n-th tetrad of the four digits of the register of the result in the code “1 of 4”, while the control unit contains 2n control nodes code “1 of 4”, the inputs and outputs of which are connected respectively to the corresponding four-digit bits of the inputs and outputs of the control unit.

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