RU1781835C - Synchronization device - Google Patents

Abstract

The invention relates to telecommunications and can be used in clock synchronization systems for discrete information transmission systems. The purpose of the invention is to reduce synchronization time by using a variable module for averaging synchronization moves in accordance with the received signal implementation. The synchronization device comprises a significant moment highlighting unit defining a generator, a first element And, a divider by two, a second element And, a third counter. reversible counter, accumulating adder, first counter, first OR element, first subtracting counter, delay element, third AND element, fourth AND element, first trigger, second subtracting counter, a second OR gate, the second flip-flop, a divider and a monostable multivibrator. By using a variable module when averaging synchronization error codes over a measurement interval to calculate the mean, the time to enter synchronism is reduced. 3 ill.

Description

(L

WITH

The invention relates to telecommunications and can be used in clock synchronization systems for transmitting disk information.

The purpose of the invention is to reduce the time required to enter synchronism.

Figure 1 presents a structural diagram of a synchronization device; figure 2 - diagram of the accumulating adder; in Fig. 3 - temporary diagrams explaining the operation of the device,

The device comprises a significant moment highlighting unit 1, a generator 2, a first AND element 3, a two divider 4, a second AND element 5. a third counter 6. a reversible counter 7, accumulating an adder 8, a first counter 9, a first OR element 10, a first subtractor counter 11, delay element 12, third AND element 13, fourth AND element 14, first trigger 15,

the second counter 16, the second subtracting counter 17, the second element OR 18, the second trigger 19, the divider 20 and the standby multivibrator 21, and the accumulating adder 8 includes the first and second buffer registers 8.1 and 8.2 and the adder 8.3.

The synchronization device operates as follows.

The pulse information sequence (Fig. 3a) is fed to the input of the significant moments extraction unit 1, which extracts the significant moments of the information signal (Fig. 3b).

Suppose that the moment of the beginning of the reception of the information signal does not coincide with the significant moment of the pulse sequence, i.e. There is a synchronization error. To the input of the direct account of the reverse counter 7 through

vj co

00 CA)

5

the open first element of the IZ (trigger 15 in the initial position is in the O state), pulses begin to arrive from the output of the divider 20. At the moment the envelope of the input information signal passes through 0 (a significant moment of the sequence), a short pulse appears at the output of the block of significant moments 1 (Fig. 3,6), arriving at the control inputs of sequential recording. The second counter 16 And and the accumulating adder 8, at the information inputs of parallel recording which receives the temporary position codes from the outputs of the reverse counter 7 (Fig.3, c, d, e). In the first buffer register 8.1 of the accumulating adder 8, the corresponding code for the temporary position of this pulse is written, and in the second buffer register 8.2, the initial zero code is written. The temporary position code (in our example 110) is added in adder 8.3 with the code from the second buffer register 8.2 and the sum code (in this case 110 + 000 110) appears at the outputs of accumulating adder 8.

In the next measurement interval, there is no zero crossing in the information sequence (Fig. 3, a), therefore, the pulse does not appear at the output of block 1. The state of the accumulating adder remains the same (110).

At the third measurement interval, at the output of the block of significant moments selection, a short pulse again appears, under the influence of which the corresponding codes will be recorded in the accumulating adder 8 and counter 16. Since the phase detuning remains constant, the code of the temporary position of the significant moment will not change ( 110). In block 8, the new code 110 from the output of the adder 8.3 is overwritten into the second buffer register 8.2. In adder 8.3, the codes 110 + 110 1100 and the new code 1100 are added at the output of the accumulating adder 8.

In the fourth measurement interval under the action of the next pulse corresponding to the significant moment of the input sequence, codes 1100 + 110 10010 will be added in block 8,

The interval for averaging the synchronization error is selected based on the interference situation in the channel and the required search time (similar to choosing the capacity of the reverse counter in the analog). For definiteness, it will be considered that the averaging interval is equal to four measurement intervals, i.e. . At the end of each measurement interval, pulses appear at the output of the direct transfer of the reverse counter 7 (Fig. Ze), which are summed by the counter 9. After four pulses,

the output of counter 9 is an overflow pulse (Fig. 3, k). This pulse is the initial moment of operation of the synchronization device in the synchronization error correction mode.

0 Under the effect of an overflow pulse, the second trigger 19 is set to one. On the leading edge of a single signal from the output of the second trigger 19, the total code is overwritten (10010)

5 from the output of the accumulating adder 8 to the first subtracting counter 11, overwriting the state of the second counter 16 to the second subtracting counter 17 and the fourth element 2 AND 14 is opened.

0 to rewrite information from counter 16 to counter 17, a standby multivibrator 21 is used, generating a short control pulse from the leading edge of the positive pulse at the output of trigger 19,

5 which passes through the second element OR 18, the control input of the parallel recording of the second subtracting counter 17. Binary number - the number of significant moments in the averaging interval turns out to be recorded in both counters 16 and 17. Clock pulses from the output of the master oscillator 2 through the open element And 14 are received to the counting inputs of the first subtracting counter 11 and the second subtracting 5 counter 17. As a result of the interaction of these elements, the operation of dividing the binary number 10010 written in the counter 11 into binary numbers is performed lo 011 recorded in the counter 16.

0 The result of the division is recorded in the third counter 6. The division is as follows. As a result of synchronous subtraction from the counters 11 and 17, their state decreases. Since the dividend is written in counter 11 and the divisor in counter 17, the state of the latter is earlier than the state of counter 11 becomes zero. At this moment, a transfer pulse appears at the output of counter 17, under the influence of which

0, the state of counter 16 is written a second time to counter 17, and binary number 001 is written to counter 6. A second subtraction cycle begins. After the second transfer pulse at the output of the counter 17 to the counter 6

5, the binary number 010 is written, and the state of the counter 16 is again rewritten to the counter 17, etc. The division process will continue until the counter 11 is completely zeroed, after which a transfer pulse will appear at its overflow output, which

trigger 19 returns to its initial state. In the counter 6, the number of averaged synchronization error codes (in this case 110) is recorded. After the completion of the division process, an overflow pulse appears at the output of the delay element 12, under the influence of which the averaged synchronization error code is written to the reverse counter 7. If the output of the reverse counter 7 contains a code other than zero, then a phase error of $ 0 occurs. If .0 , then element 2 AND 13 remains closed, because at all inputs of the first element OR 10 there are logical zeros. If A l 0 the overflow pulse through the open element 2 AND 13 is supplied to the input of the installation in 1 trigger 15 and sets it to a single state. Element And 3 closes, and the second And 5 opens. The pulses from the output of the divider 20 begin to arrive at the input of the counting down of the reverse counter 7 through the open second element And 5. The synchronization error correction mode starts with a value of 6 parts of an elementary parcel. After six pulses have passed to the input of the countdown of the reverse account 7, a pulse appears at the output of zeroing the last. Under the influence of this pulse, trigger 15 and counter 16 are set to their initial zero state, and all information recorded in accumulating adder 8 and counter 6 is erased. The counter 9 after the formation of the pulse will be in the initial state, because It works in cycles. The correction mode is over. A new cycle of measuring the synchronization error begins.

Thus, in the proposed device, the accuracy of the phase correction of the received oscillation under the reference does not depend on the information parameter of the signal. Indeed, in the measurement interval, there was no one significant moment in the input signal. In the prototype, this leads to an increase in the search time of the synchronism mode, and in the proposed device, the search time remains constant and minimal, because the signal phase value is averaged taking into account the number of received significant moments of the input signal.

Claims (1)

The claims A synchronization device comprising a master oscillator in series 5 10 15 20 25 30 35 40 5 0 5 connected reverse counter, OR element, first AND element and trigger, the direct and inverse outputs of which are connected respectively through the second and third AND elements to the inputs of the reverse and direct counts of the reverse counter, the outputs of which are connected to the corresponding inputs of the accumulating adder, to the information input of which the output of the block of highlighting significant moments is connected, the zero input of the accumulating adder is connected to the other input of the trigger and to the output of the reverse transfer of the reverse counter, the output of the highest p whose row is connected to the input of the divider by two, and the direct transfer output of the reversible counter is connected to the input of the first counter, the other inputs of the second and third elements And are interconnected, and the input of the preliminary recording of the reversible counter is connected to the second input of the first element And, characterized in that, in order to reduce the time of entering synchronism, the first and second subtracting counters, the second and third counters, an additional trigger, an OR element, and an I. element are waiting for it. waiting multivibrator, delay element and de frequency suppressor, while the output of the master oscillator through the frequency divider is connected to the corresponding inputs of the second and third elements AND, the outputs of the accumulating adder are connected to the corresponding inputs of the first subtracting counter, the output of the reverse transfer of which is connected to the installation input zero of an additional trigger, the installation input of which is connected to the output of the first counter and through the delay element - with the input of the preliminary recording of the reversible counter and with the second input of the first element And, zero inputs The second and third counters are interconnected and with the reverse transfer output of the reverse counter, the output of the master oscillator is connected to the first input of the additional element And, the output of which is connected to the counting inputs of the first and second subtracting counters, the output of the additional trigger is connected to the counting input of the first subtracting counter, with the second input of the additional element AND and with the input of the waiting multivibrator, the output of which through the additional element OR is connected to the counting input of the second subtracting about the counter, the output of which is connected to the other input of the additional OR element and to the counting input of the third counter, the output of the significant moment highlighting unit is connected to the counting input of the second counter, the outputs of which are connected to the corresponding inputs of the second counter and connected to the corresponding subtracting counter, and the outputs of the third inputs are reversible counter. FIG. / - P and g 4sh. "- C --- D as ag t i  ( , j Y / g / do lf-1 JlJgglXlJlJlJlJllJlJ lJglJlJl. e P P P P . Seri M 48inl & No. Ј 1 P R LDI Reg.Z