SU660290A1 - Arrangement for synchronizing pulse trains - Google Patents

Description

Additional elements AND, the first additional element OR and the input of the first additional trigger are the input signal, and the third input of the second additional element OR, a second additional trigger input, to another input of the shift register to another input of the first additional trigger, to the input of the first delay element, and through the second delay element to the other inputs of the additional block And rewriting elements - a synphasing signal.

Figure 1 shows the structural electrical circuit of the device; figure 2 - timing diagrams.

The device contains a shift register 1, block 2 elements AND rewriting, counter 3, element OR 4, first element AND 5, trigger 6, second element AND 7, additional counter 8, additional block 9 elements And rewriting, three additional elements And 10, 11 and 12, two additional triggers 13 and 14, two additional elements OR 15 and 16 and two delay elements 17 and 18.

The device works as follows.

In the initial state, counters 3. and 8, shift register 1, and triggers 6, 13, and 14 are reset. The input signal (see Fig. 2 a) is fed to the input of element 11 and 11, to the inputs of block 2 of elements AND rewriting, to the input of element 12, to the input of trigger 6 and to the input of element OR 15. If there is zero information in shift register 1 the counter 3 is recorded as zero information, and the output of the element OR 4 is a low voltage level. At this, the AND 11 element is closed for the input signal, which through the open AND 12 element and further through the OR 16 element passes to the output of the device (see Fig. 2k) and puts the trigger 13 into the state (see Fig. 2e). In this case, the element And 10 is unlocked, and the pulses of the reference frequency F are fed to the input of the counter 8, the signals of the reference frequency are shown in Fig. 26, and the signals at the input of the counter 8 are sent to Fil7.2c. Counter 8 operates in the add mode and sums the pulses fed to its input. The information in the counter 8 is shown in FIG. 2 g. If, during the pulse counting of the reference frequency, a synphasing pulse (see FIG. 2 e) did not arrive in the time interval between the input pulses, the next input signal passing through the OR 15 element to the installation input the zero of the counter 8, brings it to the zero state and then the counting cycle repeats.

If during the subsequent counting cycles in the interval between the filing

input pulse will be fed to the in-phase pulse (see Fig. 2d), then it passes through the OR 16 element to the output of the device (see Fig. 2k) and sets trigger 14 to the state, and shift register 1 is preset to zero (or confirms it is in the zero state), then in the shift register 1 through the time determined by the delay element 18, through block 9 the current information value is recorded in the counter 8 (at the moment of the synphating pulse) and then the counter 8 is zeroed after the time determined by the element Delays 17. Register information with 1 is shown in Whig 2g. With the input signal following the synphasing pulse (which no longer passes the device output, since element 12 is locked), information from shift register 1 through block 2 is transferred to counter 3. A high level of voltage is reproduced at the output of element 4 , the element AND D-d is opened for the input signal acting on its input, which passes to the input of trigger 6, translation

(see fig.2e). it

one

in state

leads to unlocking the element 7 for pulses of the reference frequency, which pass to the counting input of the counter 3 and to the control input of the element 5. The signals at the input of the counter 3 are shown in fig. Counter 3 operates in the subtraction mode of operation, and when applying signals to its counting input, the original information recorded in it starts to be sequentially read. The information in counter 3 is shown in Figure 2i.

When in the process of recalculation, the zero value of the information in the counter 3 is reached, element 5 is unlocked for signals from the output of element 7 and the low level of voltage is reproduced at the output of element OR 4. In this case, the element 11 is locked for input signals, and at the output of element 5, a signal is reproduced that places the trigger 6 in the zero state and through the element OR 16 passes to the output of the device, determining the output result (see figure 2k). The process then repeats.

Claims (1)

With the arrival of each input pulse, the trigger 13 is converted to H and the reference frequency pulses begin to arrive at the input of the counter 8, which are counted by the counter 8 until either the synthesizing pulse or the next input signal arrives. In the case of the arrival of the next synphating pulse, the information accumulated in counter 8: and characterizing the shift time, is transmitted to shift register 1 and then to counter 3, where it is recalculated. In the case of the input signal, no information accumulated in the counter 8 is transferred to the shift register 1 (the previously recorded information remains in the register 1), the counter 8 is reset, and the conversion cycle is performed again. In the counter 3, with the arrival of the input signal, information is recorded from register 1, which was previously stored in it. Realization of a particular case of coincidence of the input and synphating signals is not shown in the diagram. This case is implemented by well-known techniques, for example, based on two AND elements and a trigger, whose input is associated with the output of one AND element, which detects the coincidence of the input and synphating signals, and the output with the first input of another AND element, the second input of which is connected to the output intended for supplying the input signal and the output to the input of the element OR 4 devices. The number of pulses n of the reference frequency recorded in the counter 8 for the time interval between the input and synphating pulse supply times is determined by the formula where dT is the time interval between the input signal input and the synphating pulse supply moment. The code characterizing this number of pulses is transmitted to counter 3, where it is used as the initial setpoint. Since counter 3 operates in the subtraction mode and pulses of the reference frequency are sent to its input, i.e. the same signals that are fed from the input of counter 8 , the read time of the information recorded in the counter 3 will be determined by the following expression: -Lai. - LF g, - U1, i.e., is equal to the time interval between the moment of input signal supply and the moment of applying the in-phase pulse, which is required in this case. Thus, at the output of the device, we have a sequence of pulses in phase with an external synphating pulse, which can arrive at an arbitrary time. Thus, the proposed device provides a significant increase in speed compared with the known device. This is due to the fact that in the proposed device the output in-phase sequence is developed without delay, at the moment of applying the in-phase pulse, since the same pulse passes to the output of the device. Claims An apparatus for synchronizing pulse sequences, comprising a serially connected shift register, a block of recording elements AND a rewrite and a counter, which are connected respectively to the inputs of the OR element and the inputs of the first element. And, the output of which through a trigger is connected to the input of the second element And, the output of which is connected to other inputs of the counter and the first element AND, characterized in that, in order to improve speed, the consecutively connected additional counter and an additional block of elements And rewriting are entered Additional elements And, two additional triggers, two additional elements OR, and two delay elements, with the outputs of the additional block of AND elements of rewriting connected to the inputs of the shift register, and the output of the first about the delay element through the first additional element OR connected to the input of the additional counter, the other input of which is connected through the first additional element AND to the output of the first additional trigger, and the output of the element OR through the second additional element AND connected to the other input of the trigger, while the output of the element AND is connected to the first input of the second additional element OR, the second input of which through the third additional element AND is connected to the output of the second additional trigger, while at the other inputs The second element And the first additional element And the reference signal is fed, to the other inputs of the AND rewriting element block, the second and third additional AND elements, the first additional OR element and the input of the first additional trigger are the input signal, and the third input of the second additional element OR, to the input of the second additional trigger, to another input of the shift register, to another input of the first additional trigger, to the input of the first delay element, and through the second delay element to the other inputs The block of elements And rewriting of the in-phase signal. Sources of information taken into account in the examination 1. US patent 3,723,714, cl. 235-152, 1973.