NZ217553A - Gain switching signal via one of multiple paths - Google Patents

Description

217553 Prior::-/ n-T' Coir -: •>, c: Under the providers cf R"s£&< Sation 23 (1) the ...... - - _.t C.OWipkTZ Specification has been ante-dated; 23...19.H3-, ■ c:t:on Fi.'3d: ^."53-85 ;3' r aug -»a? Publication Date: P.0. Journal, No: .. initials Patents Form No. 5 NEW ZEALAND PATENTS ACT 195 3 !!n H E ?i /- COMPLETE SPECIFICATION 1 < CCD loo/^ • ^ 11 SEP 1986 r GAIN SWITCHING DEVICE FOR WATT METER t V Ix'We, SANGAMO WESTON, INC. of 180 Technology Drive, Norcross, — * Georgia, U.S.A., a company incorporated under the laws of the state of Delaware, U.S.A. hereby declare the invention, for which ^we pray that a patent may be granted toats^us, and the method by which it is to be performed, to be particularly described in and by the following statement: [(followed by page 1A.) -1A- 2 17553 GAIN SWITCHING DEVICE FOR WATT METER This application is a division of N.Z. Patent Application No. 205715 filed on 23 September 1983.

Technical Field This invention relates to watt hour apparatus for switching a signal to pass through p^ths having different gain characteristics,and more particularly to such apparatus including therein structure for reducing errors caused by interaction of common frequency components present in the signal and in a switching function used to determine the path for the signal.

Background Art Electronic instruments for measurement of electrical energy are known in the art. In such instruments, it is known to use electronic components for measurement of analog electrical parameters, such as current and.voltage, and for conversion of the analog quantities to digital signals. The use of digital circuitry enables the resultant digital signals to be multiplied with great accuracy, thereby to provide accurate representations of the electrical energy transfer rate in a circuit.

The conversion of analog signals to digital values is typically achieved by analog-to-digital converters. Such converters are capable of providing accurate digital signals representative of the analog input value, for adjustable ranges of peak or average values of the input parameters. Accordingly, prior art circuits require manual intervention to change the range of measurement in accordance with the parameter values. Alternatively, FILE 44.364 DIV. 1 i~ • •• ~i r n~ i" —r "• -r T~iitiffmrtwriiTriTnwiirtTnirirri]OTfiiiai 217553 auto-ranging electrical systems are known wherein different ranges of measurement are automatically determined by internal circuitry, the specific range being shown to the user by a visual display, for example. Such auto-ranging systems are typically responsive to peak or 'average values of alternating electrical parameters. These devices, hcwever, do not address the question of providing accurate instantaneous conversion of the low magnitudes of a high range alternating electrical quantity, such as typically found in the vicinity of the zero crossings thereof.

Moreover, in prior art systems utilizing ■ electronic signals it is known that various offset voltages of electronic components tend to result in inaccuracies. In the prior art there are provided suggestions for overcoming such offset errors. In one approach, described in U.S. Patent 4,058,768, for example, errors caused by offset are averaged out utilizing a complicated system. Therein is proposed the phase switching of voltage variable signals and of a polarity detector whenever an output pulse is generated, thereby to average out offset caused errors. An integrator is caused 'alternately to integrate upwardly or downwardly, at a repetitious cycle having a frequency substantially higher than the frequency of the electrical parameter being measured. The patent, however, fails to address the issue of inaccurate instantaneous conversions in the zero crossing area. Moreover, the correction of errors due to interaction between common frequency components of a switching function and of a signal being measured is similarly not addressed, whether such errors are due to offset voltages or to other causes. 217553 Kiere is thus a need to provide structures for correcting internal errors in an electronic measurement apparatus due to interactions between the signal being measured and a switching function used in measurement of the signal. Moreover, there is a need to provide 5 correction for inaccurate instantaneous conversions of analog values for signals having wide instantaneous variations although remaining in a particular measurement range.

It is another object of the invention to provide a gain switching arrangement for a varying input signal as a function of the 10 instantaneous value of that signal and for causing the signal to be conveyed through alternate paths having different gains therefor. Summary of the Invention In accordance with one aspect of the invention there is provided a gain switching apparatus for providing a plurality of gains 15 to a varying input signal including a plurality of paths for conveying said input signal through a plurality of gain producing circuits and for providing a plurality of gains thereto, output means, switching means for selectively switching said input signal through a selected one of said plurality of paths to said output means responsively to a 20 switching signal, and control means for generating said switching signal and for controlling said switching means, said control means including ccxiparing means for comparing an instantaneous value of said input signal with a threshold value and signal providing means responsive to said caiparing means for providing said switching signal 25 and for causing said selected one of said plurality of paths to be selected by said switching means for conveying said input signal to said output means. 2 17553 ~4~ In accordance with another aspect of the invention there is provided a gain switching method for providing a plurality of gains to a varying input signal including the steps of receiving a first signal and providing said first signal as an input signal to a plurality of paths, conveying said input signal through gain producing circuits of said plurality of paths to provide a plurality of gains to said irput signal, generating a switching signal by comparing an instantaneous value of said input signal with a threshold value and providing said switching signal in response to the comparison, and selecting a selected one of said paths for conveying said input signal to an output means by application of said switching signal to a switching means. <4 % ,A ' i o 217553 Still other objects and features of the present invention will become more readily apparent to those skilled in the art from the following description when read in conjunction with the accompanying drawing, 5 wherein there is shown and described a preferred embodiment of the invention sitr.ply by way of illustration of one of the best modes contemplated for carrying ,/T) out the invention.. As-will be realized, the invention is capable of other, different, embodiments and its 10 . several details are capable of modifications in various obvious aspects, all without departing from the invention. Accordingly, the drawings and descriptions will be regarded as illustrative in nature and not as restrictive.

Brief Description of the Drawing The accompanying drawings, incorporated in and forming a part of the specification, illustrate several aspects of the present inventioft, and, together 20 with the description, serve to explain the principles of the invention. In the drawings: Figure 1 illustrates a prior art switching apparatus useful in measurement of electrical power; Figure 2 illustrates an improvement of the 25 prior art apparatus of Figure 1 in accordance with the present invention; Figure 3 shows ' a block diagram of the inventive improvement shown in Figure 2; Figure 4. provides a block diagram representation 30 of a portion of the structure in Figure 3; and Figure 5 shows a detailed logic diagram of the structure of Figure 3. w1 '/ ■' 2 1 755 3 Best Mode for Carrying Out the Invention Typical prior art measurement of electrical power is illustrated by the structure in Figure 1. As shown therein, electrical voltage and current signals are input at leads 10 and 12, respectively. The voltage and current are represented by analog values which, after conversion to digital form in an analog-to-digital converter (ADC) 14 are multiplied in a multiplier 16. The resultant product is provided to a utilization device 18 which typically includes a display.

The arrangement of Figure 1 shows the ^ use of a single ADC to convert both the voltage and current signals. Such an approach ^5 is enabled by use of a controllediswitch 20, effectively multiplexing the voltage and current signals for input to the ADC. Not shown in the circuit is a pair of storage devices which may be necessary for storing the digital output of ADC 14 to provide a simultaneous 2o multiplier and multiplicand to multiplier 16. Of course, if two ADC units are used, the controlled switch 20 is not required and the voltage and current signals are provided directly to the converters.

In order to assure that the voltage and current ; 25 signals are accurate representations of contemporaneous ___ electrical parameters, there is provided a pair of synchronized sample-and-hold units 22 and 24. Moreover, although the circuitry in Figure 1 illustrates a single pair of input terminals for voltage and current, the structure is equally applicable to multi-phase systems by utilization of a multiplexer (not shown) for periodically sampling the voltage and current of each of the phases, and providing signals representative of the same on leads 10 and 12. 217553 A problem with the prior art structure shown in Figure 1 is that the analog-to-digital converter 14 has a limited input operating range within which accurate conversion may be obtained. Thus, independently 5 of the range of input parameters to which the device is set, it will be appreciated that for alternating current signals there will be a.portion of the signal cycle n for which the input signals have low instantaneous magnitudes. Thus, power determination in the vicinity 10 _ of the zero crossings of the current or voltage waveforms will not be as accurate as those obtained during the higher magnitude instantaneous values of the input r: waveforms.

In order to overcome this deficiency in the prior 15 art, there is thus provided a modification of the structure in Figure 1 as shown in Figure 2. More specifically, as seen in Figure 2 there is provided a gain switching network 26 in the path of the input current lead 12.

It is the function of the gain switching network 26 to 20 provide an increased amplitude of the current for conversion in ADC 14 when the instantaneous current magnitudes are low. Thus, ADC 14. provides a more accurate digital representation of the current during those instants of time when its 25 magnitude is low, in order to provide a more accurate ^ product by multiplier 16. Of course, in order to. retain the appropriate scale for the product, multiplier 16 is required to undo the effects of the amplification of the instantaneous current magnitude by gain switching 30 network 26. Towards that end, a control signal is provided by gain switching network 26 on a lead 28. ^ The signal indicates to multiplier 16 the specific gain provided by network 26 to the current signal on lead 12.

■Jr 217553 A Por simplicity in operation, where multiplier 16 may represent a function performed by a microprocessor, or by another binary coded device, gain switching network 26 may 5 provide different gains representable by different powers of 2. Multiplier 16 may then simply compensate for different ^ gains provided to the current by shifting the binary point / of its output product.

The system of Figure 2 illustrates a single gain 10 switching network 26 in the current lead. It should be appreciated, however, that a similar network may be provided in the voltage lead 10. However, inasmuch as typical power measurements are made with a fixed voltage (e.g., 115 volts at 60 Hz) and with varying current, the voltage conversions 15 will be of sufficient accuracy. Inasmuch as the current value may change/ however, and its instantaneous value is thus not predictable, the preferred embodiment of the invention contemplates compensation of the reduced accuracy of an ADC only for the current values.

Referring now to Figure 3, the gain switching network 26 is shown in greater detail in order further to explain the operation of the invention. As shown in the figure, there is provided for the input signal on lead 12 a first path 30, having a first gain therein, symbolically 25 represented by an amplifier 32, and a second path 34, having a second gain represented by an amplifier 36. It should be appreciated that the illustration of two alternate paths for the input signal is illustrative only. That is, there may be provided a larger number of alternate paths for' the 2 1 75 5 3 input signal. The specific gain given to the input signal prior to its passage to ADC 14 is determined by the instantaneous value thereof. Thus, where ADC 14 (or other utilization apparatus receiving the 5 output of gain switching network 26) includes a number of operating ranges, each requiring a separate signal amplitude for proper operation, it is clear - that a number of such paths, with an appropriate number of gain factors provided therein, may be used in 10 the invention.

The signals passed by the first and second paths are provided to a controlled switch 38, which provides an output on its output lead 39 to the sample-and-hold circuit 24 shown in Figure 2. A control 15 circuit 40 is provided for controlling switch 38 in order to pass the input signal after amplification in path 1 or path 2 to the ADC.

In accordance with the preferred embodiment, the control circuit 40 includes a signal providing 20 circuit 42, for providing a switching function control signal for switch 38. Additionally, control circuit 40 includes a comparator 44. The comparator is used to compare the input signal (either directly or, as shown in Figure 3, after amplification in. one of the 25 paths) with a threshold to determine which gain should be provided to the signal prior to its passage through control switch 38 to the utilization device represented by ADC 14. Upon determination of the appropriate gain, comparator 44 causes circuit 42 to provide a control 30 signal for switch 3B- in order to switch the appropriate path into the circuit. a 755 3 Preferably, the circuit 42 for providing a signal to the controlled switch 38 and to the multiplier 16 includes a latch 4 6 for temporarily storing the results of the comparison conducted at comparator 44. The output of latch 4 6 may be used directly to provide the desired output switching function and the output control signal to multiplier 16. However, such a connection may lead to an error for the following reason.

Ideally, for a situation wherein ADC 14 is set to accept 60 Hz signals of a particular (high) signal range, the instantaneous signal magnitude is at low levels requiring further amplification (in the vicinity of a zero crossing) at a 120 Hz rate. Thus, the output of latch 46 should include only a 120 Hz component, and should not include a 60 Hz component. However, because of possible; asymmetries in the input waveform, in the offset voltages in the positive and negative comparisons conducted at comparator 44, or because of differences in offset voltages in paths 30 and 34, a 60 Hz component may be included in the switching signal output by latch 46. This component thus affects the switching of switch 38 and provides a -60 Hz error component on output lead 39.

Since this signal is ultimately multiplied in multiplier 16 by a voltage signal having the same frequency,, the result of the multiplication may include an appreciable DC error.

It is known that a multiplication of signals of two frequencies results in signals having sum and difference frequency components. Where the two multiplied signals include a common frequency component, the difference frequency component is thus at zero, or DC frequency. Accordingly, the present invention includes an error reducing circuit 48 within the circuit 42 providing the output switching function. It is the "7/:: • ■■ ■: r-*f. y< m 217553 _11_ function of error reducing circuit 48 to provide a substitute switching function for the function output by latch 46, wherein the substitute function is substantially devoid of components at the common input frequency, •5 thus reducing or eliminating the DC error hereinabove described. Thus, rather than providing the switching function generated in latch 46 to switch 38 and to multiplier 16, the inventive circuit substitutes a switching function at a substitute frequency, so 10 that the interaction with the -60 Hz input frequency will not result in the undesirable DC component. - Referring now to Figure 4, the error reducing '"7 circuit 48 is shown to include a delay circuit 50 and a logic gate 52 for providing the substitute switching 15 function. The output of latch 46 is input to the delay circuit 50, and combined with the output of delay circuit 50 in logic gate 52 to provide the substitute switching function.

In operation, delay circuit 50 is selected 20 to provide a delay of 1/2 period of the offending common frequency. Thus, where it is desired to eliminate a 60 Hertz component, an 8.33 millisecond delay is provided. By combining the output of latch 46 with its output 1/2 cycle previous thereto, there 25 results at the output of logic gate 52 a signal of a frequency double the ur.desired frequency. That is, w logic gate 52 outputs a switching function at twice the frequency of the function output by latch 46, and any errors ther.ein are similarly provided at double 30 'frequencies. Thus, a 60 Hz error component in the switching function, due to the various offset voltages for example, is replaced by a 120 Hz .waveform in the substitute switching function generated by logic m 217553 ,-~-S Vj gate 52. Subsequent correlation between the signal passed by switch 38 and the 60 Hz input voltage signal might thus result in an easily ignored 60 Hz error component, but without the objectionable DC error. it should be understood that instead of being delayed by 1/2 the period of the frequency common to the input signal and the switching function, the output function of the latch may be delayed by an appropriate plurality of any submultiple of the period of the common 10 frequency. For example, to provide a tripling of the output error frequency the error reducing circuit may be altered to provide logic gate 52 with three inputs originating at the latch output. A first input would be passed through a delay circuit of 1/3 the common 15 period, a second input would be provided a delay of 2/3 of the common period, and the third input would be the direct output of the latch itself. As will be appreciated, this approach results in tripling of the frequencies in the output of the latch circuit-20 Referring now to Figure 5, there is shown a logic diagram illustrating in detail the preferred embodiment of the present invention. Preferably, the gain of path 34 is unity and the gain of path 30 is represented by a circuit arrangement 54 wherein 25 the gain of operational amplifier 32 is adjusted by . resistors Rl and R2 to equal a power of 2, such as 8, in accordance with the previous description. The output of operational amplifier 32 is provided to a pair of comparators 56 and 58 which form the structure 30 shown as comparator 44 in Figure 3.

Comparators 56 and 58 provide output signals indicative of whether the output of amplifier 32 is within or without a range between +Vj_ and -V£. Typically, 2 1755 3 vl*v2' so that f°r values of the input signal in a symmetric low range the signal is amplified by amplifier 32 prior to passage through switch 38 to the ADC.

Operation of the circuit thus provides for control of switch 38 to pass the input signal to the sample-and-hold circuitry 24 when its instantaneous amplitude is sufficiently high. When the amplitude is low, however, and is within a predetermined range, the signal passed to sample-and-hold circuit 24 is the amplified version of the input signal, as provided by operational amplifier 32. The determination of whether the input signal is within or without the predetermined range is made by comparators 56 and 58, each of which provides a high level output signal when the input signal is within the low range. The resultant low level overrange signals output by the open collector output circuits of the comparators are wire OR'ed to provide a high level input signal to a D-type flip-flop 60 only when the input signal is within the low range requiring increased gain. The output of flip-flop 60 is provided to the data input of a shift register 62, performing the function of delay circuit 50 in Figure 4. The shift register output and the flip-flop output are both input to a NAND circuit 64 wtiich provides a high level control signal for the switching circuit whenever either ■ input thereto is low.

Thus, the controlled switch 38, which may be a type DG 303, .manufactured by Siliconix, for example, provides a closed switch for path 34 if the input signal is now, or was 1/2 period previously, beyond the low level range. Alternatively, the signal on path 30 is passed to the ADC if the input signal is now, 217553 and was 1/2 period previously, within the low level range requiring additional amplification.

Preferably, the flip-flop 60, the shift register 62, and the sample-and-hold units 22 and 24 are clocked by a common signal provided on lead 66. The shift register is selected to have an appropriate number of stages to store a sequence of outputs of the flip-flop covering half the common period at the clock rate of the signal on lead 66.

Where a microprocessor is used to perforin the multiplication function, as well as to control sequencing t of operatioas in the circuit, the substitute switching function output by control circuit 40 on lead 28 may be applied to an interrupt line thereof. Thus, since a low value on line 28 is indicative of provision of a signal to the ADC which represents an amplified version of the input signal, the presence of a low level on line 28 may be used to trigger the microprocessor (not shown) to correct for the gain of amplifier 32.

Where the gain of amplifier 32 is eight, the microprocessor will provide a product after a leftward shift of the binary point by three binary places.

Although the invention has been described in terms of a watt-hour environment, it should be.appreciated that the described structure as recited in the claims is applicable in other environments as well. Thus, in addition to providing a reduced gain switching function for a watt-hour meter, the present invention more broadly provides an error reducing apparatus for environments wherein a switching function is generated as a function of a particular input signal, and results in a component having a common frequency with the 217553 input signal. By changing the frequency of "the switching function components, errors due to correlation of the frequency component with similar components of the input signal are thus reduced.

The foregoing description of the preferred embodiment of the invention has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise form disclosed, since many obvious modifications and variations are possible in light of the above teaching.. The embodiment was chosen and described in order best to explain the principles of the invention and ifcs practical application, thereby to enable others skilled in the art best to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, when interpreted in accordance with the full breadth to which they are fairly and legally entitled.

Claims (12)

vK^V5'"*1 -16- 217553 What we claim is;

1- A gain switching apparatus for providing a plurality of gains to a varying input signal comprising: a) a plurality of paths for conveying said input signal through a plurality of gain producing circuits and for providing a plurality of gains thereto, b) output means having an output signal, c) switching means for selectively switching said input signal through a selected one of said plurality of paths to said output means responsively to a switching signal, and d) control means for generating said switching signal and for controlling said switching means, said control means including i) comparing means for comparing an instantaneous value of said input signal with a threshold value and ii) signal providing means responsive to said comparing means for providing said switching signal and for causing said selected one of said plurality of paths to be selected by said switching means for conveying said input signal to said output means, e) error reducing means for reducing output errors due to interaction between components of a common frequency in said output signal and said switching signal.

2. The apparatus according to claim 1, wherein a first one of said paths comprises operational amplifying means for providing a first gain to said input signal, said comparing means being connected to the output of said operational amplifying means for comparing an amplified value of said input signal with said threshold value.

3. The apparatus according to claim 1 or 2, wherein said control means further comprises latching means for retaining the result of said comparison for a selected period of time and for providing an output representative thereof, and connecting means for controlling said switching means responsively to said latching means output, and whereby said reducing means reduces output errors due to interaction -17- 2.1 7 553 between components of a common frequency in said input signal and in said output of said latching means.

4. The apparatus according to claim 3, wherein said error reducing means comprises delay means for delaying said latching means output by a submultiple of the period of said common frequency and combining means for combining said latching means output with the delayed latching means output to provide a control signal component for said switching signal at a multiple of said common frequency.

5. The apparatus according to claim 4, wherein said delay means comprises shift register means connected to said latching means and providing an output, and said combining means comprises logic gate means connected to receive the output of said shift register means and the output of said latching means for providing said control signal component.

6. The apparatus according to claim 5, wherein said shift register means is provided with a predetermined number of stages and with a predetermined clock frequency to store the output of said latching means for one half the period of said common frequency, whereby said gate means provides said control signal component at double the common frequency.

7. The apparatus according to claim 5, wherein said output means comprises analog-to-digital converting means having output signals, sample-and-hold means for selectively providing samples of said input signal from said switching means or samples of a second input signal to said analog-to-digital converting means, and multiplying means for multiplying the output signals of said analog-to-digital converting means.

^ 8. The apparatus according to claim 7, wherein said combining means provides to said multiplying means the control signal for determining scale factor for products produced by said multiplying means corresponding to the gain provided to said input signal by said selected one of said plurality of paths.

9. The apparatus according to any one of the previous claims, comprising first input means for receiving a signal and providing said first signal as the input 1') !■. said plurality of paths, second input means for receiving a second signal and providing said second signal as the second input signal to said sample-and-hold means, one of said first and second input means receiving a current input signal and the other receiving a voltage input signal, said multiplying means providing a product representative of electrical power associated with said voltage and current inputs.

10. A gain switching method for providing a plurality of gains to a varying input signal comprising; receiving a first signal and providing said first signal as an input signal to a plurality of paths; conveying said input signal through gain producing circuits of said plurality of paths to provide a plurality of gains to said input signal; generating a first switching signal by comparing an instantaneous value of said input signal with a threshold value and providing said switching signal in response to the comparison; generating a substitute switching signal from said first switching signal having a frequency different from said first switching signal; and selecting a selected one of said paths for conveying said input signal to an output means by application of said substitute switching signal to a switching means.

11. The method according to claim 10, comprising amplifying said input signal by a first one of paths to provide a first gain to said input signal for an amplified value of said input signal and wherein the comparing step comprises comparing the amplified value of said input signal with said threshold value.

12. The method according to claim 10 or 11, wherein the step of generating a substitute switching signal comprises latching and delaying the result of the comparing step for a selected period of time and providing an output represen thereof for controlling said substitute switching sign '"V 8 MAY 1987 19 217553 13 A gain switching apparatus for providing a plurality of gains for a varying input signal and controlling the path of said input signal as the result of a comparison of the instantaneous value of said input signal to a threshold value, substantially as herein described with reference to any one of Figures 2, 3, 4 and 5 of the accompanying drawings. 14. A gain switching method for providing a plurality of gains for a varying input signal and controlling the path of said input signal as the result of a comparison of the instantaneous value of said input signal to a threshold value, substantially as herein described with reference to any one of Figures 2, 3, 4 and 5 of the accompanying drawings. BALDWIN, SON & CAREY I 18 HAY1987z V. JJ J