KR960008563Y1 - Parallel bus control system - Google Patents

Abstract

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Description

Parallel bus controller

1 is a block diagram of a conventional parallel bus controller.

Figure 2 is a block diagram of the control device of the parallel bus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: processor 20: first buffer

30: second buffer 40: memory

50: bus control unit 60: third buffer

The present invention relates to an electronic exchange system, and more particularly, to a control device of a parallel bus to ensure high-speed data communication by appropriately varying the communication speed according to data amount of data communication between several nodes.

Conventionally, as can be seen in FIG. 1, the mixer 1 for mixing the address buffer applied from the CPU 5 according to the counter clock, and the memory unit 2 for storing data in parallel for transmission and reception. ), A memory control unit 3 for controlling the memory unit 2 via the memory control bus, a data bus buffer 7 and a parallel bus buffer for connecting external modules according to the applied parallel bus number and counter clock ( 6) the CPU 5 controlling the entire system via the address bus in accordance with the PAL 4 controlling the interrupt signal and data applied; and the CPU 5 and the data bus in accordance with the control signal of the PAL 4; And a data bus buffer 7 for transmitting and receiving data through the data, and a buffer 8 for notifying the CPU 5 of the parallel bus number applied from an external module.

In the conventional parallel bus controller configured as described above, in order to access the data stored in the memory unit 2 and share the counter with the CPU 5, the mixer 1 has a data signal for the address bus applied from the CPU 5 ( AB) is mixed according to the applied counter clock (CNT CK). At this time, the CPU 5 reads the number of the parallel bus applied through the buffer 8 from the external bus module and determines the timing of transmission and reception according to the parallel bus number PBN. After that, the PAL 4 controls the gate of the parallel bus buffer 6 according to the control signal applied from the CPU 5 through the interface to transmit data applied from the memory unit 2 to the external module. The received signal applied from the memory unit 2 is stored in the memory unit 2. In this case, data transmission and reception of the memory unit 2 is performed according to the control signal of the memory control unit 3. As the time setting for the occupancy of the parallel bus, a unique number is assigned to the transmission / reception module so that only the corresponding data is transmitted and received, the transmission time is extended, and only 16 bytes are transmitted from one module.

As described above, since only 16 bytes are transmitted in one module, data must be divided and transmitted when transmitting more than 16 bytes. Therefore, reliability of transmission is reduced, and performance of transmission is degraded due to fixed transmission timing setting. And, there is a problem that all the messages are received so that data management is inefficiently performed.

The present invention has been made in view of the above-mentioned problems. The purpose of the present invention is to allocate a length of message reception to 512 bytes in one module to exclude message loss due to split transmission, and to allocate a bus to a node having no message to receive. By eliminating the loss, time is eliminated to improve performance in data transmission and reception, and unnecessary data is not received at the self-receiving node to efficiently manage received data.

In order to achieve the object as described above, the present invention is a communication device via a parallel bus, the control means for performing the overall operation of the system, the control signal applied from the control means and the external clock generating means is applied from Bus control means for setting a timing for occupying the address bus and the data bus according to a clock signal, and outputting a control signal according to the clock signal; and controlling the address bus occupancy on the control means side according to a control signal applied from the bus control means. A first buffer for buffering timing, a second buffer for buffering timing for the occupancy of a data bus for applying a data signal to the control means according to a control signal applied from the bus control means, an address bus and a data bus Memory means for storing data transmitted and received via; Provides a control apparatus for a parallel bus, it characterized in that it comprises a third buffer for receiving the external module and the data according to a control signal of the bus control means.

Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings.

2 is a block diagram of a control device of a parallel bus according to the present invention, and FIG. 3 is a detailed block diagram of the bus controller shown in FIG.

As can be seen in FIG. 2, the parallel bus controller of the present invention includes a processor 10, a first buffer 20, a second buffer 30, a memory unit 40, a bus controller 50, and a third controller. Buffer 60, processor 10 controls the overall operation of the system. The bus controller 50 outputs a control signal for occupying the address bus AB and the data bus DB according to an applied control signal and a clock signal. The first buffer 20 buffers a signal applied from the processor 10 through the address bus AB according to a signal applied from the bus controller 50 and outputs a signal for accessing the memory unit 40. The second buffer 30 is connected to the processor 10 through the data bus DB and buffers the corresponding data signal according to a control signal applied from the bus controller 50 to the processor 10. The memory unit 40 stores data transmitted and received via the address bus AB and the data bus DB. The third buffer 60 transmits / receives data to / from an external module according to a control signal of the bus controller 50 and stores the data in the memory unit 40 through the received data bus controller 50.

Referring to the operation of the present invention configured to have such a function as follows.

When the processor 10 allocates a unique number for a bus to be occupied for data transmission and reception to the bus controller 50, the bus controller 50 assigns a bus to be occupied according to a clock signal CK applied from the outside. The timings of the address bus AB and the data bus DB for the assigned unique number are set. After the timing of the address bus AB and the data bus DB is set, a signal for transmitting data is applied, and the bus controller 50 accesses the data stored in the memory 40 and then opens the third buffer 60. After buffering at the timing assigned for transmission, transmit to external module. When data is applied from the external module to the bus controller 50 through the third buffer 60, the bus controller 50 stores the applied data at a predetermined address of the memory 40 and displays an address stored in an internal register. . The signal for the address address at which data is received is applied to the first buffer 20 side, and the signal for the data address received at the second buffer 30 is applied. The first buffer 20 performs a buffering operation on the timing at which the signal for the address address is applied thereto, and the second buffer 30 buffers the applied data on the data bus at the timing allocated thereto. The processor 10 notifies the processor 10 whether the data has been received.

At this time, since the timing allocated to the node is not set in the node without the received data, the waste of time is eliminated in the transmission and reception of the data, thereby improving the performance of the transmission and reception. Data saved in the) is efficiently stored for easy management.

In addition, since data for the transmitted message is allocated to 512 bytes, the loss of the transmitted message is eliminated, thereby improving reliability in message transmission.

Claims (1)

In a communication apparatus using a parallel bus, the control means for performing the overall operation of the entire system, and the occupancy of the address bus and the data bus in accordance with a control signal applied from the control means and a clock signal applied from an external clock generating means. Bus control means for setting a timing for outputting the control signal and outputting a control signal according thereto, a first buffer for buffering timing for occupying the address bus on the control means side according to a control signal applied from the bus control means, and the bus control A second buffer buffering a timing for occupying a data bus for applying a data signal to the control means according to a control signal applied from the means, memory means for storing data transmitted and received via an address bus and a data bus; External module and data according to control signal of bus control means And a third buffer for transmitting and receiving data.