JP2971006B2 - Serial communication method and serial communication controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial communication method for controlling serial communication and a serial communication controller, and more particularly, to a method for controlling reception and transmission of both reception and transmission buffers when performing half-duplex communication. The present invention relates to a serial communication method and a serial communication controller that can be used as a buffer.

[0002]

2. Description of the Related Art Generally, there are two types of serial communication, full-duplex communication and half-duplex communication. Here, full-duplex communication is a communication method in which transmission and reception are performed simultaneously, and half-duplex communication is a communication method in which only one of transmission and reception is performed at a time. Hereinafter, a serial communication controller that controls serial communication will be described.

FIG. 5 is a block diagram showing an example of a conventional serial communication controller. The serial communication controller 60 includes a CPU interface 16 for controlling data exchange between an external CPU (central processing unit) and an internal circuit of the serial communication controller 60, and a reception shift for converting received data, which is serial data, to parallel data. , 14n for temporarily holding parallel data output from the reception shift register 12, and a transmission buffer for temporarily holding parallel data input from the CPU. , 18n, and a transmission shift register 20 that converts parallel data read from the transmission buffers 18a to 18n and outputs the converted data as serial data.

Next, the serial communication controller 60
Will be described. First, in reception, the reception shift register 12 converts received data, which is serial data, from serial to parallel and outputs it as parallel data, which are sequentially stored in the receiving buffers 14a to 14n. Here, when the maximum number, for example, four pieces of parallel data that can be held in the receiving buffers 14a to 14n is held, the interrupt request signal INT for requesting the CPU to read the received data from the CPU interface 16 is issued. Is output. Upon receiving the interrupt request signal INT, the CPU branches from the main routine to the interrupt routine, activates the read signal RD_, and sets the parallel data held in the receiving buffers 14a to 14n in accordance with the order in which the parallel data is held. After reading sequentially through the internal data bus, the CPU interface 16 and the external data bus, the process returns to the main routine again. Thus, the received data is read by the CPU.

In transmission, the CPU branches from the main routine to the interrupt routine, and writes the write signal WR.
_ To an active state, and the maximum number, for example, four parallel data that can be held in the transmission buffers 18a to 18n is sequentially transferred to the transmission buffers 18a to 18n through the external data bus, the CPU interface 16 and the internal data bus. After writing, it returns to the main routine again. The parallel data written in the transmission buffers 18a to 18n are sequentially read out in accordance with the writing order, and are read in parallel by the transmission shift register 20.
The serial data is converted and output as transmission data which is serial data. Here, the transmission buffers 18a to 18
When all the parallel data written in n is read, the CPU interface 16 sends a signal to the CPU.
An interrupt request signal INT requesting the writing of the next parallel data is output. The transmission data is transmitted in this way.

Since the serial communication controller 60 is designed for full-duplex communication, reception and transmission can be simultaneously and independently operated. In addition, in the full-duplex communication, it is possible to cope with the half-duplex communication by always performing only one of the transmission and the reception at a time.

In the serial communication controller 60 described above, at least one, and preferably a plurality of, receiving buffers 14a to 14n and transmitting buffers 18a to 18n are provided. One of the reasons is to prevent the interrupt request signal INT from being frequently output to the CPU.

[0008] For example, it is assumed that the reception buffer and the transmission buffer hold parallel data in units of 8 bits, and each has only one reception buffer and one transmission buffer. In this case, each time 8-bit received data is received and held in the receiving buffer, an interrupt request signal INT for requesting the CPU to read the received data is output. When one piece of parallel data is written from the CPU to the transmission buffer, an interrupt request signal INT for requesting the CPU to write the next parallel data is output each time the piece of parallel data is read.

As described above, the smaller the number of receiving and transmitting buffers, the more frequently the CPU outputs the interrupt request signal INT for requesting reading of the received data and writing of the transmitted data. Therefore, C
The PU takes a lot of time for the processing of the interrupt routine, and there is a problem that a sufficient time for the processing of the main routine cannot be avoided.

On the other hand, it is assumed that, for example, four reception buffers and four transmission buffers are provided, respectively. In this case, the interrupt request signal INT for requesting the CPU to read the received data is output until the parallel data is held in all the four receiving buffers, that is, until the 32-bit received data is received. Not done. Further, until four parallel data are written from the CPU to the transmission buffer and all of them are read out,
That is, until the 32-bit transmission data is read, C
An interrupt request signal INT requesting the PU to write the next parallel data is not output.

Thus, by providing n reception buffers and n transmission buffers, the number of times the interrupt request signal INT is output to the CPU can be reduced by 1 / n.
Can be For this reason, the overhead due to the processing of the interrupt routine can be reduced, and the CPU can be used efficiently.

Another reason for providing a plurality of receiving and transmitting buffers is to cope with a high communication rate.

As described above, when the reception data is held in the reception buffer and the interrupt request signal INT requesting the reading of the reception data is output to the CPU, C
The PU reads out the reception data held in the reception buffer. However, when the number of reception buffers is small and the communication rate is high, the next reception data is overwritten in the reception buffer before the CPU reads the reception data held in the reception buffer,
Received data before being overwritten will be lost,
A so-called reception overrun error occurs.

On the other hand, even when the transmission data is written to the transmission buffer, if the number of transmission buffers is small and the communication rate is high, the writing of the transmission data cannot be performed in time due to the overhead due to the processing of the interrupt routine. A so-called transmission underrun error occurs in which transmission data output from the communication controller is interrupted on the way.

In order to solve these problems, it is effective to increase the number of reception and transmission buffers. By providing a plurality of reception buffers in this manner, it is possible to cope with a high communication rate. Therefore, it is needless to say that it is preferable to provide as many reception buffers and transmission buffers as possible.

However, the provision of a plurality of receiving and transmitting buffers naturally increases the scale of the hardware. For this reason, there is a problem that the number of gates (the number of transistors) increases each time the number of reception and transmission buffers increases, and the layout area also increases.

Further, as described above, despite the fact that the hardware of the serial communication controller supports full-duplex communication, it is designed so that the transmission data is output after checking the error of the received data. There are many things that have been done. Therefore, in reality, the serial communication controller is often used for half-duplex communication. For example, a modem uses full-duplex communication,
Half-duplex communication is used in X modems, LANs (Local Area Networks) in general, and connections between personal computers and peripheral devices.

Conventionally, since a serial communication controller that supports full-duplex communication in hardware is often used for half-duplex communication in software, a transmission buffer is not used at the time of reception. Not used, conversely,
At the time of transmission, the receiving buffer was not used at all. For this reason, there is also a problem that any one of the reception buffer and the transmission buffer is wasted.

[0019]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a high-speed communication rate without increasing the scale of hardware in view of various problems based on the prior art. An object of the present invention is to provide a serial communication method and a serial communication controller that can reduce overhead due to interrupt processing even when the rate is low.

[0020]

In order to achieve the above object, the present invention provides a serial communication controller having at least one receiving buffer and at least one transmitting buffer. The reception and transmission buffers are used as reception and transmission buffers, respectively, and when receiving half-duplex communication, the reception and transmission buffers are both used as reception buffers, and when transmitting the half-duplex communication. The present invention also provides a serial communication method, wherein both the reception buffer and the transmission buffer are used as transmission buffers.

According to the present invention, there is provided a receiving unit having at least one receiving buffer, receiving serial data and converting the serial data into parallel data, and holding the parallel data in the receiving buffer; A transmission unit that has a trust buffer, holds parallel data to be transmitted in the transmission buffer, converts the parallel data into serial data, and transmits the serial data; Switching to duplex communication, when transmitting and receiving the full-duplex communication, the receiving and transmitting buffers are used as receiving and transmitting buffers, respectively, and when receiving the half-duplex communication, the receiving and transmitting buffers are used. Both are used as reception buffers, and during transmission of the half-duplex communication, both the reception and transmission buffers are used as transmission buffers. There is provided a serial communication controller, characterized in that it comprises a switching means configured to use as a file.

Here, the control signal for controlling the switching means is preferably a signal input from an external terminal or a signal output from an internal control register.

[0023]

The serial communication controller according to the present invention comprises:
Switching means for switching the communication mode between full-duplex communication and half-duplex communication according to a control signal is provided. Also,
In the serial communication method of the present invention, when performing reception and transmission simultaneously by full-duplex communication, the reception buffer is used as a reception buffer, and similarly, the transmission buffer is used as a transmission buffer. On the other hand, when performing reception by half-duplex communication, both the reception buffer and the transmission buffer are used as reception buffers. Similarly, when performing transmission, both the reception buffer and the transmission buffer are used as transmission buffers. Is done. Therefore, according to the serial communication method and the serial communication controller of the present invention, when used in full-duplex communication, it operates in exactly the same manner as a conventional serial communication controller, and can also receive or transmit half-duplex communication. When used, the number of reception buffers or transmission buffers can be doubled, so that not only can a higher communication rate be supported, but also the overhead due to interrupt processing can be reduced and the CPU can be used. It can be used efficiently.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a serial communication method and a serial communication controller according to the present invention will be described in detail based on preferred embodiments shown in the accompanying drawings.

FIG. 1 is a block diagram of one embodiment of the serial communication controller of the present invention. The serial communication controller 10 includes a receiving shift register 12 serving as a receiving unit and receiving buffers 14a, 14b, 14c, 1
4d, a CPU interface 16, transmission buffers 18a, 18b, 18c, 18d, transmission shift registers 20 as transmission units, and switching means 22. Note that the number of reception buffers and transmission buffers is not particularly limited.

In the serial communication controller 10, the reception shift register 12 is a so-called serial-to-parallel converter for converting serial data into parallel data having a predetermined bit length. That is, the reception shift register 12 receives the reception data which is serial data, and the reception shift register 12
The data is parallel-converted and output from the reception shift register 12 as parallel data having a predetermined bit length.

The receiving buffers 14a to 14d are
This is a FIFO (First-In-First-out) format buffer. That is, parallel data output from the reception shift register 12 is sequentially input to these reception buffers 14a to 14d and temporarily stored therein. When the parallel data is read from the reception buffers 14a to 14d, , Are sequentially read in accordance with the input order.

The CPU interface 16 controls exchange between a CPU that controls the serial communication controller 10 and an internal circuit of the serial communication controller 10. This CPU interface 1
6, a read signal RD_ and a write signal WR_ are input from the CPU, and an interrupt request signal INT is output from the CPU interface 16 to the CPU. An external data bus signal is used bidirectionally for communication with the CPU, and an internal data bus signal is used bidirectionally for communication with the internal circuit.

The transmission buffers 18a to 18d
It is a buffer of the FIFO format like the receiving buffers 14a to 14d. That is, these transmission buffers 18a
To 18d temporarily hold parallel data input from the CPU through the external data bus, the CPU interface 16, and the internal data bus. When parallel data is read from the transmission buffers 18a to 18d, the parallel data is input to Are sequentially read out according to the order in which they are read.

The transmission shift register 20 is a so-called parallel-to-serial converter for converting parallel data having a predetermined bit length into serial data. That is,
Parallel data read from the transmission buffers 18a to 18d is sequentially input to the transmission shift register 20 in accordance with the held order, and the transmission shift register 20 performs parallel-to-serial conversion. Output as transmission data which is serial data.

Finally, the switching means 22 switches the communication system of the serial communication controller 10 to either full-duplex communication or half-duplex communication. For example, by setting the control signal input to the switching means 22 to a high level, the serial communication controller 10 is used in full-duplex communication, and conversely, by setting it to a low level, the serial communication controller 10 is used in half-duplex communication. You.

The control signal input to the switching means 22 is a control signal input from the CPU through a dedicated input terminal, or a CPU interface 16 by the CPU.
Preferably, the control signal is a control signal output from an internal control register that is set by software through the CPU.

Next, the serial communication method of the present invention and the operation of the serial communication controller 10 will be described.

To use the serial communication controller 10 of the present invention in full-duplex communication, for example, a high level is set as a control signal input to the switching means 22. As a result, the serial communication controller 10 is used for full-duplex communication, that is, the receiving buffers 14a to 14d are used as receiving buffers and the transmitting buffers 18a to 18a are used.
8d are used separately as transmission buffers. The operation when the serial communication controller 10 of the present invention is used for full-duplex communication is the same as the operation of the conventional serial communication controller 60 shown in FIG.
Here, the description is omitted.

On the other hand, in order to use the serial communication controller 10 for half-duplex communication by applying the serial communication method of the present invention, a low level is set as a control signal input to the switching means 22. Thereby, the serial communication controller 10 is used for half-duplex communication, that is,
Reception buffers 14a to 14d and transmission buffer 1
As shown in FIG. 2, 8a to 18d are all used as reception buffers in the case of reception, and as shown in FIG. 3, all are used as transmission buffers in the case of transmission.

In the reception of the half-duplex communication, the reception data, which is serial data, is input to the reception shift register 12 and is converted from serial data to parallel data to be converted into parallel data having a predetermined bit length, for example, 8 bits. Buffers 14a to 14d and transmission buffers 18a to 1
8d are sequentially input and temporarily stored. Here, the reception buffers 14a to 14d and the transmission buffer 18
When the maximum number of parallel data that can be stored in each of the data a to d, for example, eight parallel data in the illustrated example, an interrupt request signal INT for requesting the CPU to read the received data from the CPU interface 16,
Is output. Upon receiving the interrupt request signal INT, the CPU branches from the main routine to the interrupt routine, and sets the read signal RD_ to an active state, for example, a low level, and sets the read signal RD_ to the parallel state held in the reception buffers 14a to 14d and the transmission buffers 18a to 18d. The internal data bus, C
After sequentially reading through the PU interface 16 and the external data bus, the process returns to the main routine again. Thus, the received data is received.

In transmitting half-duplex communication, the CPU
Branches from the main routine to the interrupt routine, and sets the write signal WR_ to an active state, for example, a low level, through the external data bus, the CPU interface, and the internal data bus to transmit the buffers 18a to 18d.
After the maximum number of data that can be held in the receiving buffers 14a to 14d, for example, eight parallel data in the illustrated example are sequentially written to the transmitting buffers 18a to 18d and the receiving buffers 14a to 14d, the process returns to the main routine. Return. Transmission buffers 18a to 18d
The parallel data written in the receiving buffers 14a to 14d are sequentially read out in accordance with the written order, and are converted from parallel to serial by the transmission shift register 20 and output as transmission data that is serial data. . Here, the transmission buffers 18a to 18d
When all the parallel data written to the receiving buffers 14a to 14d are read, the CPU interface 16 outputs an interrupt request signal INT requesting the CPU to write the next parallel data. The transmission data is transmitted in this way.

As described above, when the serial communication method of the present invention is applied and the serial communication controller is used for half-duplex communication, the transmission buffer is also used as the reception buffer at the time of reception. At the time of transmission, a reception buffer can also be used as a transmission buffer. For this reason, it can be used as twice as many receiving and transmitting buffers as the conventional one, although it has only the same number of receiving and transmitting buffers as the conventional one.

Therefore, according to the serial communication method of the present invention, it is possible to cope with serial communication at a high communication rate with a smaller hardware scale than adding a new reception and transmission buffer. In addition, even when the communication rate is relatively low, the overhead due to the processing of the interrupt routine can be reduced and the CPU can be used efficiently.

Next, the serial communication method and the serial communication controller of the present invention will be described more specifically with reference to specific examples.

FIG. 4 is a circuit diagram showing an embodiment of the serial communication controller according to the present invention. The serial communication controller 30 includes a reception shift register 12 serving as a reception unit, reception buffers 14a, 14b, 14c, and 14
d, the reception write pointer 28, the reception read pointer 32, and the multiplexer 34, the transmission buffers 18a, 18b, 18c, and 18d serving as transmission units, the transmission shift register 20, the transmission write pointer 40, and the transmission read pointer 42 And multiplexers 44, and selectors 24a, 24b, 24c, 24d as switching means,
Selectors 26a, 26b, 26c, 26d, selector 3
6a, 36b, 36c, 36d and selector 38a,
38b, 38c and 38d.

Here, the received data, which is serial data, is input to the receiving shift register 12, and the output signal 46 of the receiving shift register 12 is supplied to the selectors 24a to 24a.
4d and input terminals 1 of selectors 36a-36d. Similarly, the input signal 4 from the CPU
8 are selectors 36a to 36d through an internal data bus.
And input terminals 1 of selectors 24a to 24d.

The write enable signals R_WE0, R_WE1, R_WE are received from the write pointer 28 for reception.
2, R_WE3, R_WE4, R_WE5, R_WE
6, R_WE7 are output, and selectors 26a to 26
26d and input terminals 1 of selectors 38a-38d. Similarly, the write enable signals T_WE0 and T_WE are transmitted from the transmission write pointer 40.
1, T_WE2, T_WE3, T_WE4, T_WE
5, T_WE6, T_WE7 are output, and input terminals 0 of selectors 38a to 38d and selectors 26a to 26d respectively.
26d is input to the input terminal 1.

The output signals of the selectors 24a to 24d and the selectors 36a to 36d are respectively supplied to the receiving buffers 14a to 14d and the transmitting buffers 18a to 18d.
d to the data input terminal of the selector 26a.
To 26d and the output signals of the selectors 38a to 38d are
These are input to the write enable terminals WE of the receiving buffers 14a to 14d and the transmitting buffers 18a to 18d, respectively. The selection signals SEL are provided to the selection ends of the selectors 24a to 24d and the selectors 26a to 26d.
R is input to the selectors 36a to 36d and the selectors 38a to 38d.
ELT has been entered.

The receiving buffers 14a to 14d output parallel data R0, R1, R2, and R3.
These parallel data R0 to R3 are input to the data input terminals 0, 1, 2, 3 of the multiplexer 34 and the data input terminals 4, 5, 6, 7 of the multiplexer 44, respectively. Similarly, the transmission buffers 18a to 18d output parallel data T0, T1, T2, and T3. These parallel data T0 to T3 are output from the data input terminals 0, 1, 2, and 3 of the multiplexer 44 and the multiplexer 34, respectively. The data is input to data input terminals 4, 5, 6, and 7.

The selection signal 50 output from the reception read pointer 32 is input to the selection terminal of the multiplexer 34, and the output signal is connected to the internal data bus. Similarly, a selection signal 52 output from the transmission read pointer 42 is input to the selection end of the multiplexer 44, and the output signal is input to the transmission shift register 20. The transmission shift register 20 outputs transmission data that is serial data.

In the serial communication controller 30, the reception shift register 12, the reception buffer 14a
1 to 14d, the transmission shift register 20, and the transmission buffers 18a to 18d are the same as those in the serial communication controller 10 shown in FIG. Further, the reception write pointer 28 and the reception read pointer 32, and the transmission write pointer 40
Since the transmission read pointer 42 has the same function as the transmission read pointer 42, the reception write pointer 28
Only the reception read pointer 32 will be described.

First, the reception write pointer 28 is provided with write enable signals R_WE0 to R_WE7 for determining the reception buffers 14a to 14d or the transmission buffers 18a to 18d in which the output signal 46 output from the reception shift register 12 is held. Is output. The reception write pointer 28 has a counter that counts up each time the output signal 46 is output after serial-to-parallel conversion has been completed by the reception shift register 12. Enable signal R_WE
Only one of 0-R_WE7 is activated.

In the case of full-duplex communication, the value of the above-described counter is counted up in the range of '0' to '3'.
After '3', it is initialized to '0'. Also, one of the write enable signals R_WE0 to R_WE3 is activated according to the value of the counter from '0' to '3'. Similarly, in the case of half-duplex communication, the value of the above-described counter is counted up in a range of '0' to '7',
After '7', it is initialized to '0'. Also, one of the write enable signals R_WE0 to R_WE7 is activated according to the value of the counter from '0' to '7'.

Further, the reception read pointer 32 is used by the CPU among the parallel data R0 to R3 output from the reception buffers 14a to 14d and the parallel data T0 to T3 output from the transmission buffers 18a to 18d.
Outputs a selection signal 50 for selecting the parallel data to be read. The reception read pointer 32 has a counter which counts up each time parallel data is read out from the reception buffers 14a to 14d and the transmission buffers 18a to 18d by the CPU, and the value of this counter is "0". To '7', the data input terminals 0 to 7 of the multiplexer 34, respectively.
Is selected from among the parallel data R0 to R3 and the parallel data T0 to T3 input to the.

In the case of full-duplex communication, the value of the above-described counter is counted up in the range of '0' to '3'.
After '3', it is initialized to '0'. Similarly, in the case of half-duplex communication, the value of the above-described counter is counted up in the range of '0' to '7', and is initialized to '0' after '7'.

Next, the serial communication controller 30
Will be described.

First, the serial communication controller 30
Is used in full-duplex communication, the control signals SELR, SE
Both LT are set to low level. Thus, the selectors 24a to 24d, the selectors 26a to 26d, the selectors 36a to 36d, and the selectors 38a to 38d selectively output the signal input to the input terminal 0.

That is, the output signals 46 of the receiving shift register 12 are input to the data input terminals of the receiving buffers 14a to 14d, respectively, and the write enable terminals R_WE0 to R_WE3 are respectively supplied to the write enable terminals WE.
Is entered. Similarly, transmission buffers 18a to 18d
Of the input signal 48 from the CPU.
Is input through an internal data bus, and its write enable terminal WE has a write enable signal T_WE, respectively.
0 to T_WE3 are input.

In the reception of full-duplex communication, every time the reception data is converted from serial to parallel by the reception shift register 12 and the output signal 46 is output, the write enable signal R output from the reception write pointer 28 is output.
_WE0 to R_WE3 are activated in this order. As a result, the output signal 46 of the receiving shift register 12 is held in the receiving buffers 14a to 14d in this order. On the other hand, the CPU sets the reception buffers 14a to 14
When reading the parallel data R0 to R3 held in d, each time the CPU reads the parallel data R0 to R3, the selection signal 50 output from the reception read pointer 32 has a value of '0' to '3'. 'Are counted up in order. As a result, the parallel data R0-R
3 are selectively output in this order by the multiplexer 34, and are read out in this order by the CPU through the internal data bus.

In the transmission of full-duplex communication, the CPU
The write enable signal T_W output from the transmission write pointer 40 every time the input signal 48
E0 to T_WE3 are activated in this order. As a result, the input signal 48 from the CPU is held in the transmission buffers 18a to 18d in this order. on the other hand,
When the parallel data T0 to T3 held in the transmission buffers 18a to 18d are read, every time the parallel data T0 to T3 is read, the value of the selection signal 52 output from the transmission read pointer 42 becomes '0'. '~
It is counted up in the order of '3'. As a result, the parallel data T0 to T3 are selected and output in this order by the multiplexer 44, and are converted from parallel to serial by the transmission shift register 20 in this order and output as transmission data.

Next, the serial communication controller 30
Is used for receiving half-duplex communication, the control signal SEL
R and SELT are set to a low level and a high level, respectively. As a result, the selectors 24a to 24d and the selectors 26a to 26d selectively output the signal input to the input terminal 0, and conversely, the selectors 36a to 36d and the selectors 38a to 38d output the signal input to the input terminal 1. Selected output.

That is, the output signals 46 of the receiving shift register 12 are input to the data input terminals of the receiving buffers 14a to 14d, respectively, and the write enable signals R_WE0 to R_WE3 are respectively supplied to the write enable terminals WE.
Is entered. Similarly, transmission buffers 18a to 18d
The output signal 46 of the receiving shift register 12 is input to both data input terminals of the write enable terminal WE.
Respectively have write enable signals R_WE4 to R_W
E7 is input.

In the reception of half-duplex communication, the write enable signal R output from the reception write pointer 28 every time the reception data is converted from serial to parallel by the reception shift register 12 and the output signal 46 is output.
_WE0 to R_WE7 are activated in this order. As a result, the output signal 46 of the reception shift register 12 is held in the reception buffers 14a to 14d and the transmission buffers 18a to 18d in this order. on the other hand,
The CPU controls the parallel data R0 to R3 and the transmission buffer 18 held in the reception buffers 14a to 14d.
a to 18d of parallel data T0 to T3
Is read by the CPU, the parallel data R0 to R
Every time 3 and the parallel data T0 to T3 are read, the value of the selection signal 50 output from the reception read pointer 32 is counted up in the order of '0' to '7'. As a result, the parallel data R0 to R3 and the parallel data T0 to T3 are selected and output in this order by the multiplexer 34, and are read out in this order by the CPU through the internal data bus.

Next, the serial communication controller 30
Is used for transmitting half-duplex communication, the control signal SEL
R and SELT are set to a high level and a low level, respectively. Thus, the selectors 24a to 24d and the selectors 26a to 26d select and output the signal input to the input terminal 1, and conversely, the selectors 36a to 36d and the selectors 38a to 38d output the signal input to the input terminal 0. Selected output.

That is, an input signal 48 from the CPU is input to both data input terminals of the transmission buffers 18a to 18d, and write enable signals T_WE0 to T_WE3 are input to their write enable terminals WE, respectively.
Similarly, an input signal 48 from the CPU is input to the data input terminals of the receiving buffers 14a to 14d, and write enable signals T_WE4 to T_WE7 are input to the write enable terminals WE, respectively.

In the transmission of half-duplex communication, every time the input signal 48 from the CPU is input, the write enable signals T_WE0 to T_WE0 output from the transmission write pointer 40
T_WE7 is activated in this order. As a result, the input signal 48 from the CPU is transmitted to the transmission buffer 1.
8a to 18d and reception buffers 14a to 14d are stored in this order. On the other hand, the transmission buffers 18a-1
When the parallel data T0 to T3 held in 8d and the parallel data R0 to R3 held in the reception buffers 14a to 14d are read, every time the parallel data T0 to T3 and the parallel data R0 to R3 are read, The value of the selection signal 52 output from the transmission read pointer 42 is counted up in the order of '0' to '7'. As a result, the parallel data T0 to T3
And the parallel data R0 to R3 are
4, the data is selectively output in this order, and is converted from parallel to serial by the transmission shift register 20 in this order and output as transmission data.

As described above, the serial communication controller 3
At 0, the communication system of the serial communication controller 30 can be switched to either full-duplex communication or half-duplex communication by appropriately setting the control signals SELR and SELT. When used in half-duplex communication, the transmission buffers 18a to 18d can also be used as reception buffers in reception, and similarly, the reception buffers 14a to 14d are also used as transmission buffers in transmission. be able to.

[0064]

As described in detail above, in the serial communication method and the serial communication controller of the present invention, the serial data communication method is switched to either full-duplex communication or half-duplex communication. Of course, the same operation as the conventional serial communication controller can be performed by the duplex communication, and furthermore, the reception buffer and the transmission buffer can be used as the reception buffer in the reception of the half-duplex communication. In transmission, these buffers can be used together as transmission buffers. Therefore, according to the serial communication method and the serial communication controller of the present invention, with a smaller hardware scale than adding a new reception and transmission buffer,
It is possible to increase reception and transmission buffers,
It is possible to cope with a higher communication rate, and to reduce the overhead due to interrupt processing,
The PU can be used efficiently.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment in full-duplex communication of a serial communication controller of the present invention.

FIG. 2 is a block diagram of an embodiment in receiving half-duplex communication by the serial communication controller of the present invention.

FIG. 3 is a block diagram of one embodiment of transmission of half-duplex communication by the serial communication controller of the present invention.

FIG. 4 is a configuration circuit diagram of an embodiment of a serial communication controller according to the present invention.

FIG. 5 is a block diagram of an example of a conventional serial communication controller.

[Explanation of symbols]

10, 30, 60 Serial communication controller 12 Reception shift register 14a, 14b, 14c, 14d, ..., 14n Reception buffer 16 CPU interface 18a, 18b, 18c, 18d, ..., 18n Transmission buffer 20 Transmission shift register 22 Switching means 24a, 24b, 24c, 24d, 26a, 26b, 2
6c, 26d, 36a, 36b, 36c, 36d, 38
a, 38b, 38c, 38d selector 28 reception write pointer 32 reception read pointer 34, 44 multiplexer 40 transmission write pointer 42 transmission read pointer 46 output signal 48 input signal 50, 52, SELR, SELT selection signal R_WE0, R_WE1 , R_WE2, R_WE3, R
_WE4, R_WE5, R_WE6, R_WE7, T_
WE0, T_WE1, T_WE2, T_WE3, T_W
E4, T_WE5, T_WE6, T_WE7 Write enable signal R0, R1, R2, R3, T0, T1, T2, T3 Parallel data

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁶ , DB name) H04L 29/08 H04L 5/14

Claims (3)

(57) [Claims] 1. A serial communication controller having at least one reception buffer and at least one transmission buffer, wherein the reception and transmission buffers are used as reception and transmission buffers when transmitting and receiving full-duplex communication. When receiving the half-duplex communication, both the reception buffer and the transmission buffer are used as a reception buffer, and when transmitting the half-duplex communication, the reception and transmission buffers are both used as a transmission buffer. A serial communication method, comprising: 2. The apparatus according to claim 1, further comprising at least one receiving buffer.
A receiving unit that receives serial data, converts the data into parallel data, and stores the parallel data in the reception buffer; and at least one transmission buffer, and stores parallel data to be transmitted in the transmission buffer. A transmission unit that converts the parallel data into serial data and transmits the data; and a control signal that switches the communication method between full-duplex communication and half-duplex communication. The trust buffer is used as a reception buffer and a transmission buffer, respectively.When receiving the half-duplex communication, the reception buffer and the transmission buffer are both used as reception buffers. Switching means for setting both the transmission buffer and the transmission buffer to be used as the transmission buffer. Real communication controller. 3. The serial communication controller according to claim 2, wherein the control signal for controlling the switching means is a signal input from an external terminal or a signal output from an internal control register.