KR960003073B1 - Apparatus for rapidly clearing the output display of a computer system - Google Patents

Abstract

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Description

Device for quickly clearing the output display of a computer system

1 is a block diagram illustrating an arrangement for selecting individual frames displayed on a computer output device according to the present invention.

2 is a block diagram illustrating an arrangement for selecting individual windows displayed on a computer output device in accordance with the present invention.

3 is a block diagram illustrating an arrangement for selecting a particular frame including a three-dimensional image displayed on a computer output device according to the present invention.

4 is a truth table useful for explaining the operation of the arrangement shown in FIG.

5 is a block diagram of a system incorporating a device for selecting a window, frame, and depth size of a signal provided to a computer output device.

FIG. 6 is a truth table useful for explaining the operation of the circuit shown in FIG.

7 is a block diagram illustrating a register and a memory addressable from a central processing unit to a host address bus in accordance with the present invention.

8 is useful for understanding the operation of erasing the frame recognition memory according to the present invention.

TECHNICAL FIELD The present invention relates to logic circuits, and more particularly to logic circuits that provide significantly different switching between output display frames in a computer system.

As computer systems, such as workstations, have become increasingly complex, it has become apparent that they are conveniently used to synthesize cartoon images in movies and television.

A computer capable of supplying animated output offers a clear advantage over television and movies because, unlike anything else, it is possible to compose and modify animated display images.

The ability of computers to provide three-dimensional representations has accelerated and augmented the need for systems capable of handling animated objects.

An important problem in using a computer to provide animated output is that the animation needs to be displayed in incremental, fast-paced, frame-by-frame displays.

In order to display a single frame of graphic material on a cathode ray tube (CRT), it is necessary to store an indication for each position (pixel) appearing in the cathode ray tube or other display information displayed at that position.

For a large and detailed display, the number of pixels in the cathode ray tube is averaged about 1000 in the horizontal direction and a total of 1 million pixels is given for any information stored as the same number in the vertical direction.

In a preferred system capable of providing several different colors and hues to the cathode ray tube, each of these pixels has 24-bit digital information that defines a particular color output.

As a result, about 24 million bits of information are needed to store each frame represented as an output.

However, storing nearly 24 million bits in each memory location of a frame provided as an output to the cathode ray tube actually takes a considerable amount of time, and erasing those bits to provide the next frame requires more time. .

The slight delay between frames was eliminated using a double buffer system provided with two full screen bitmapped memory and alternately switched to the cathode ray tube.

Such a system can shorten the time between two frames of information display but does not eliminate the need to quickly erase each display memory and must be recorded in subsequent frames.

As a result, even double buffered systems are very slow to provide optimum output for animation purposes.

Therefore, a first object of the present invention is to improve the speed at which images are switched from frame to frame and displayed at the output of a computer system.

It is a second object of the present invention to eliminate the actual delay associated with erasing the display memory between frames in a computer system.

A third object of the present invention is to eliminate the need to erase the display and depth memory between frames of a computer system.

A fourth object of the present invention is to improve the operating speed of a computer system.

The present invention essentially eliminates the time normally used to clear the display memory of the computer system, thereby improving the speed at which individual frames can be switched to the output of the computer system.

The system accomplishes this by providing a double buffer frame recognition memory for storing an indication of a frame stored corresponding to information in the associated display memory.

Each pixel in the display memory has a corresponding associated pixel in the frame recognition memory. When a frame stored in the display memory is read, the output frame recognition register indicates the frame to be read as a frame number, which indicates the value of each pixel in the frame recognition memory when the frame recognition memory and the display memory are scanned for cathode ray tube refresh. Is compared with

Only pixels in the selected frame are provided to be output from the display memory to the cathode ray tube.

At pixels whose number of output frame recognition registers and frame recognition memory are not compared, the background color generator is activated to provide information to the cathode ray tube. This allows frame-to-frame writing to the display memory to continue without erasing the display memory and deleting only a small portion of the frame recognition memory.

A somewhat similar additional logic array is provided to determine the depth at which pixels of a particular frame are written along the Z-axis so that the three-dimensional shape is correctly displayed on the two-dimensional output display.

The present invention allows the Z-buffer to continue to use frame-to-frame without deleting the Z buffer. In addition, another similar logical arrangement is provided for determining the window in which pixels of a particular frame are written so that the window can be handled in the same system.

These and other features and advantages of the present invention will become apparent to those skilled in the art in the following detailed description, together with the several figures.

[Frame Recognition]

Referring to FIG. 1, there is shown a display output system 10 for quickly processing information in accordance with the present invention.

For the purposes of this description, the frame may include a particular graphic or data structure that is desired to be displayed as a full screen display on a cathode ray tube or other computer output device.

System 10 operates under the control of a central processing unit (CPU), not shown in FIG. When it is desired to record a particular graphic frame on an output device such as a cathode ray tube (CRT) 12 shown in FIG. 1, the actual information displayed is recorded in the display memory.

The system 10 includes a first display memory (A) 13 and a second display memory (B) 14.

The parallel use of two display memories whose output is selected by the multiplexer 15 allows for fast switching between the frames of the display required to complete the animation.

In the normal case, the frame is written to the display memory A while the frame in the display memory B is supplied as an output to the cathode ray tube. The frame information of the display memory A is supplied as an output to the cathode ray tube while a new frame is written to the display memory B.

In the prior art system, each display memory A and B must be deleted before new information is stored therein.

With a display that has a significant number of pixels and writes 24-bits of information to each pixel as in the preferred embodiment, this erasing step is time consuming and can delay the operation of the system to the point where its use in animation is impractical. have.

In order to avoid loss of time and to provide the necessary switching speed for animation, the output system 10 of the present invention also has a pair associated with an input frame recognition (FID) register 16, similarly named display memories A and B. Frame recognition (FID) memory (A 17 and B 18), output frame recognition (FID) register 19, background color register 20 and control register 21.

The system 10 also includes a multiplexer 22, a comparator circuit 23, a write enable logic 24, and a logic circuit 25.

The operation of system 10 is as follows. The CPU uses the control register using the host data bus to select whether to write to the FID memory (A 17 or B 18) and its associated display memory (A 13 or B 14). Enter a value in (21).

The CPU then supplies a frame recognition number stored in the input frame recognition register 16 used for all information to be written for the frame. In the preferred system, 16 frame numbers (0-15) are used.

After the input frame recognition register is initialized the frame number, the actual information displayed on the output device is sent from the CPU to the selected display memory (A or B).

The display memories A and B are full screen bitmapped memories, respectively.

Frame recognition memories A and B are also full-screen bitmap memories, each of which is a multiplexer 22 which receives input from input (FID) register 16 and allows the output to be quickly switched for display of animated graphic images. To output).

Each piece of input information on the host data bus from the CPU carries pixel addresses and color information (e.g. RGB color values).

Assuming that the display memory A and the FID memory A are selected, the RGB color value is the appropriate pixel address in the display memory A while the frame identification number is written to the same pixel address of the frame recognition memory A. Is filled in.

Whereas a preferred system requires storage of 4 bits of frame identification number, RGB color values require 24 bits of storage for each pixel.

As a result, when any particular previous frame has been written to the display memory A, the display memory A includes an indication to be displayed with RGB color values at the address position selected for the particular frame. Assuming that a triangle (shown on the upper left side of the CRT 12) is stored in the display memory A and written in the cathode ray tube 12 shown in FIG. 1, the color values of the triangle are displayed in the display memory A. The triangular marks are stored in the same pixel in the frame recognition memory A but as frame identification numbers while located in the appropriate pack cells.

For example, if a triangular mark is stored as frame zero, the color mark is provided as a triangle in the display memory while the half call zero is stored at the same triangular position in the associated FID memory. When displaying frame zero on the CRT, the CPU stores the frame identification number which is zero in this case in the output frame recognition register 19 using the host data bus (4 bit register in the preferred embodiment).

The CPU also writes to the control register 21 such that the multiplexers 22 and 15, which control the output of the frame recognition memory and the display memory, respectively, are set to select an output from the memory A.

Then, as each pixel of the display memory A is scanned to its output through its combined multiplexer, the frame recognition value is also scanned from the frame recognition memory A for a particular pixel.

The value from the frame recognition memory will be zero only at the location where the triangle is stored.

As a result, the comparator circuit 23 for comparing the selected frame recognition memory with the output from the output frame recognition register 19 provides a signal indicating a pixel of the frame recognition memory A in which frame zero is written (i.e., Triangle has a frame identification number of zero).

Therefore, at the position where the frame recognition memory A stores the zero frame identification number, the comparator circuit supplies the same output indicating a pixel which is part of the current frame; The RGB color signal stored in the pixel in the display memory A is supplied to the cathode ray tube via the logic circuit 25.

On the other hand, in every pixel other than having a frame identification number zero in the frame recognition memory A, the comparator circuit 23 provides an output that is not the same indicating that the pixel is not part of the current frame; The background color is provided from the background color register 20 and transmitted to the cathode ray tube 12.

This arrangement of signal processing has many advantages.

For example, the system needs to be stored in display memory only at locations where color values indicate front data.

As a result, the storage of information can be processed at a faster rate than a normal system where 24-bit information must be stored in each pixel.

In particular, the display memory does not have to be deleted after the information about the frame has been read in order to write subsequent frames in the memory.

For example, after frame zero is processed as described above, subsequent frames processed by a particular FID memory have a subsequent frame number of one. As a result, the information recorded in the display memory associated with the FID memory is simply written above the information in that memory since only the information finally provided to the display will be the information associated with frame number 1 selected by the FID output register.

It will be appreciated that this configuration, which eliminates the need to delete display memory, speeds up the operation of the system and allows for fast switching for animation.

Although the use of the FID memory and registers allows the system to operate without erasing the display memory between specific frames, the number of bits used in the frame identification number system, which is preferably 4 bits, may indicate how many frames are written before the FID memory is deleted. Decide if you can.

As a 4-bit digital storage device for recording frame numbers, 16 frames can be used.

If the FID memory has not been deleted after 16 frames, it is possible to remain in the FID memory, for example, as the information associated with the previous zero frame arrives at the zero frame again.

Since this information can be an error, the system needs to clear the FID memory at least once every 16 uses.

An advantageous way to complete the deletion without delaying the system to some extent is to delete at least 1/15 of the FID memory after each frame has been written to the output device.

8 illustrates the division of the FID memory into 15 horizontal strips.

After the zero frame is displayed on the CRT, the erase value of the “0” frame number is written to the top horizontal strip of the FID memory; After one frame is displayed, the erase value of the "1" frame number is written to the subsequent horizontal strip of memory. After each successive display of the frame, a similar value is supplied to each successive horizontal strip.

As a result, the next time the zero frame is written to the FID memory, the memory is erased with all horizontal strips below the top strip to zero, and the top strip of the original zero value FID memory is filed with 15, the last frame number used. Will be deleted as a whole value of zero.

As a result, the old zero frame signal will not appear to distort the information stored in the FID memory.

As each next frame number is written, the same result occurs and just before a new frame is written, the memory will erase all indications for that frame number. Of course, erasing a value from a memory consists of the prior art, which is well known by means of special means for a particular memory element.

It is obvious to those familiar with this technique that deleting 1/15 of the FID memory after each frame output to the CRT is considerably faster than the arrangement used by conventional systems that require erasing the entire display memory with each output to the CRT. something to do.

First, the display memory contains 24 bits in each pixel, each of which must be erased. On the other hand, the FID memory has only 4 bits in each pixel.

This alone will result in a six times faster system even if the FID memory is totally erased after each write to the output device.

In the preferred embodiment of deleting only 1/15 of the FID memory, the time required is 1/15 of the time to delete the entire FID memory.

As a result, the total time used for erasing in the present system is almost 1/90 of the time required in conventional systems with equivalent display memory.

This advantage can be easily improved by using more bits of FID memory.

[Window Recognition]

The output system described with respect to FIG. 1 can be conveniently used for a computer system using multiple windows. For example, FIG. 2 illustrates a window recognition output system 30 that can be used with or without the frame recognition structure.

The system 30 is used to supply an output signal to the cathode ray tube 12 in which signals appear in different windows of the cathode ray tube.

The system 30 includes a pair of double buffer display memories A 13 and B 14, each of which is a full screen bitmap memory.

In a preferred embodiment, each display memory may include 24 bits of storage for each pixel that stores color information. The system 30 also includes a window recognition (WID) register 34 which stores four bits of information in a preferred embodiment and a window recognition which is a full screen bitmap memory that stores four bits of information for each pixel in a preferred embodiment. WID) memory 35.

The window recognition (WID) comparator 36 receives an output signal from the WID register 34 and the WID memory 35. The system 30 also includes a multiplexer 37, write enable logic 38, and a control register 39 for selectively enabling respective display memories A and B. As shown in FIG.

In operation, the window is first selected by the value supplied from the CPU. These values include the pixel address and the window identification number for each pixel in the window.

The window identification number is written in each corresponding pixel of the specific window in the window recognition memory 35. When the first window is written to the window recognition memory, each pixel in that window carries a window identification number for that window.

When the next window located in front of the first window is written to the window recognition memory, the portion of the second window overlapping the first is written over the first overlap pixel, and therefore automatically covers and clips the first.

After all necessary windows have been recorded, the window recognition memory 35 stores the display shown in the CRT 12 display of FIG.

When information needs to be stored in the display memory for a particular window (a window system can be used not only as a double buffer system but also as a single display memory), the information is written from the CRT to the display memory via the data bus.

This information includes the pixel address, the above mentioned RGB color value, and the window identification number. The window recognition number is stored in the window recognition register 34 and compared with the window recognition number stored in the pixel in the window recognition memory 35.

If the window recognition number stored in the window recognition memory 35 is the same as the number in the window recognition register 34, the comparator circuit 36 causes the address enable pixel 38 of the display memory to which the write enabler 38 selects the RGB information. To be filled in.

If the comparator circuit determines that the window recognition number is not equal to the number stored in that pixel in the window recognition memory, the RGB information is not stored in the display memory. As a result, a signal for the window will be written only at that address of the selection display memory in each particular window.

The signal recorded in the display memory is finally transmitted from the specific display memory via the multiplexer 37 to the cathode ray tube 31 shown in FIG.

Many additional benefits are realized with the use of the window recognition system described herein.

For example, a window recognition system allows information in a particular window to be written in the correct area of the display and to clip any portion of any particular window that is located behind another window.

In addition, since the window recognition memory is a full screen bitmap memory, the window can be of any shape that can be displayed even if it is not a rectangular window as usual.

[Depth information]

In order to provide fast switching between frames of the display memory without erasing such display memory, the system shown in FIG. 1 also incorporates a device that provides an output that indicates the depth of each pixel provided to a particular display on the cathode ray tube. Can be. Several systems for providing depth information are well known in the art, but the normal method provides an indication that is recorded in the display of the position of the pixel along the Z axis (three-dimensional axis) with each pixel.

3 illustrates a system 40 that includes this information.

The system 40 includes a Z buffer memory 41 for storing Z, that is, a depth information value, a Z buffer comparison circuit 42 for comparing the Z buffer values stored in a new Z value for each particular pixel, and a FID memory output. The multiplexer 43 and the comparator 44 are added to the first circuit.

The write enable logic circuit 24 is used to control the recording of information in the FID memory, the Z buffer memory, and the display memory.

Although common in display memory, it is desirable to use a Z buffer memory 41 that does not need to be erased during operation to increase system operation.

The normal Z buffer memory is a full screen bitmap memory that stores, in each pixel address, an indication of a specific position that a pixel takes along the Z axis, such as a FID memory, a display memory, and a window memory.

In a preferred embodiment of the present invention, the Z buffer memory stores 24 bits in each pixel; As a result, erasing this memory can actually slow down the system. In a conventional system, the Z buffer memory is first deleted with a background Z value after each frame. This occurs because the Z buffer memory for each frame only stores the best value for each pixel.

Since the background is the deepest indication that can be displayed, the Z buffer memory is normally erased in the background before any frame is recorded. If not deleted, after the system has been running for some time, the Z buffer memory stores information from multiple previous frames and needs to know which pixels are used and which are excluded.

In order to know whether a new pixel should be written to the display memory, it is first necessary to know whether that pixel of the frame recognition memory contains the information in the frame to be written.

This determination is made in a system using the particular FID memories 17 and 18 and the input frame recognition register 16 selected by the control register 21. The obtained FID number is compared with the FID number stored in the displayed pixel in the FID memory; If the comparison result numbers are the same, the FID comparator 44 is in a frame in which the FID number stored in that pixel is being written, and therefore the write enable indicating that the pixel has been written at least once for this frame. The same output is supplied to the logic 24.

If the FID numbers are not the same, this pixel has not been previously written to this frame, and the comparator circuit 44 supplies a signal to the write enable logic that causes the acquisition information to be written to several memories.

In this case, the selected display memory receives the color display signal at the fax cell position, the selected FID memory receives the new frame recognition number, and the Z value is written to the Z buffer memory.

If the signal from the FID comparator 44 is the same to indicate that the pixel was previously written to this frame, then the Z buffer comparison needs to determine whether to write. The Z buffer comparator 42 indicates the Z value at the pixel position in the Z buffer memory and compares it with the new Z value.

If the Z buffer comparison is equal to or less than the number stored in memory, the new pixel is located on the same plane or in front of the previously written pixel, and write enable logic is appropriate for display memory, FID memory, and Z. Pixels can be written to the buffer memory.

A truth table is shown in FIG. 4 and shows the comparison values used in the FID comparator 44 and the Z buffer comparator 42 to operate the write enable logic so that the pixels can be written to a memory different from the display memory. For the comparator output in the table, 1 indicates that the = or <= condition is true, 0 indicates that the condition is not true, while X indicates that the comparison condition is not used.

For a write output, 0 means no write occurs and 1 means write occurs.

As the table shows, when the FID memory comparison results in that the FID numbers are different, a new frame is written and the write enable circuit is operated whatever the Z buffer comparison is.

On the other hand, if the FID comparison indicates that the FID numbers are the same, the result of the Z buffer comparison controls the operation of the write enable circuit.

5 shows a system incorporating the elements of the invention described above to provide very fast switching between frames displayed by a pair of double buffer display memories in an output cathode ray tube.

The system includes a control register 21 which receives an input signal from the CPU on the data bus and sends a signal to enable the window recognition circuit, the Z buffer circuit and the frame recognition circuit.

The control register also selects which of the double buffer display memories 13 and 14 and the frame recognition memories 17 and 18 is selected for any particular operation, such as input or output.

The system 50 also includes a write enable logic 24 that acts as a central control to write information into the frame recognition memory, the Z buffer memory, and the display memory.

In operation, system 50 operates in the following manner. The control register 21 receives a value indicating which of the specific elements of the circuit is enabled,

For example, a particular program may or may not operate as a window comparison circuit, a frame recognition register, or a Z buffer memory circuit. This is true because a particular program may not have enabled window behavior, may not operate in a three-dimensional region, or may not be used to provide animation at a particular time.

The following discussion assumes that all three subsystems are enabled by signals to the control register. The basic operation of the system 50 is to first determine whether the data signal is in a particular window, then determine whether the data signal enters the specific frame in which it is written, and finally the data signal stored for that frame is It is determined whether or not it is located before the data signal already stored in the frame.

The first step of any operation is to store a window used in the window recognition memory. This is done by writing a value from the CPU indicative of each window to be used into the window recognition memory 35.

Then, when a particular pixel is desired to be written to the display memory 13 or 14, a value is stored in the control register 21 to select the appropriate A or B display memory and the appropriate associated frame recognition memory 17 or 18.

The CPU writes the value of the current window into the WID register 34 and writes the value of the current frame into the input FID register 16.

In the window recognition circuit, the window number in the WID register 34 is compared with the window identification number stored in the window recognition memory 35, and if they are the same (i.e. when the information of the pixel is located in the window), The signal is sent to the write enable logic 24.

In the input FID comparator 44, the frame number in the input FID register is compared with the frame number stored in the frame recognition memory selected for the control register.

If the comparison is not the same, the pixel has not yet been written to this frame (if an enable signal has been received from the window-aware comparison circuit) and the signal has a write enable logic causing the write enabler to write to each memory. Supplied directly to (24).

That is, the write enable logic writes to the selected specific FID memory, to the Z buffer memory, and to the display memory selected by the control register.

If the enable signal has not been received from the window recognition comparator, the enable signal from the FID comparator does not cause the write enable logic to write anywhere in the memory.

Assuming that the window comparator provided the enable signal and that the comparison of the signals in the FID register and the selected FID memory and that the selected FID memory indicates the same pixel recognition, this indicates that this pixel has already been written to the address for this frame; It is necessary to compare the Z buffer to determine whether this pixel is in front of the already stored pixel.

Z buffer comparison compares the Z values stored in the Z buffer memory for that pixel with the Z values supplied by the CPU.

If the Z value supplied by the CPU is less than or equal to that stored in the Z buffer memory, the new or current pixel is before the stored pixel; The signal is provided for the write enable logic to write to the FID memory, the Z buffer memory, and the selected display memory.

FIG. 6 is a truth table illustrating how the comparison results in the window comparator circuit, the frame recognition comparator, and the Z buffer comparator control the operation of the write enable circuit in FIG.

The other parts of the circuit shown in FIG. 5 for the system 50 are in fact identical to those already described and will not be described again in detail. For example, background color register 20 is used to provide a background color at a location where a pixel displayed on the CRT is not a foreground pixel of the selected frame.

As described above, the output FID register 19 is used to determine the output frame identification number by comparing it with the frame identification number stored in the selected FID memory, and to output from the appropriate display memory or background color register.

Although the present invention has been described by preferred embodiments, various modifications and alterations may be made by those skilled in the art without departing from the spirit and scope of the invention.

Therefore, the present invention should be evaluated with the following claims.

Claims (26)

A computer output system for displaying information of a plurality of individual frames on a display means including a display, comprising: a first memory having a first memory having a plurality of pixel storage positions for storing the frame information at pixel positions; Way ; A second memory including a second memory having a plurality of pixel positions corresponding to the pixel positions in the first memory for storing one of a plurality of n-bit frame representations in each of the pixel positions in a second memory; Means (each said n-bit representation represents one of said plurality of individual frames of information stored in said first memory); Input the frame information into the first memory and the n-bit frame representation into the second memory such that the frame information and the n-bit frame representation occupy the same pixel location in the first and second memories, respectively. Input means coupled to the first memory means and to the second memory means for communication; If the display is the same, the display indicating the specific frame to be displayed on the display is stored at the pixel position in the second memory means such that the frame information stored at the corresponding pixel position in the first memory is displayed on the display. First comparing means coupled to the second memory means for comparing with the displayed display; And erasing means coupled to said second memory means for deleting successive portions of said second memory after information of each particular frame is displayed on said display, wherein said deleted portion is at least displayed in said specified portion. And a pixel location of said second memory for storing an n-bit frame representation of frame information. 2. The apparatus of claim 1, further comprising: a third memory having a plurality of pixel positions corresponding to the pixel positions in the first memory for storing one of a plurality of displays at each of the pixel positions in a third memory; Third memory means connected to an input means, each said display representing a window displayed on said display; And second comparing means coupled to said third memory means for comparing an indication indicative of a particular window to be displayed on said display with said indication stored at said pixel location in said third memory means; And the input means inputs the information to be displayed on the display to the first memory means if the displays compared by the second comparison means are the same. 2. The apparatus according to claim 1, further comprising a register means coupled to said first comparing means and said input means for storing background color information, said register means being equal to said indication compared by said first comparing means. Otherwise display the background information on the display. 4. The apparatus of claim 3, wherein the first memory of the first memory means comprises a first pair of all screen bitmap memories, and wherein the second memory of the second memory means is a second pair of all screen bitmap memories. Computer output system comprising a. 5. The apparatus of claim 4, wherein the first memory means further comprises first selecting means for selecting one of the bitmap memories in the first pair of bitmap memories, wherein the second memory means comprises: the second memory means; And second selecting means for selecting one of said bitmap memories in a pair of bitmap memories. 6. The computer output system of claim 5 wherein said first and second selection means each comprise a multiplexer. 7. The computer output system of claim 6 wherein the frame information includes an RGB color value. The computer output system of claim 1, wherein the frame information comprises an RGB color value. A computer output system for displaying a plurality of individual frame information on a display means including a display such that information appears three-dimensionally on the display, the computer output system having a plurality of pixel storage positions for storing the frame information at pixel positions. First memory means including a first memory; A second memory including a second memory having a plurality of pixel positions corresponding to the pixel positions in the first memory for storing one of a plurality of n-bit frame representations in each of the pixel positions in a second memory; Means (each said n-bit representation represents one of said plurality of individual frames of information stored in said first memory); Third memory means including a third memory having a plurality of pixel positions corresponding to the pixel positions in the first memory for storing depth information at each of the pixel locations in the third memory; Conditionally input the frame information into the first memory such that the frame information, the n-bit frame indication, and the depth information occupy the same pixel position in the first, second, and third memories, respectively, to the first memory means, the second memory means and the third memory means to conditionally input an n-bit frame indication into the second memory and to conditionally input the depth information into the third memory. Input means coupled; If the display is not the same, the input means transfers the frame information to the corresponding pixel position in the first memory, the display to the pixel position in the second memory, and the depth information to the pixel in the third memory. The third memory means and the third to compare the depth information stored in the third memory with the depth information input by the input means when the indications compared by the first comparing means to store in the position are the same. And a second comparing means coupled to the input means. 10. The specific frame according to claim 9, wherein if the display is the same, the frame information and the depth information stored in the corresponding pixel position in the first and second memory means respectively are displayed on the display. And third comparing means coupled to said second memory means and to said input means for comparing an indication of with said indication stored at said pixel location in said second memory. 11. The apparatus of claim 10, further comprising a register means coupled to the third comparing means and the input means for storing background color information, wherein the memory means is not the same as the indication compared by the third comparing means. Otherwise display the background information on the display. 12. The apparatus of claim 11, wherein the first memory of the first memory means comprises a full screen bitmap memory of a first memory pair, and wherein the second memory of the second memory means is a second screen of all screen bitmaps. Computer output system comprising a memory. 13. The apparatus of claim 12, wherein the first memory means further comprises first selecting means for selecting one of the bitmap memories in the first pair of bitmap memories, wherein the second memory means comprises: the second memory means; And second selecting means for selecting one of said bitmap memories in a pair of bitmap memories. The computer output system of claim 13, wherein the first and second selection means each comprise a multiplexer. 15. The computer output system of claim 14 wherein the frame information comprises an RGB color value. 10. The computer output system of claim 9, wherein the frame information comprises an RGB color value. A computer output system for displaying information of a plurality of individual frames such that information can be selectively displayed in a window and three-dimensionally on a display, the display comprising means for storing the frame information at pixel locations. First memory means including a first memory having a plurality of pixel storage locations; A second memory including a second memory having a plurality of pixel positions corresponding to the pixel positions in the first memory for storing one of a plurality of n-bit frame representations in each of the pixel positions in a second memory; Means (each said n-bit representation represents one of said plurality of individual frames of information stored in said first memory); Third memory means comprising a third memory having a plurality of pixel positions corresponding to said pixel positions in said first memory for storing one of a plurality of said n-bit representations in each pixel position in a third memory; (Each said display represents a window displayed on said display); Fourth memory means including a fourth memory having a plurality of pixel positions corresponding to the pixel positions in the first memory for storing depth information at each pixel position in a fourth memory; The frame information is stored such that the frame information, the n-bit frame display window information, and the depth information for each specific frame occupy the same pixel position in the first, second, third and fourth memories, respectively. Conditionally input into a first memory, conditionally input the n-bit frame indication into the second memory, input the window information into the third memory, and condition the depth information into the fourth memory Input means coupled to said first memory means, said second memory means, said third memory means, and said fourth memory means for inputting therein; First comparing means coupled to said third memory means for comparing a display representing a particular window to be displayed on said display with said display stored at said pixel position in said third memory means; If the indications are not the same and the indications compared by the first comparing means are the same, the frame information is input to the first memory, the n-bit indication is input to the second memory, and the depth information is input to the first memory. Second comparing means coupled to said second memory means for comparing said indication representing said particular frame to be displayed on said display to be input into four memories with said indication stored at said pixel position in said second memory means; And if the stored depth information has a value equal to or greater than the depth information input by the input means, the input means sends the frame information to the corresponding pixel position in the first memory, and displays the display. In the fourth memory when both the indications being compared by the first and second comparing means are stored in the corresponding pixel position in the second memory and in the corresponding pixel position in the fourth memory. And third comparison means coupled to the fourth memory means and the input means for comparing the stored depth information with the depth information input by the input means. 18. The display apparatus according to claim 17, wherein if the display is the same, the display indicating the specific frame to be displayed on the display such that the frame information stored at the corresponding pixel position in the first memory is displayed on the display. And fourth comparing means coupled to said second memory means for comparing with said display stored at said pixel location in memory means. 19. The apparatus according to claim 18, further comprising a register means coupled to said fourth comparing means and said input means for storing background color information, said register means being equal to said indication compared by said fourth comparing means. Otherwise display the background information on the display. 20. The apparatus of claim 19, further comprising erasing means coupled to the second memory means for deleting each successive portion of the second memory after each particular frame is displayed on a display. And at least a pixel position of said second memory for storing an n-bit frame representation of information of said particular frame being displayed. 21. The computer output system of claim 20, further comprising control means for separately enabling one or more of said second memory means, said third memory means and said fourth memory means. 22. The computer output system of claim 21 wherein the frame information comprises an RGB color value. 22. The apparatus of claim 21, wherein the first memory of the first memory means comprises a first pair of all screen bitmap memories, and wherein the second memory of the second memory means is a second pair of all screen bitmap memories. Computer output system comprising a. 24. The apparatus of claim 23, wherein the first memory means further comprises first selecting means for selecting one of the bitmap memories in the first pair of bitmap memories, wherein the second memory means comprises: the second memory means; And a second selection means for selecting one of said bitmap memories in a pair of bitmap memories. 25. The computer output system of claim 24 wherein the first and second selection means each comprise a multiplexer. 27. The computer output system of claim 25, wherein the frame information includes an RGB color value.

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