KR20220159268A - Host device, storage device and electronic device - Google Patents

Abstract

An electronic device according to an embodiment of the present invention comprises: a host device including an application which requests data to be written and a file system which generates a log related to attributes of the data in response to the request of the application and allocates a section corresponding to the data based on the log; and a storage device including a memory device which includes a plurality of memory dies and a memory controller which receives the data and the log of the data from the host device and controls the memory device to sequentially store the data in a physical zone in the memory device corresponding to the section. The memory controller allocates a super block including the physical zone based on the log. The super block can include a plurality of first physical zones each including one or more memory blocks in one memory die according to the log, or a plurality of second physical zones each including a part of each of memory blocks included in different memory dies. According to the present invention, efficient management for each characteristic of data is possible.

Description

HOST DEVICE, STORAGE DEVICE AND ELECTRONIC DEVICE}

The present invention relates to an electronic device, and more particularly, to a host device, a storage device, and an electronic device including the same.

The storage device converts a logical address received from the host device into a physical address, and thus, a logical area within the host device and a physical area of the storage device are related to each other. Accordingly, in order to improve the performance of electronic devices, a new device or method capable of controlling the host device and the storage device in a complementary manner is required.

An embodiment of the present invention provides a host device, a storage device, and an electronic device capable of efficiently managing data by characteristics.

An electronic device according to an embodiment of the present invention generates a log about properties of the data in response to an application requesting to write data and a request of the application, and a section corresponding to the data based on the log. a host device that contains an allocating file system; and receiving the data and the log of the data from a memory device including a plurality of memory dies and the host device, and sequentially storing the data in a physical zone in the memory device corresponding to the section. and a storage device including a memory controller controlling a memory device, wherein the memory controller allocates a super block including the physical zone based on the log, and the super block includes one super block according to the log. It may include a plurality of first physical zones including one or more memory blocks within the memory die or may include a plurality of second physical zones including portions of each of memory blocks included in different memory dies.

A host device according to an embodiment of the present invention includes an application requesting to write data; and a file system that generates a log of attributes of the data in response to a request of the application and allocates a section corresponding to the data based on the log, wherein the file system includes one or more first section groups for determining a section group including the section, and allocating one of empty sections in the section group as a new section regardless of the order of sections in the section group; or one or more second section groups to which new sections are assigned according to the order of sections within the section groups.

A storage device according to an embodiment of the present invention includes a memory device including a plurality of memory dies; and receiving data and a log of the data from an external host, allocating a super block in which data is to be stored in the memory device, and sequentially storing the data in a physical zone included in the super block. and a memory controller controlling the device, wherein the super block includes a plurality of first physical regions including one or more memory blocks in one memory die according to the log, or is included in different memory dies. A plurality of second physical zones including portions of each of the memory blocks may be included.

The present technology provides a host device, a storage device, and an electronic device capable of efficiently managing data by characteristics.

1 is a diagram for explaining an electronic device according to an embodiment of the present invention.
FIG. 2 is a diagram for explaining the memory device of FIG. 1 .
FIG. 3 is a diagram for explaining the memory cell array of FIG. 2 .
4 is a diagram for explaining section allocation in a host device and physical zone allocation in a storage device according to an embodiment of the present invention.
5 is a diagram for explaining the structure of a section allocated by a file system.
6 is a diagram for explaining a process of allocating a new section of a first section group according to an embodiment of the present invention.
7A and 7B are diagrams for explaining a process of allocating a new section of a second section group according to an embodiment of the present invention.
8 is a diagram for explaining a reset process of a first section group according to an embodiment of the present invention.
9 is a diagram for explaining a reset process of a second section group according to an embodiment of the present invention.
10 is a diagram for explaining classification of data according to an embodiment of the present invention.
11 is a diagram for explaining classification of data according to another embodiment of the present invention.
12 is a diagram for explaining memory block management of a storage device according to an embodiment of the present invention.
13 is a diagram for explaining a memory block management process of an electronic device according to an embodiment of the present invention.
14 is a flowchart illustrating a process of determining a sacrificial section for cleaning according to an embodiment of the present invention.
15 is a diagram for explaining a process of allocating a new section to valid data corresponding to logical addresses in a victim section during cleaning according to an embodiment of the present invention.
16 is a diagram illustrating another embodiment of the memory controller of FIG. 1 .
17 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present invention is applied.
18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.
19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

1 is a diagram for explaining an electronic device according to an embodiment of the present invention.

Referring to FIG. 1 , a storage device 50 may include a memory device 100 and a memory controller 200 . The storage device 50 stores data under the control of the host 400, such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. It may be a device that Alternatively, the storage device 50 may be a device that stores data under the control of the host 400 that stores high-capacity data in one place, such as a server or data center.

The storage device 50 may be manufactured as one of various types of storage devices according to a host interface, which is a communication method with the host 400 . For example, the storage device 50 may include a multimedia card in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital in the form of SD, mini-SD, and micro-SD. card, universal serial bus (USB) storage device, universal flash storage (UFS) device, personal computer memory card international association (PCMCIA) card-type storage device, PCI (peripheral component interconnection) card-type storage device, PCI-E ( It may be configured with any one of various types of storage devices such as a PCI express card type storage device, a CF (compact flash) card, a smart media card, a memory stick, and the like.

The storage device 50 may be manufactured in any one of various types of packages. For example, the storage device 50 may include package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer- level fabricated package), wafer-level stack package (WSP), and the like.

The memory device 100 may store data. The memory device 100 operates in response to control of the memory controller 200 . The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells that store data.

The memory cells are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, and triple-level cells storing three data bits. (Triple Level Cell; TLC) or Quad Level Cell (QLC) capable of storing four data bits.

A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100 . A memory block may be a unit for erasing data.

In an embodiment, the memory device 100 may include DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), and RDRAM. (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change RAM (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM) ) and so on. In this specification, for convenience of explanation, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command and an address from the memory controller 200 and access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by a command with respect to an area selected by an address. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the memory device 100 will program data into an area selected by an address. During a read operation, the memory device 100 will read data from an area selected by an address. During the erase operation, the memory device 100 will erase data stored in the area selected by the address.

The memory controller 200 may control overall operations of the storage device 50 .

In an embodiment, the memory controller 200 may receive data and a logical address (LA) from the host 400, and the memory controller 200 includes the logical address LA in the memory device 100. firmware (not shown) capable of converting the stored data into a physical address (PA) indicating the addresses of memory cells to be stored. Also, the memory controller 200 may store a logical-physical address mapping table constituting a mapping relationship between the logical address LA and the physical address PA in the buffer memory.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host 400 . During a program operation, the memory controller 200 may provide a program command, a physical address, and data to the memory device 100 . During a read operation, the memory controller 200 may provide a read command and a physical address to the memory device 100 . During an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100 . Alternatively, the memory controller 200 may open or close a physical zone within the memory device 100 according to a request of the host 400 . Opening the physical area may be generating a map table for logical addresses corresponding to a logical address group corresponding to the physical area, for example, a section allocated to data by a host. Closing the physical area may indicate that there will be no write request for storing data in the corresponding physical area until an open request for the corresponding physical area is received again. The host 400 may provide the request to open or close the physical area as a separate request or together with other requests such as a write request.

In an embodiment, the memory controller 200 may generate commands, addresses, and data on its own and transmit them to the memory device 100 regardless of a request from the host 400 . For example, the memory controller 200 uses commands for performing program operations, read operations, and erase operations involved in performing wear leveling, read reclaim, garbage collection, and the like. , addresses and data may be provided to the memory device 100 .

In an embodiment, the memory controller 200 may include a flash translation layer. The flash translation layer may convert a logical address LA corresponding to a request received from the host 400 into a physical address PA and output the converted physical address to the memory device 100 .

For example, as described above, the flash translation layer converts a logical address (LA) corresponding to a program request into a physical address (PA), or converts a logical address (LA) corresponding to a read request into a physical address (PA). , or a logical address LA corresponding to an erase request may be converted into a physical address PA. The flash translation layer outputs the converted physical address PA to the memory device 100, and the memory device 100 may perform an operation on a page or memory block corresponding to the physical address PA.

In an embodiment, the memory controller 200 may receive logical addresses from the file system 420 and convert the received logical addresses into consecutive physical addresses. When consecutive physical addresses are output to the memory device 100, the memory device 100 may perform consecutive operations corresponding to the consecutive physical addresses. At this time, successive physical addresses may be determined according to the type of assigned physical zone. The types of physical zones will be described in more detail with reference to FIGS. 4, 12 and 13.

In an embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 400 and a buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 400 in a buffer memory and then transmit the data temporarily stored in the buffer memory to the memory device 100 .

In various embodiments, the buffer memory may be used as an operation memory and a cache memory of the memory controller 200 . The buffer memory may store codes or commands executed by the memory controller 200 . Alternatively, the buffer memory may store data processed by the memory controller 200 .

In an embodiment, the buffer memory is DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR) or RDRAM It may be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM) such as (Rambus Dynamic Random Access Memory).

In various embodiments, the buffer memory may be connected externally to the storage device 50 . In this case, volatile memory devices connected to the outside of the storage device 50 may serve as a buffer memory.

In an embodiment, the memory controller 200 may control at least two or more memory devices 100 . In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operating performance. The interleaving method may be a method of controlling operations of at least two or more memory devices 100 to overlap. Alternatively, the interleaving method may be a method of controlling operations of a plurality of groups classified in one memory device 100 to be overlapped. In this case, the group may be a unit of one or more memory dies or a unit of one or more memory planes.

The host 400 is USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe ( PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM ), LRDIMM (Load Reduced DIMM), etc., may communicate with the storage device 50 using at least one of various communication methods.

In an embodiment, the host 400 may include an application 410 . The application 410 is also referred to as an application program and may be software executed on an operating system (OS). The application 410 may process data in response to user input. For example, the application 410 may process data in response to a user's input and transfer a request to store the processed data in the memory device 100 of the storage device 50 to the file system 420 . .

The file system 420 may allocate a logical address (LA) where data is stored in response to a request transmitted from an application. In an embodiment, the file system 420 may be a log structure file system (LFS). The log structured file system (LFS) may create a log in consideration of attributes of input data, and allocate a section corresponding to the data based on the log. At this time, the section may be a set of logical addresses. Therefore, allocation of a section may mean that logical addresses corresponding to corresponding data are allocated. Data to which sections are allocated may be sequentially stored in storage areas of the memory device 100 corresponding to the sections. For example, the log structured file system (LFS) may be a flash friendly file system (F2FS). A flash-friendly file system (F2FS) is a log-based file system designed in consideration of the characteristics of a Solid State Drive (SSD), and can increase parallelism within the SSD by using a multi-head log. Data generated in different logs can be assigned different sections. The log structure file system (LFS) cannot overwrite data. When data is modified, the log structure file system (LFS) allocates a new logical address corresponding to the data to be modified and writes the data to a physical area corresponding to the new logical address.

Data requested to be written by the application 410 may be stored in a host memory (not shown) in the host, and may be flushed to the storage device 50 according to a request from the application through a device interface (not shown). can The host memory may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

FIG. 2 is a diagram for explaining the memory device of FIG. 1 .

Referring to FIG. 2 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input/output circuit 140 and a control logic 150 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKi. The plurality of memory blocks BLK1 to BLKi are connected to the address decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKi may be connected to the input/output circuit 140 through column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL may include bit lines.

In an embodiment, the memory cell array 110 may include one or more memory dies, and each memory die may include one or more planes including one or more memory blocks.

Also, the plurality of memory blocks BLK included in the memory cell array 110 may be grouped into two or more super blocks (SBs). The super block SB may be a unit in which the control logic 150 manages a plurality of memory blocks BLK included in the memory cell array 110 . One super block (SB) is a set of memory blocks (BLK) in which a read operation and/or a write operation are performed simultaneously or at the same time, or a read operation and/or a write operation are linked or related, or one A set of memory blocks BLK in which a read operation and/or a write operation are performed in response to a command of , or memory blocks in which a read operation and/or a write operation are performed in conjunction with or simultaneously in the memory cell array 110 ( BLK). In addition, among several memory blocks BLK, a group of memory blocks BLK that are distinguished from each other in terms of management or operation may be referred to as a super block SB. Each of the two or more super blocks SB may have the same size. That is, the number of memory blocks BLK included in each of two or more super blocks SB may be the same. Alternatively, at least one of the two or more super blocks SB may have a different size from the rest. That is, the number of memory blocks BLK included in at least one super block SB among the plurality of super blocks SB may be different from the number of memory blocks BLK included in the other super blocks SB. have. Also, two or more memory blocks BLK included in each of the two or more super blocks SB may be located on the same memory die. Alternatively, the two or more memory blocks BLK included in each of the two or more super blocks SB may be located on two or more different memory dies.

Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line may be defined as one physical page. That is, the memory cell array 110 may include a plurality of physical pages. The memory cells of the memory device 100 include a single level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, and three data bits. It may be configured as a triple level cell (TLC) that stores . or a quad level cell (QLC) that can store four data bits.

In an embodiment, the voltage generator 120, the address decoder 130, and the input/output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 under the control of the control logic 150 . A peripheral circuit may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

The voltage generator 120 is configured to generate a plurality of operating voltages using an external power supply voltage supplied to the memory device 100 . The voltage generator 120 operates in response to control of the control logic 150 .

As an example embodiment, the voltage generator 120 may generate an internal power voltage by regulating an external power voltage. The internal power supply voltage generated by the voltage generator 120 is used as an operating voltage of the memory device 100 .

As an embodiment, the voltage generator 120 may generate a plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may be configured to generate various voltages required by the memory device 100 . For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

The voltage generator 120 includes a plurality of pumping capacitors receiving an internal power supply voltage in order to generate a plurality of operating voltages having various voltage levels, and generates a plurality of pumping capacitors in response to the control of the control logic 150. It will selectively activate to generate a plurality of operating voltages.

The generated operating voltages may be supplied to the memory cell array 110 by the address decoder 130 .

The address decoder 130 is connected to the memory cell array 110 through row lines RL. The address decoder 130 is configured to operate in response to control of the control logic 150 . The address decoder 130 may receive the address ADDR from the control logic 150 . The address decoder 130 may decode a block address among the received addresses ADDR. The address decoder 130 selects at least one memory block among the memory blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 may decode a row address among the received addresses ADDR. The address decoder 130 may select at least one word line among word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder 130 may decode a column address among the received addresses ADDR. The address decoder 130 may connect the input/output circuit 140 and the memory cell array 110 according to the decoded column address.

Illustratively, the address decoder 130 may include components such as a row decoder, a column decoder, and an address buffer.

The input/output circuit 140 may include a plurality of page buffers. A plurality of page buffers may be connected to the memory cell array 110 through bit lines. During a program operation, data may be stored in memory cells selected according to data stored in a plurality of page buffers.

During a read operation, data stored in selected memory cells may be sensed through bit lines, and the sensed data may be stored in page buffers.

The control logic 150 may control the address decoder 130 , the voltage generator 120 and the input/output circuit 140 . The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control peripheral circuits by generating control signals in response to the command CMD and the address ADDR.

FIG. 3 is a diagram for explaining the memory cell array of FIG. 2 .

Referring to FIG. 3 , the memory cell array 110 may include one or more memory dies, and each memory die may include one or more planes including one or more memory blocks. . Although the memory cell array 110 is illustrated in FIG. 3 as including four memory dies (DIE#0, DIE#1, DIE#2, and DIE#3), the number of memory dies is not limited thereto. The plurality of memory dies may transmit/receive data to and from the memory controller through a plurality of channels, and each channel may be connected to one or more memory dies. For example, if one channel is connected to one memory die, one memory die can receive one command at a time, and the planes included in one memory die transmit the commands received by the memory die in parallel. can be dealt with

4 is a diagram for explaining section allocation in a host device and physical zone allocation in a storage device according to an embodiment of the present invention.

Referring to FIG. 4 , the file system 420 of the host device generates a log of attributes of the data in response to a request from the application 410 requesting to write data, and based on the log, a log corresponding to the data is generated. section can be assigned. A section may be a group of a plurality of logical addresses, and allocating a section corresponding to data may mean allocating some or all of the plurality of logical addresses included in the section to corresponding data. In one embodiment, a plurality of logical addresses corresponding to one section may be consecutive logical addresses. Alternatively, a plurality of logical addresses corresponding to one section may not be contiguous, but information on logical addresses included in each section may be stored in a memory in a host or a memory on a storage device, and the logical addresses in each section may be managed. . Also, the file system 420 may determine a section group including a section based on a log allocated to data. A section group may include a plurality of sections, and logical addresses included in sections in one section group may be consecutive. Alternatively, logical addresses included in sections within one section group may not be contiguous, but information on logical addresses included in each section group is stored in a memory in a host or a memory on a storage device to obtain a logical address for each section group. can manage In one embodiment, the section group includes a first section group in which the file system allocates any one of empty sections in the section group as a new section regardless of the order of sections in the section group, and the file system allocates a new section according to the order of sections in the section group. A second section group for allocating sections may be included.

In addition, the host 400 may provide logs and section-allocated data by the file system 420 to the storage device 50 . In one example, data may be provided to the storage device 50 by a device interface (not shown) in the host 400 . The file system 420 may manage the memory device 100 in the storage device 50 by dividing it into a plurality of areas. In one embodiment, the file system 420 stores the storage space in the memory device 100 as a check point area, a segment information table (SIT), and a node address table (NAT). ), a segment summary area (SSA), and a main area. The checkpoint area may store checkpoints. A checkpoint is data that preserves a state up to a logical breakpoint of the system when a system interruption event such as sudden power off occurs during operation of the computing system, and the checkpoint can be used to recover the data. The segment information table (SIT) may include valid page information within each segment. The node address table (NAT) may include identifiers for each node constituting the indexing tree of a file stored in the memory device 100 and a physical address corresponding to each node identifier. The segment summary area SSA may include summary information of each segment of the main area, which will be described later. The main area may be a space for storing various directory information, data, file information, and the like actually used by users. In this specification, all data and information stored in the main area are comprehensively defined as data. At this time, the data stored in the main area may be classified into nodes or data according to its type. A node may mean an inode or an index, and data may mean a directory or user file data. In addition, stored data may be classified according to temperature, and the temperature of each data may be classified into hot, warm, and cold. Accordingly, the data may be classified into hot nodes, warm nodes, cold nodes, hot data, warm data, cold data, etc. by the file system 420, logs may be allocated, and then stored in the main area. Accordingly, the main area may be divided into virtual areas corresponding to sections allocated by the file system 420, and a specific log may be allocated to each of the virtual areas. Also, these virtual zones may be grouped and divided into virtual zone groups corresponding to the section groups determined by the file system 420 . Also, each of the virtual zones may include a plurality of segments, and data may be sequentially stored in each segment. In this case, one segment may correspond to one or more logical addresses. These virtual zones are physically implemented in a host memory (not shown) in a host or a buffer memory device (not shown) of a storage device, or information about logical addresses included by sections and section groups is stored in a host memory or buffer memory device. It can be logically implemented by managing in

The storage device 50 may include a memory controller 200 and the memory device 100 , and the memory controller 200 may include a zone manager 210 and a flash conversion layer 220 .

The memory controller 200 may receive data from the host 400 . The data may be data allocated to logs and sections by the file system 420 . The zone management unit 210 may allocate a super block in which data is stored based on the log of the received data. A super block includes a plurality of physical zones, and the shape of the physical zones included in the super block is different depending on the type of super block, so assigning a super block determines the shape of the physical zone in which data is stored. it could be That is, a first physical zone including one or more memory blocks in one memory die and a second physical zone including a portion of each of memory blocks included in different memory dies may be determined in which physical zone should be included. have. In this case, a super block including a plurality of first physical zones may be referred to as a first super block, and a super block including a plurality of second physical zones may be referred to as a second super block. In this case, the data stored in the first super block may be data to which sections in the first section group are allocated by the file system 420, and data stored in the second super block are allocated to sections in the second section group. may be data.

The zone management unit 210 may provide the flash conversion layer 220 with information on the type of physical zone in which data is to be stored, and the flash conversion layer 220 converts the logical address of the data to which the section is allocated to the physical address based on this information. can be converted to In one embodiment, logical addresses included in the section may be assigned to the data allocated to the section, and the flash translation layer 220 assigns the logical address of the data to be stored consecutively within the physical area determined by the area management unit 210. can be converted to a physical address.

The flash conversion layer 220 may transmit the converted physical address to the zone manager 210, and the zone manager 210 may control the memory device 100 to store data at the received physical address.

5 is a diagram for explaining the structure of a section allocated by a file system.

Referring to FIG. 5 , a section may include a plurality of logical addresses. Logical addresses included in one section may be contiguous addresses or non-contiguous addresses. Allocating a section to data may mean allocating a logical address within the section. Information on addresses included in each section may be included in a memory in a host or a memory in a storage device. Logical addresses may be sequentially allocated according to the size of write-requested data. For example, if there is a write request for data D1 and D2 of a specific size, and the section of FIG. 5 is allocated to both data D1 and D2, logical addresses LA1 to LA3 may be allocated for D1, and D2 Logical addresses of LA4 and LA5 may be allocated for .

6 is a diagram for explaining a process of allocating a new section of a first section group according to an embodiment of the present invention.

Referring to FIG. 6 , a section group to which a new section can be allocated may be defined as a first section group 421a regardless of the order of sections within the section group. In this case, the logical addresses included in the sections in the section group may be consecutive to each other, and the logical addresses may increase as the number of sections in the section group increases. Accordingly, the section order may mean the order of section numbers in a section group, which may mean the order in the direction of increasing logical addresses. Alternatively, logical addresses included in sections in a section group may not be consecutive to each other. In this case, the section order may be determined based on information about sections stored in a separate memory and logical addresses included in each section group. In the case of the first section group 421a, since the sections are allocated and logical addresses can be assigned regardless of the section order, the third section (Section#3) is assigned first and all logical addresses in the third section are assigned. After becoming a full section, a first section (Section#1) may be allocated and a logical address for new data may be assigned. When all the logical addresses of the first section, which is an open section, are assigned to data and the first section becomes a full section, the file system 420 creates an empty section, section 0 (Section#0). Alternatively, any one of the second sections (Section#2) may be allocated as a new section and a logical address included therein may be assigned to data.

7A and 7B are diagrams for explaining a process of allocating a new section of a second section group according to an embodiment of the present invention.

Referring to FIGS. 7A and 7B , a section group to which new sections can be allocated according to the order of sections within the section group may be defined as a second section group 421b. As shown in FIG. 7A, in the second section group, the 0th section (Section#0) is opened first and logical addresses included therein are given to data. The first section (Section#1) may be allocated as a new section to store data. If all the sections in the second section group 421b are full sections as shown in FIG. 7B, the file system 420 allocates a new second section group 421b, and then the first section in the new second section group The 0th section (Section#0) may be allocated as a new section, and a logical address included therein may be assigned to data. At this time, in the case of the second section group 421b, sections are allocated according to the order of sections within the section group. If the last section, the third section (Section#3), is a full section, among the previous sections, empty sections (Empty Section) cannot exist. Therefore, in the case of the second section group 421b, there is no need to find an empty section in the section group, and if the next section in the second section group 421b does not exist, the file system 420 starts a new second section. The group 421b is assigned.

8 is a diagram for explaining a reset process of a first section group according to an embodiment of the present invention.

Referring to FIG. 8 , in the first section group 421a, 1) when the 0th section (Section#0) is reset, 2) by discarding all data corresponding to logical addresses in the 0th section. , the 0th section becomes an empty section and the reset operation is completed. In addition, 3) when resetting the first section (Section#1), 4) by discarding all data corresponding to logical addresses in the first section, the first section becomes an empty section. The reset operation is complete. In addition, 5) when the second section (Section#2) is reset, 6) by discarding all data corresponding to logical addresses in the second section, the second section becomes an empty section. The reset operation is complete. That is, when a reset operation is performed on one section included in the first section group 421a, in response to this, data corresponding to logical addresses in the corresponding section are discarded, and the corresponding section is immediately empty ( empty) section, and thus the reset operation can be completed. At this time, discarding the data corresponding to the logical addresses may mean releasing the mapping relationship between the logical addresses and the data. The reset operation is performed when all data corresponding to logical addresses in a specific section are invalid. If there is valid data, it is mapped to a logical address in another section, and the data corresponding to the corresponding logical address is invalid. ) After processing, a reset operation may be performed. Logical addresses included in the reset-completed section may be assigned again for new data. This reset operation may be performed by a file system.

9 is a diagram for explaining a reset process of a second section group according to an embodiment of the present invention.

4 and 9, in the second section group 421b, 1) when the 0th section (Section#0) is reset, 2) data corresponding to logical addresses in the 0th section are not immediately discarded. and information indicating that the 0th section is ready to reset is stored in the bitmap. In addition, 3) when the first section (Section#1) is reset, 4) data corresponding to logical addresses in the first section are not immediately discarded, indicating that the first section is preparing for reset (Ready to Reset). Information is stored in a bitmap. In addition, 5) when the second section (Section#2) is reset, 6) data corresponding to logical addresses in the second section are not immediately discarded, indicating that the second section is preparing for reset (Ready to Reset). Information is stored in a bitmap. In addition, 7) when the third section (Section#3) is reset, 8) data corresponding to logical addresses in the third section are not discarded as waves, indicating that the third section is preparing for reset (Ready to Reset). Information is stored in a bitmap. 9) Accordingly, when information indicating that resetting is being prepared for all sections of the second section group 421b is stored in the bitmap, all data corresponding to all logical addresses in all sections are discarded, All sections in the second section group 421b become empty sections at once, so that the reset operation can be completed. That is, in the case of the second section group 421b, when only some of the sections are reset, data is not immediately discarded and the section does not become an empty section, and all sections in the second section group 421b are reset. After an operation is performed, that is, after information indicating that resetting is being prepared for all sections is stored, data corresponding to logical addresses of all sections included in the second section group 421b are discarded, thereby discarding the second section group 421b. ) can be empty at the same time. When the reset operation is completed, information indicating that resetting is being prepared may be deleted for all sections in the second section group 421b. At this time, a bitmap storing information indicating that resetting is being prepared may be included in an arbitrary location in the storage device. At this time, discarding the data corresponding to the logical addresses may mean releasing the mapping relationship between the logical addresses and the data. The reset operation is performed when all data corresponding to logical addresses in a specific section are invalid. If there is valid data, it is mapped to a logical address in another section, and the data corresponding to the corresponding logical address is invalid. ) After processing, a reset operation may be performed. Logical addresses included in the reset-completed section may be assigned again for new data. This reset operation may be performed by a file system.

10 is a diagram for explaining classification of data according to an embodiment of the present invention.

In an embodiment, data requested to be written by an application may be classified into nodes or data according to its type, and may be classified into hot, warm, and cold according to temperature. Accordingly, the file system 420 may generate logs such as hot node, warm node, cold node, hot data, warm data, and cold data according to data attributes. For example, a hot node can be an inode or direct node block for a directory, so a hot node is overwritten or updated very frequently and is not subject to garbage collection. It can also be data with high probability. A warm node may be an inode or direct node block for a regular file, and thus, a warm node may be data that is overwritten or updated frequently and has a considerable probability of being subject to garbage collection. A cold node may be an indirect node block, and therefore, a cold node may be data that has a low overwrite and update frequency, but is highly likely to be subject to garbage collection. Hot data can be a directory entry block, quota, or relatively small file data of 64 KB or less. Therefore, hot data is overwritten or updated more frequently than other data, and is not subject to garbage collection. It may be data with a high probability of being a target. The worm data may be a data block created by a user, and may be, for example, file data with a relatively large capacity of 64 KB or more. Therefore, the worm data is data with a relatively high update frequency but a relatively low probability of being subject to garbage collection. can be Cold data is data moved by cleaning or garbage collection, data blocks classified as cold data by users, or file data having a specific format (eg, .db, .jpg, etc.), for example. For example, it may be multimedia file data, and therefore, cold data may be data that has a low overwrite frequency and a relatively low probability of being subject to garbage collection. However, the classification of such data is not limited to this method, and may be modified in a method having various criteria including the method in FIG. 11 below. In this specification, the cleaning of the file system allocates another section for valid data corresponding to the logical address in the victim section in order to secure an empty section from the host's point of view, and then the logical addresses in the victim section It means releasing the relationship between the data and the data corresponding thereto, and garbage collection is a victim physical area of a memory device to secure an empty physical area or an empty memory block from the point of view of a storage device. It may refer to moving valid data among data stored in a zone to another physical zone and then erasing the corresponding physical zone. That is, cleaning and garbage collection may mean the same operation as a result.

Referring to FIG. 10 , sections included in a first section group may be allocated to hot nodes, warm nodes, cold nodes, and hot data, and sections included in a second section group may be allocated to warm data and cold data. At this time, the hot node, warm node, cold node, and hot data to which the first section included in the first section group is allocated are the first type data, and the warm data to which the second section included in the second section group is allocated, and Cold data may be defined as the second type of data. However, the classification of each data included in the first section group and the second section group is not limited to that shown in FIG. 10, and data may be classified in various ways according to settings. Preferably, the data of the first type may have a relatively small capacity or may be data with a high possibility of being updated or overwritten. Also, the second type data may have a relatively large capacity or data that is unlikely to be updated or overwritten. Accordingly, the second type data may be data that is relatively more affected by input/output performance than the first type data. In this case, the data classified as the first type data may be allocated to sections within one first section group regardless of specific attributes thereof. Alternatively, even for the same first type of data, if attributes such as data type (node or data) or temperature (hot, warm, cold) are different, sections in a plurality of different first section groups may be allocated accordingly. have. Similarly, data classified as the second type data may be allocated to sections within one second section group regardless of specific attributes thereof. Alternatively, even for the same second type data, if attributes such as data type (node or data) or temperature (hot, warm, cold) are different, sections in a plurality of different second section groups may be allocated accordingly. have.

11 is a diagram for explaining classification of data according to another embodiment of the present invention.

Referring to FIG. 11 , data may be classified according to a classification criterion different from that of FIG. 10 . In the case of FIG. 11 , data is classified into hot node, warm node, hot data, warm data, and cold data. Hot nodes can include inodes for directories, inodes for files, and direct nodes. Warm nodes can include indirect nodes, directory entry blocks, and quotas. In addition, hot data may include small-sized file data, warm data may include medium-sized file data, and cold data may include large-sized file data or file data of any size having a specific format. That is, the classification of data presented in FIG. 11 is based on the type of data, size of data, frequency of data occurrence, frequency of overwrite, etc. so that it can be more suitable for dividing and managing section groups and super blocks. may have been reclassified. The hot nodes, warm nodes, and hot data classified accordingly are classified as first type data and assigned sections in the first section group, and warm data and cold data are classified as second type data and sections in the second section group can be assigned However, the data classification criterion is not limited to the contents described with respect to FIG. 10 and the contents shown in FIG. 11 .

12 is a diagram for explaining memory block management of a storage device according to an embodiment of the present invention.

Referring to FIGS. 3, 4, and 12 , the memory cell array 110 may include a plurality of memory dies, for example, four memory dies (DIE#0 to DIE#3). have. Also, each memory die may include a plurality of planes each including a plurality of memory blocks, and may include, for example, four planes (PLANE#0 to PLANE#3). The zone management unit 210 classifies and manages a plurality of memory blocks in the memory cell array as super blocks. A super block may include one or more physical zones. A super block may be formed across a plurality of memory dies, eg, as shown in FIG. 12 , a super block may be formed across all memory dies. The super block may be classified into a first super block 111a and a second super block 111b according to the shape of the included physical zone.

The first physical zone 112a included in the first super block 111a may include one or more blocks in one memory die. For example, as shown in FIG. 12 , an area including one memory block included in plane 0 to plane 3 for each memory die may be designated as one physical area. Four first physical zones 112a, one formed for each die, may be included.

The second physical zone 112b included in the second super block 111b may include portions of blocks included in different memory dies. For example, as shown in FIG. 12 , the second physical zone 112b is formed throughout the four memory dies (DIE#0 to DIE#3), but only a part of each of the memory blocks included in each plane. can include For example, as shown in FIG. 12 , only 1/4 of the pages of each memory block included in each plane may be included. Accordingly, the second super block 111b may include four second physical regions 112b formed over the entire memory die and including only some pages of each memory block.

In an embodiment, the first super block 111a and the second super block 111b may have the same size. That is, the first super block 111a and the second super block 111b may include the same number of memory blocks. Also, the size of the first physical zone 112a and the second physical zone 112b may be the same. That is, the number of pages included in the first physical zone 112a and the second physical zone 112b may be the same. While the first physical zone 112a is formed within one memory die, the second physical zone 112b may be formed across multiple memory dies. Accordingly, in the case of the second physical zone 112b, it is possible to operate in a die interleaving manner. In particular, as shown in FIG. 12, when the second physical zone 112b is formed over the entire memory die, a full-die It is possible to operate in an interleaved manner. However, it is not possible to simultaneously allocate and program different second physical zones 112b. In addition, since the second physical zone includes only a part of each of the memory blocks, when a specific physical zone is to be erased, it cannot be erased immediately, and all pages of each of the memory blocks partially included in the corresponding physical zone are erased. is possible, that is, when the entire physical area of the super block including the corresponding physical area can be erased, the corresponding physical area can be erased. Therefore, in the case of the second physical zone, there is an advantage that it is possible to operate in an interleaved manner in units of memory dies, but considering limitations in programming and erasing, it may not be suitable for storing data with high input/output frequency. Therefore, by using both the first super block and the second super block, data having a relatively small capacity or high input/output frequency is stored in the first physical zone in the first super block, and the second physical zone in the second super block By storing data with a relatively large capacity or low input/output frequency in the zone, performance improvement of the electronic device can be expected.

13 is a diagram for explaining a memory block management process of an electronic device according to an embodiment of the present invention.

4, 12, and 13 , the file system 420 of the host 400 generates a log based on attributes of the data for data requested to be written by the application 410, and based on this log data to determine the section group that contains the section to be allocated for data. According to various criteria, data is first type data to which the first section 422a of the first section group 421a is assigned and second type data to which the second section 422b of the second section group 421b is assigned. can be distinguished by Data allocated to the first section 422a in the first section group 421a by the file system is stored in the first physical area in the first super block 111a of the memory device 100 under the control of the memory controller 200. Data stored in 112a and allocated to the second section 422b in the second section group 421b will be stored in the second physical zone 112b in the second super block 111b of the memory device 100. can The first section group 421a corresponds to the first super block 111a, and thus the first section 422a corresponds to the first physical zone 112a. The characteristics of the first section 422a to which new sections can be allocated regardless of the order of sections in the section group match the characteristics of the first physical zone 112a managed for each memory die, and the first section and the first section 422a Both physical zones have the same characteristics that a reset or erase operation can be performed in units of one section or physical zone. In addition, the characteristics of the second section 422b for allocating new sections according to the section order within the section group match the characteristics of the second physical zone 112b formed over a plurality of memory dies, and the second section and the second section 422b All physical zones cannot be reset or erased in units of one section or physical zone, and after the second section group and the second super block to which each belongs are reset or erased, the unit of the section group and super block The characteristics of performing a reset or erase operation are consistent with .

The first sections 422a in the first section group 421a are allocated regardless of the section order, and the zone management unit 210 responds to a physical zone allocation request from the host 400 in which section-allocated data is to be stored. may allocate a first physical zone 112a formed as an area within one memory die. The second sections 422b in the second section group 421b are allocated according to the section order, and in response to a physical zone allocation request from the host 400 in which section-allocated data is to be stored, the zone management unit 210 A second physical zone 112b formed of an area including some of memory blocks in a plurality of memory dies may be allocated. In response to the physical zone allocation request of the host 400, when the zone management unit 210 returns information indicating that there is no additionally allocable physical zone in the super block currently in use, the file system 420 allocates a new section group and then , Sections within the new section group may be allocated, and in response to this, the zone management unit 210 may allocate a new super block and a new physical zone included therein, and then store data to which the new section is allocated. Alternatively, the file system 420 may allocate a new section group and sections included therein without receiving information on the super block and the physical zone from the zone management unit 210 as a reply.

14 is a flowchart illustrating a process of determining a sacrificial section for cleaning according to an embodiment of the present invention.

Referring to FIGS. 4 and 14 , costs of candidate sections may be calculated in step S1401. The cost at this time may be calculated in a manner conventionally used for selecting the sacrificial section. For example, it may be performed in a greedy manner or a cost-benefit manner. The greedy method is a method of selecting a section having the smallest number of valid blocks as a victim section by setting a cost that is smaller as the number of valid blocks corresponding to the logical addresses included in the section is the smallest. The cost-benefit method sets the cost value by considering both the modification time of data corresponding to the logical addresses in each section and the number of valid blocks corresponding to the logical addresses in the section. As the number of effective blocks in a section decreases, a lower cost is assigned, and such a section may be selected as a victim section. In one embodiment, the cost of the sacrificial section may be calculated in a greedy manner in the case of foreground cleaning and in a cost-benefit manner in the case of background cleaning.

In step S1403, the section type of the cost-calculated candidate section can be checked. That is, it may be determined whether the corresponding section is a first section belonging to the first section group or a second section belonging to the second section group.

In step S1405, when it is determined that the second section is not, that is, when it is determined that it is the first section, the cost calculated in step S1401 may be maintained without change as in step S1411. On the other hand, when it is determined that the second section is the second section in step S1405, the cost may be corrected based on the number of sections in which reset preparation (“Ready to Reset”) information is stored, as in steps S1407 and S1409. A state in which a reset operation is not completed because a reset operation is intended to be performed on a specific section belonging to the second section group, but another section that is not ready to perform the reset operation exists in the corresponding section group can be defined as a reset preparation state. have. At this time, the section in preparation for resetting state may store information indicating this in a separate bitmap. In step S1407, the number of all sections being prepared for reset among all sections allocated by the file system 420 may be considered. For example, when the number of sections being prepared for reset among all sections exceeds a threshold, the probability that a candidate section included in the second section group is selected as a victim section may be increased by lowering the cost, and the threshold is not exceeded. If you can't, you can keep the cost. Alternatively, different weights may be assigned according to the number of sections being prepared for reset among all sections. Alternatively, when the number of sections being prepared for reset among all sections exceeds the threshold value, the number of sections being prepared for reset in the second section group to which the corresponding section belongs may be checked in step S1409. If the number of sections being prepared for reset among all sections does not exceed the threshold value, step S1409 may not be performed. In step S1409, if the number of sections being prepared for reset in the second section group to which the corresponding section belongs exceeds the threshold value, the probability that the corresponding section is selected as a victim section may be increased by lowering the cost, and if the cost does not exceed the threshold value, the cost may be reduced. can keep Alternatively, different weights may be assigned according to the number of sections being prepared for reset in the second section group. At this time, both steps S1407 and S1409 may be performed, or only one of them may be performed.

After calculating and correcting the cost, a final cost value may be compared in step S1413 and a sacrifice section for cleaning the sections may be determined.

In one embodiment, when cleaning is performed, a next cleaning time may be adjusted in consideration of a ratio of logical addresses corresponding to invalid data among logical addresses included in all sections. At this time, in the case of the second section group, since the logical addresses included in the sections being prepared for reset are not logical addresses that can be assigned to new data, the data corresponding to the logical addresses in the section being prepared for reset are invalid data. You can adjust the timing of the next cleaning by handling it.

15 is a diagram for explaining a process of allocating a new section to valid data corresponding to logical addresses in a victim section during cleaning according to an embodiment of the present invention.

Referring to FIG. 15 , when a victim section is selected through the same process as in FIG. 14 , a new section may be allocated to valid data corresponding to logical addresses in the victim section. In this case, the section to which the valid data is newly allocated may be a section included in a section group of the same type as the section group including the previously allocated section. For example, data classified as the first type data and allocated to the first section in the first section group, such as hot node, warm node, cold node, and hot data in FIG. will move to If the first section to be allocated in the first section group does not exist, after allocating a new first section group, any one section included in the first section group may be allocated to valid data corresponding to logical addresses in the victim section. have. In addition, data classified as the second type data and allocated to the second section in the second section group, such as warm data and cold data in FIG. 15, are moved to the second section in the second section group. If there is no second section to be allocated in the second section group, after allocating a new second section group, any one section included in the second section group may be allocated to valid data corresponding to logical addresses in the victim section. have.

16 is a diagram illustrating another embodiment of the memory controller of FIG. 1 .

Referring to FIG. 16 , a memory controller 1000 includes a processor 1010, an internal memory 1020, an error correction code circuit 1030, a host interface 1040, A buffer memory interface (Buffer Memory Interface) 1050 and a memory interface (Memory Interface; 1060) may be included.

The processor 1010 may perform various operations for controlling the memory device 100 or generate various commands. Upon receiving a request from the host 400, the processor 1010 may generate a command according to the received request and transmit the generated command to a queue controller (not shown). In response to a physical zone allocation request from the host 400, the processor 1010 may allocate a super block in a memory device in which data received from the host is to be stored and a physical zone included in the super block. You can manage physical zones.

The internal memory 1020 may store various pieces of information necessary for the operation of the memory controller 1000 . For example, internal memory 1020 may include logical and physical address map tables. The internal memory 1020 may include at least one of random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), cache, and tightly coupled memory (TCM). .

The error correction code circuit 1030 is configured to detect and correct an error in data received from the memory device 100 using an error correction code (ECC). The processor 1010 may adjust a read voltage according to an error detection result of the error correction code circuit 1030 and control the memory device 100 to perform re-reading. As an exemplary embodiment, the error correction block may be provided as a component of the memory controller 1000 .

The host interface 1040 may exchange commands, addresses, and data between the memory controller 1000 and the host 400 . For example, the host interface 1040 may receive a request, address, data, etc. from the host 400 and output data read from the memory device 100 to the host 400 . The host interface 1040 includes USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics) protocols may be used to communicate with the host 400 . The host interface 1040 may receive a request to allocate a physical zone corresponding to a section allocated for data by the host 400 .

The buffer memory interface 1050 may transmit data between the processor 1010 and the buffer memory. The buffer memory may be used as an operation memory or cache memory of the memory controller 1000 and may store data used in the storage device 50 . The buffer memory interface 1050 by the processor 1010 may use the buffer memory as a read buffer, a write buffer, a map buffer, and the like. Depending on the embodiment, the buffer memory is DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), or It may include Rambus Dynamic Random Access Memory (RDRAM). When the buffer memory is included in the memory controller 1000, the buffer memory interface 1050 may be omitted.

The memory interface 1060 may exchange commands, addresses, and data between the memory controller 1000 and the memory device 100 . For example, the memory interface 1060 may transmit commands, addresses, and data to the memory device 100 through a channel and may receive data from the memory device 100 . The memory interface 1060 may transmit/receive commands, addresses, data, etc. to or from the memory device 100 based on super blocks and physical areas allocated and managed by the processor 1010 .

17 is a block diagram showing a memory card system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 17 , a memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

The memory controller 2100 is connected to the memory device 2200 . The memory controller 2100 is configured to access the memory device 2200 . For example, the memory controller 2100 may be configured to control read, program, erase, and background operations of the memory device 2200 . The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200 . The memory controller 2100 may be implemented identically to the memory controller 200 described with reference to FIG. 1 . For example, the memory controller 2100 may allocate a physical area and a super block including the physical area within the memory device 2200 and control the memory device 2200 in units of the physical area and the super block.

Illustratively, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. can

The memory controller 2100 may communicate with an external device through the connector 2300 . The memory controller 2100 may communicate with an external device (eg, a host) according to a specific communication standard. For example, the memory controller 2100 may include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), and advanced technology attachment (ATA). ), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, It is configured to communicate with an external device through at least one of various communication standards such as NVMe. Illustratively, the connector 2300 may be defined by at least one of the above-described various communication standards.

For example, the memory device 2200 may include electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and STT-MRAM. (Spin Transfer Torque Magnetic RAM) and the like.

The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 are integrated into a single semiconductor device such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), or a smart media card (SM, SMC). ), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), and universal flash memory (UFS).

18 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 18 , an SSD system 3000 includes a host 3100 and an SSD 3200 . The SSD 3200 exchanges signals with the host 3100 through the signal connector 3001 and receives power through the power connector 3002 . The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment of the present invention, the SSD controller 3210 may perform the function of the memory controller 200 described with reference to FIG. 1 .

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100 . The SSD controller 3210 may control the plurality of flash memories through a plurality of channels CH1 to CHn. One or more memory dies may be connected to each channel. For example, the signals may be signals based on an interface between the host 3100 and the SSD 3200 . For example, signals include Universal Serial Bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), Advanced Technology Attachment (ATA), Serial- Interfaces such as ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. It may be a signal defined by at least one of

The auxiliary power supply 3230 is connected to the host 3100 through a power connector 3002 . The auxiliary power supply 3230 can receive power from the host 3100 and charge it. The auxiliary power supply 3230 may provide power to the SSD 3200 when power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200 . For example, the auxiliary power supply 3230 is located on the main board and may provide auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 temporarily stores data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or metadata (metadata) of the flash memories 3221 to 322n. For example, a mapping table) may be temporarily stored. The buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

19 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 19 , a user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, or a file system. Illustratively, the application processor 4100 may include controllers, interfaces, graphic engines, and the like that control components included in the user system 4000 . The application processor 4100 may be provided as a System-on-Chip (SoC). The application processor 4100 may generate a log for data requested by a user to write, allocate section groups and sections based on the logs, and provide data to which the sections are allocated to the storage module 4400 .

The memory module 4200 may operate as a main memory, working memory, buffer memory, or cache memory of the user system 4000 . The memory module 4200 includes volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, and the like. can do. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as a single semiconductor package.

The network module 4300 may communicate with external devices. Illustratively, the network module 4300 may include code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), and long term evolution (LTE). ), wireless communication such as Wimax, WLAN, UWB, Bluetooth, Wi-Fi, etc. may be supported. For example, the network module 4300 may be included in the application processor 4100 .

The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100 . Alternatively, the storage module 4400 may transmit data stored in the storage module 4400 to the application processor 4100 . For example, the storage module 4400 is a non-volatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, a 3D NAND flash, and the like. can be implemented For example, the storage module 4400 may be provided as a removable storage medium such as a memory card or an external drive of the user system 4000 .

For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate in the same way as the memory device 100 described with reference to FIG. 1 . The storage module 4400 may operate in the same way as the storage device 50 described with reference to FIG. 1 .

The user interface 4500 may include interfaces for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, and the like. have. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

50: storage device
100: memory device
200: memory controller
400: host

Claims (20)

a host device including an application requesting to write data and a file system that generates a log of properties of the data in response to the request of the application and allocates a section corresponding to the data based on the log; and
Receive the data and the log of the data from a memory device including a plurality of memory dies and the host device, and sequentially store the data in a physical zone in the memory device corresponding to the section. A storage device including a memory controller for controlling the device; includes,
The memory controller,
Allocating a super block including the physical zone based on the log;
The super block,
According to the log, a plurality of first physical zones including one or more memory blocks in one memory die or a plurality of second physical zones including portions of each of memory blocks included in different memory dies are provided. electronic devices, including
According to claim 1,
The file system determines a section group including the allocated section based on the log,
The section group is a first section group including a first section allocated with data stored in the first physical zone or a second section group including a second section allocated with data stored in the second physical zone. electronic device.
The method of claim 2, wherein the log,
An electronic device allocated according to the type and temperature of the data.
According to claim 3,
Data stored in the first physical zone has a smaller capacity or higher input/output frequency than data stored in the second physical zone.
The method of claim 4, wherein the log of data stored in the first physical zone,
An electronic device that is either a hot node, warm node, cold node, and hot data.
The method of claim 4, wherein the log of data stored in the second physical zone,
An electronic device that is either warm data or cold data.
applications requesting to write data; and
In response to the request of the application, a file system that generates a log related to the attributes of the data and allocates a section corresponding to the data based on the log;
The file system determines a section group including the section based on the log;
The section group is
one or more first section groups allocating one of the empty sections in the section group as a new section regardless of the order of the sections in the section group; or
one or more second section groups to which new sections are allocated according to the order of sections in the section groups;
The method of claim 7, wherein the file system,
A host device that performs a reset operation of converting the section into an empty section when all data corresponding to a specific section is invalid.
The method of claim 8, wherein the file system,
When all data corresponding to the specific section included in the first section group is invalid, the host device completes the reset operation by discarding all the data.
The method of claim 9, wherein the file system,
When all data corresponding to the specific section included in the second section group is invalid, storing information indicating that the specific section is ready to reset;
The host device completes a reset operation by discarding all data corresponding to all sections after storing information indicating that resetting is being prepared for all sections included in the second section group.
11. The method of claim 10, wherein the file system,
A host device that performs cleaning by determining a victim section and performing the reset operation on the victim section in order to secure an empty section.
The method of claim 11, wherein the sacrificial section,
The host device determined using the number of sections in which information indicating that the reset is being prepared is stored.
According to claim 12,
Among data corresponding to the victim section, valid data is moved to a section in a section group having the same type as a section group including the victim section.
a memory device including a plurality of memory dies; and
The memory device receives data and a log of the data from an external host, allocates a super block in which data is to be stored in the memory device, and sequentially stores the data in a physical zone included in the super block. Including; a memory controller for controlling;
The super block,
According to the log, a plurality of first physical zones including one or more memory blocks in one memory die or a plurality of second physical zones including portions of each of memory blocks included in different memory dies are provided. A storage device containing
15. The method of claim 14, wherein the memory controller,
A storage device that receives a log of data to be stored from the external host and allocates the super block according to the log.
16. The method of claim 15, wherein the memory controller,
When a write request for data is received from the host, the storage device converts a logical address corresponding to the data into a continuous physical address within a physical area included in the super block according to the allocated super block.
The method of claim 14, wherein the second physical zone,
A storage device formed across all memory dies.
According to claim 14,
The number of pages included in the first physical zone and the number of pages included in the second physical zone are the same.
According to claim 14,
The super block is a first super block including a plurality of first physical zones or a second super block including a plurality of second physical zones,
The storage device of claim 1 , wherein the number of memory blocks included in the first super block and the second super block are the same.
The method of claim 19, wherein the first super block and the second super block,
A storage device comprising one or more memory blocks formed across all memory dies and included in each of all the memory dies.

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