KR20220159269A - Storage device and operating method thereof - Google Patents

Abstract

The invention relates to a storage device and an operating method thereof. The storage device according to one embodiment of the present invention may include: a memory device including a plurality of memory dies; and a memory controller controlling the memory device in units of super blocks including two or more memory blocks included in the memory device. One or more of the super blocks may be a super block including a plurality of small multi-die zones including a portion of each of memory blocks included in different memory dies. The memory controller may select a sacrificial superblock in response to a garbage collection execution request received from an external host, and the garbage collection execution request may include information about valid pages included in the small multi-die region. The efficient management is possible according to data characteristics.

Description

Storage device and its operating method {STORAGE DEVICE AND OPERATING METHOD THEREOF}

The present invention relates to an electronic device, and more particularly, to a storage device and an operating method thereof.

The storage device converts the logical address received from the host into a physical address, and thus, a logical area within the host and a physical area of the storage device are related to each other. Accordingly, in order to improve the performance of electronic devices, a new device or method capable of controlling a host and a storage device in a complementary manner is required.

An embodiment of the present invention provides a storage device capable of efficiently managing data by characteristics and an operation method thereof.

A storage device according to an embodiment of the present invention includes a memory device including a plurality of memory dies; and a memory controller controlling the memory device in units of super blocks including two or more memory blocks included in the memory device, wherein one or more of the super blocks are memory blocks included in different memory dies. A super block including a plurality of small multi-die zones including a part of each zone, wherein the memory controller selects a victim super block in response to a garbage collection request received from an external host; The garbage collection execution request may include information about valid pages included in the small multi-die zone.

An operating method according to an embodiment of the present invention includes a memory device including a plurality of memory dies and a memory controller controlling the memory device in units of super blocks including two or more memory blocks included in the memory device. A method of operating a storage device, comprising: receiving a garbage collection request from an external host; and selecting a victim super block based on information on valid pages included in the garbage collection performance request from among the super blocks, wherein one or more of the super blocks are included in different memory dies. It may be a super block including a plurality of small multi-die zones including portions of each of the memory blocks.

The present technology provides a storage device capable of efficiently managing each characteristic of data and an operation method thereof.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present invention.
FIG. 2 is a diagram for explaining the memory device of FIG. 1 .
FIG. 3 is a diagram for explaining the memory cell array of FIG. 2 .
4 is a diagram for explaining a super block allocation process of a storage device according to an embodiment of the present invention.
5 is a diagram for explaining super block management of a storage device according to an embodiment of the present invention.
6 is a diagram for explaining the structure of a section allocated by a file system.
7 is a diagram for explaining a process of allocating a new section of a first section group by a file system.
8 and 9 are diagrams for explaining a process of allocating a new section of a second section group by a file system.
10 is a diagram for explaining a reset process of a first section group by a file system.
11 is a diagram for explaining a reset process of a second section group by a file system.
12 is a diagram for explaining garbage collection in a storage device according to an embodiment of the present invention.
13 is a flowchart illustrating a process of selecting a victim super block in a storage device according to an embodiment of the present invention.
14 is a flowchart illustrating a process of performing garbage collection on a victim super block in a storage device according to an embodiment of the present invention.
15 is a diagram illustrating another embodiment of the memory controller of FIG. 1 .
16 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present invention is applied.
17 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.
18 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in the present specification or application are only exemplified for the purpose of explaining the embodiment according to the concept of the present invention, and the implementation according to the concept of the present invention Examples may be embodied in many forms and should not be construed as limited to the embodiments described in this specification or application.

1 is a diagram for explaining a storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 1 , a storage device 50 may include a memory device 100 and a memory controller 200 . The storage device 50 stores data under the control of the host 400, such as a mobile phone, smart phone, MP3 player, laptop computer, desktop computer, game console, TV, tablet PC, or in-vehicle infotainment system. It may be a device that Alternatively, the storage device 50 may be a device that stores data under the control of the host 400 that stores high-capacity data in one place, such as a server or data center.

The storage device 50 may be manufactured as one of various types of storage devices according to a host interface, which is a communication method with the host 400 . For example, the storage device 50 may include a multimedia card in the form of SSD, MMC, eMMC, RS-MMC, and micro-MMC, secure digital in the form of SD, mini-SD, and micro-SD. card, universal serial bus (USB) storage device, universal flash storage (UFS) device, personal computer memory card international association (PCMCIA) card-type storage device, PCI (peripheral component interconnection) card-type storage device, PCI-E ( It may be configured with any one of various types of storage devices such as a PCI express card type storage device, a CF (compact flash) card, a smart media card, a memory stick, and the like.

The storage device 50 may be manufactured in any one of various types of packages. For example, the storage device 50 may include package on package (POP), system in package (SIP), system on chip (SOC), multi-chip package (MCP), chip on board (COB), wafer- level fabricated package), wafer-level stack package (WSP), and the like.

The memory device 100 may store data. The memory device 100 operates in response to control of the memory controller 200 . The memory device 100 may include a memory cell array (not shown) including a plurality of memory cells that store data.

The memory cells are single-level cells (SLC) each storing one data bit, multi-level cells (MLC) storing two data bits, and triple-level cells storing three data bits. (Triple Level Cell; TLC) or Quad Level Cell (QLC) capable of storing four data bits.

A memory cell array (not shown) may include a plurality of memory blocks. Each memory block may include a plurality of memory cells. Each memory block may include a plurality of pages. In an embodiment, a page may be a unit for storing data in the memory device 100 or reading data stored in the memory device 100 . A memory block may be a unit for erasing data.

In an embodiment, the memory device 100 may include DDR Double Data Rate Synchronous Dynamic Random Access Memory (SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), and RDRAM. (Rambus Dynamic Random Access Memory), NAND flash memory, Vertical NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change RAM (PRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), spin transfer torque random access memory (STT-RAM) ) and so on. In this specification, for convenience of explanation, it is assumed that the memory device 100 is a NAND flash memory.

The memory device 100 is configured to receive a command and an address from the memory controller 200 and access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by a command with respect to an area selected by an address. For example, the memory device 100 may perform a write operation (program operation), a read operation, and an erase operation. During a program operation, the memory device 100 will program data into an area selected by an address. During a read operation, the memory device 100 will read data from an area selected by an address. During the erase operation, the memory device 100 will erase data stored in the area selected by the address.

The memory controller 200 may control overall operations of the storage device 50 .

In an embodiment, the memory controller 200 may receive data and a logical address (LA) from the host 400, and the memory controller 200 includes the logical address LA in the memory device 100. firmware (not shown) capable of converting the stored data into a physical address (PA) indicating the addresses of memory cells to be stored. Also, the memory controller 200 may store a logical-physical address mapping table constituting a mapping relationship between the logical address LA and the physical address PA in the buffer memory.

The memory controller 200 may control the memory device 100 to perform a program operation, a read operation, or an erase operation according to a request of the host 400 . During a program operation, the memory controller 200 may provide a program command, a physical address, and data to the memory device 100 . During a read operation, the memory controller 200 may provide a read command and a physical address to the memory device 100 . During an erase operation, the memory controller 200 may provide an erase command and a physical address to the memory device 100 . Alternatively, the memory controller 200 may open or close a zone in the memory device 100 according to a request of the host 400 . Opening a zone may mean creating a map table for logical addresses corresponding to a logical address group corresponding to the corresponding zone, for example, a section allocated to data by a host. Closing a zone may indicate that there will be no write request for storing data in the zone until an open request for the zone is received again. The host 400 may provide the request to open or close the zone as a separate request, or together with other requests such as a write request.

In an embodiment, the memory controller 200 may generate commands, addresses, and data on its own and transmit them to the memory device 100 regardless of a request from the host 400 . For example, the memory controller 200 uses commands for performing program operations, read operations, and erase operations involved in performing wear leveling, read reclaim, garbage collection, and the like. , addresses and data may be provided to the memory device 100 .

In an embodiment, the memory controller 200 may include a flash translation layer. The flash translation layer may convert a logical address LA corresponding to a request received from the host 400 into a physical address PA and output the converted physical address to the memory device 100 .

For example, as described above, the flash translation layer converts a logical address (LA) corresponding to a program request into a physical address (PA), or converts a logical address (LA) corresponding to a read request into a physical address (PA). , or a logical address LA corresponding to an erase request may be converted into a physical address PA. The flash translation layer outputs the converted physical address PA to the memory device 100, and the memory device 100 may perform an operation on a page or memory block corresponding to the physical address PA.

In an embodiment, the memory controller 200 may receive logical addresses from the file system 420 and convert the received logical addresses into consecutive physical addresses. When consecutive physical addresses are output to the memory device 100, the memory device 100 may perform consecutive operations corresponding to the consecutive physical addresses. At this time, consecutive physical addresses may be determined according to the type of zone to be allocated. The types of zones will be described in detail with reference to FIGS. 4 and 5 .

In an embodiment, the storage device 50 may further include a buffer memory (not shown). The memory controller 200 may control data exchange between the host 400 and a buffer memory (not shown). Alternatively, the memory controller 200 may temporarily store system data for controlling the memory device 100 in the buffer memory. For example, the memory controller 200 may temporarily store data input from the host 400 in a buffer memory and then transmit the data temporarily stored in the buffer memory to the memory device 100 .

In various embodiments, the buffer memory may be used as an operation memory and a cache memory of the memory controller 200 . The buffer memory may store codes or commands executed by the memory controller 200 . Alternatively, the buffer memory may store data processed by the memory controller 200 .

In an embodiment, the buffer memory is DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR) or RDRAM It may be implemented as dynamic random access memory (DRAM) or static random access memory (SRAM) such as (Rambus Dynamic Random Access Memory).

In various embodiments, the buffer memory may be connected externally to the storage device 50 . In this case, volatile memory devices connected to the outside of the storage device 50 may serve as a buffer memory.

In an embodiment, the memory controller 200 may control at least two or more memory devices 100 . In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operating performance. The interleaving method may be a method of controlling operations of at least two or more memory devices 100 to overlap. Alternatively, the interleaving method may be a method of controlling operations of a plurality of groups classified in one memory device 100 to be overlapped. In this case, the group may be a unit of one or more memory dies or a unit of one or more memory planes.

The host 400 is USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe ( PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM ), LRDIMM (Load Reduced DIMM), etc., may communicate with the storage device 50 using at least one of various communication methods.

In an embodiment, the host 400 may include an application 410 . The application 410 is also referred to as an application program and may be software executed on an operating system (OS). The application 410 may process data in response to user input. For example, the application 410 may process data in response to a user's input and transfer a request to store the processed data in the memory device 100 of the storage device 50 to the file system 420 . .

The file system 420 may allocate a logical address (LA) where data is stored in response to a request transmitted from an application. In an embodiment, the file system 420 may be a log structure file system (LFS). The log structured file system (LFS) may create a log in consideration of attributes of input data, and allocate a section corresponding to the data based on the log. At this time, the section may be a set of logical addresses. Therefore, allocation of a section may mean that logical addresses corresponding to corresponding data are allocated. Data to which sections are allocated may be sequentially stored in storage areas of the memory device 100 corresponding to the sections. For example, the log structured file system (LFS) may be a flash friendly file system (F2FS). A flash-friendly file system (F2FS) is a log-based file system designed in consideration of the characteristics of a Solid State Drive (SSD), and can increase parallelism within the SSD by using a multi-head log. Data generated in different logs can be assigned different sections. The log structure file system (LFS) cannot overwrite data. When data is modified, the log structure file system (LFS) allocates a new logical address corresponding to the data to be modified and writes the data to a physical area corresponding to the new logical address.

Data requested to be written by the application 410 may be stored in a host memory (not shown) in the host, and may be flushed to the storage device 50 according to a request from the application through a device interface (not shown). can The host memory may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

FIG. 2 is a diagram for explaining the memory device of FIG. 1 .

Referring to FIG. 2 , the memory device 100 may include a memory cell array 110 , a voltage generator 120 , an address decoder 130 , an input/output circuit 140 and a control logic 150 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKi. The plurality of memory blocks BLK1 to BLKi are connected to the address decoder 130 through row lines RL. The plurality of memory blocks BLK1 to BLKi may be connected to the input/output circuit 140 through column lines CL. In an embodiment, the row lines RL may include word lines, source select lines, and drain select lines. In an embodiment, the column lines CL may include bit lines.

In an embodiment, the memory cell array 110 may include one or more memory dies, and each memory die may include one or more planes including one or more memory blocks.

Also, the plurality of memory blocks BLK included in the memory cell array 110 may be grouped into two or more super blocks (SBs). The super block SB may be a unit in which the control logic 150 manages a plurality of memory blocks BLK included in the memory cell array 110 . One super block (SB) is a set of memory blocks (BLK) in which read and/or write operations are performed simultaneously or at the same time, or in which read and/or write operations are linked or related, or A set of memory blocks BLK in which a read operation and/or a write operation are performed with respect to a command, or a set of memory blocks BLK in which a read operation and/or a write operation are performed in conjunction with or simultaneously in the memory cell array 110. may be a set. In addition, a group of memory blocks BLK that are distinguished from each other in terms of management or operation among several memory blocks BLK may be referred to as a super block SB. Each of the two or more super blocks SB may have the same size. That is, the number of memory blocks BLK included in each of two or more super blocks SB may be the same. Alternatively, at least one of the two or more super blocks SB may have a different size from the rest. That is, the number of memory blocks BLK included in at least one super block SB among the plurality of super blocks SB may be different from the number of memory blocks BLK included in the other super blocks SB. Also, two or more memory blocks BLK included in each of the two or more super blocks SB may be located on the same memory die. Alternatively, the two or more memory blocks BLK included in each of the two or more super blocks SB may be located on two or more different memory dies.

Each of the plurality of memory blocks BLK1 to BLKi includes a plurality of memory cells. In an embodiment, the plurality of memory cells may be nonvolatile memory cells. Among the plurality of memory cells, memory cells connected to the same word line may be defined as one physical page. That is, the memory cell array 110 may include a plurality of physical pages. The memory cells of the memory device 100 include a single level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, and three data bits. It may be configured as a triple level cell (TLC) that stores . or a quad level cell (QLC) that can store four data bits.

In an embodiment, the voltage generator 120, the address decoder 130, and the input/output circuit 140 may be collectively referred to as a peripheral circuit. The peripheral circuit may drive the memory cell array 110 under the control of the control logic 150 . A peripheral circuit may drive the memory cell array 110 to perform a program operation, a read operation, and an erase operation.

The voltage generator 120 is configured to generate a plurality of operating voltages using an external power supply voltage supplied to the memory device 100 . The voltage generator 120 operates in response to control of the control logic 150 .

As an example embodiment, the voltage generator 120 may generate an internal power voltage by regulating an external power voltage. The internal power supply voltage generated by the voltage generator 120 is used as an operating voltage of the memory device 100 .

As an embodiment, the voltage generator 120 may generate a plurality of operating voltages using an external power supply voltage or an internal power supply voltage. The voltage generator 120 may be configured to generate various voltages required by the memory device 100 . For example, the voltage generator 120 may generate a plurality of erase voltages, a plurality of program voltages, a plurality of pass voltages, a plurality of select read voltages, and a plurality of non-select read voltages.

The voltage generator 120 includes a plurality of pumping capacitors receiving an internal power supply voltage in order to generate a plurality of operating voltages having various voltage levels, and generates a plurality of pumping capacitors in response to the control of the control logic 150. It will selectively activate to generate a plurality of operating voltages.

The generated operating voltages may be supplied to the memory cell array 110 by the address decoder 130 .

The address decoder 130 is connected to the memory cell array 110 through row lines RL. The address decoder 130 is configured to operate in response to control of the control logic 150 . The address decoder 130 may receive the address ADDR from the control logic 150 . The address decoder 130 may decode a block address among the received addresses ADDR. The address decoder 130 selects at least one memory block among the memory blocks BLK1 to BLKi according to the decoded block address. The address decoder 130 may decode a row address among the received addresses ADDR. The address decoder 130 may select at least one word line among word lines of the selected memory block according to the decoded row address. In an embodiment, the address decoder 130 may decode a column address among the received addresses ADDR. The address decoder 130 may connect the input/output circuit 140 and the memory cell array 110 according to the decoded column address.

Illustratively, the address decoder 130 may include components such as a row decoder, a column decoder, and an address buffer.

The input/output circuit 140 may include a plurality of page buffers. A plurality of page buffers may be connected to the memory cell array 110 through bit lines. During a program operation, data may be stored in memory cells selected according to data stored in a plurality of page buffers.

During a read operation, data stored in selected memory cells may be sensed through bit lines, and the sensed data may be stored in page buffers.

The control logic 150 may control the address decoder 130 , the voltage generator 120 and the input/output circuit 140 . The control logic 150 may operate in response to a command CMD transmitted from an external device. The control logic 150 may control peripheral circuits by generating control signals in response to the command CMD and the address ADDR.

FIG. 3 is a diagram for explaining the memory cell array of FIG. 2 .

Referring to FIG. 3 , the memory cell array 110 may include one or more memory dies, and each memory die may include one or more planes including one or more memory blocks. . Although the memory cell array 110 is illustrated in FIG. 3 as including four memory dies (DIE#0, DIE#1, DIE#2, and DIE#3), the number of memory dies is not limited thereto. The plurality of memory dies may transmit/receive data to and from the memory controller through a plurality of channels, and each channel may be connected to one or more memory dies. For example, if one channel is connected to one memory die, one memory die can receive one command at a time, and the planes included in one memory die transmit the commands received by the memory die in parallel. can be dealt with

4 is a diagram for explaining a super block allocation process of a storage device according to an embodiment of the present invention.

1 and 4 , the file system 420 of the host 400 generates a log based on data attributes for data requested to be written by the application 410, and classifies the data based on this log. Determines the section group that contains the section to be allocated for data. According to various criteria, data is first type data to which the first section 422a of the first section group 421a is assigned and second type data to which the second section 422b of the second section group 421b is assigned. can be distinguished by Data allocated to the first section 422a in the first section group 421a by the file system is stored in the small single die zone in the first super block 111a of the memory device 100 under the control of the memory controller 200. Data stored in (small single-die zone, 112a) and allocated to the second section 422b in the second section group 421b is stored in the small multi-die zone in the second super block 111b of the memory device 100. (small multi-die zone, 112b). The first section group 421a corresponds to the first super block 111a, and thus the first section 422a corresponds to the small single die zone 112a. The characteristics of the first section 422a, to which new sections can be allocated regardless of the order of sections in the section group, correspond to the characteristics of the small single die zone 112a managed for each memory die, and the first section 422a Both the small single die zone 112a and the small single die zone 112a have the same characteristics that a reset or erase operation can be performed in units of one section or zone. In addition, the characteristics of the second section 422b for allocating new sections according to the section order within the section group match the characteristics of the small multi-die zone 112b formed over a plurality of memory dies, and the second section 422b ) and the small multi-die zone 112b cannot be reset or erased in units of one section or zone, and both the second section group 421b and the second super block 111b to which each belongs can be reset or erased. After reaching the enabled state, the characteristic of performing a reset or erase operation in units of section groups and super blocks is consistent. Assignment and reset of the first section 422a and the second section 422b are described in more detail in FIGS. 6 to 11, and the shapes of the small single die zone 112a and the small multi-die zone 112b in FIG. 5. .

The first sections 422a in the first section group 421a are allocated regardless of the section order, and in response to a zone allocation request from the host 400 in which data to which the sections are allocated will be stored, the memory controller 200 selects one It is possible to allocate a small single die zone 112a formed of an area within the memory die of . The second sections 422b in the second section group 422b are allocated according to the section order, and in response to a request from the host 400 for allocating a zone in which section-allocated data is to be stored, the memory controller 200 configures a plurality of A small multi-die zone 112b formed of a region including some of memory blocks in memory dies may be allocated. In response to the zone allocation request of the host 400, when the memory controller 200 returns information indicating that there is no additionally allocable zone in the super block currently being used, the file system 420 allocates a new section group and then allocates a new section group. Sections within the section group may be allocated, and in response to this, the memory controller 200 may allocate a new super block and a new zone included therein, and then store data to which the new section is allocated. Alternatively, the file system 420 may allocate a new section group and a section included in the new section group by itself without receiving information about the super block and zone from the memory controller 200 .

5 is a diagram for explaining super block management of a storage device according to an embodiment of the present invention.

1, 4, and 5 , the memory cell array 110 may include a plurality of memory dies, for example, four memory dies (DIE#0 to DIE#3). have. Also, each memory die may include a plurality of planes each including a plurality of memory blocks, and may include, for example, four planes (PLANE#0 to PLANE#3). The memory controller 200 may control the memory cell array 110 of the memory device 100 by dividing it into a plurality of super blocks. Super blocks may include two or more memory blocks included in the memory cell array 110 . Super blocks may include a plurality of zones. A super block may be formed across a plurality of memory dies, and as shown in FIG. 5 , a super block may be formed across all memory dies. The super block may be classified into a first super block 111a and a second super block 111b according to the shape of the included zone. In a storage device according to an embodiment of the present invention, a super block, which is a unit in which the memory controller 200 controls the memory device 100, is composed of only second super blocks 111b including small multi-die zones 112b or , second super blocks 111b including small multi-die zones 112b and first super blocks 111a including small single die zones 112a.

The small single die zone 112a included in the first super block 111a may include one or more blocks in one memory die. For example, as shown in FIG. 5 , an area including one memory block included in planes 0 to 3 for each memory die may be designated as one zone, and accordingly, the first super block 111a is It may include four small single die zones 112a formed one by one.

The small multi-die zone 112b included in the second super block 111b may include portions of blocks included in different memory dies. For example, as shown in FIG. 5, the small multi-die zone 112b is formed over all four memory dies (DIE#0 to DIE#3), but only a part of each of the memory blocks included in each plane. can include For example, as shown in FIG. 5 , only 1/4 of the pages of each memory block included in each plane may be included. Accordingly, the second super block 111b may include four small multi-die zones 112b formed over all memory dies to include only some pages of each memory block.

In an embodiment, the first super block 111a and the second super block 111b may have the same size. That is, the first super block 111a and the second super block 111b may include the same number of memory blocks. Also, the size of the small single die zone 112a and the small multi-die zone 112b may be the same. That is, the number of pages included in the small single-die zone 112a and the small multi-die zone 112b may be the same. The small single die zone 112a may be formed within one memory die, while the small multi-die zone 112b may be formed across a plurality of memory dies. Therefore, in the case of the small multi-die zone 112b, the die interleaving method can be operated. In particular, when the small multi-die zone 112b is formed over all memory dies as shown in FIG. 5, full-die ) can be operated in an interleaving manner. However, it is not possible to simultaneously allocate and program different small multi-die zones 112b. In addition, since the small multi-die zone includes only a part of each memory block, when a specific zone is to be erased, it cannot be erased immediately, and all pages of each memory block partially included in the corresponding zone can be erased When erasure of all zones of the super block including the corresponding zone is possible, the corresponding zone can be erased. Therefore, in the case of a small multi-die zone, there is an advantage in that it can operate in an interleaving manner in units of memory dies, but considering limitations in programming and erasing, it may not be suitable for storing data with high input/output frequency. Accordingly, when both the first super block and the second super block are used, data having a relatively small capacity or high input/output frequency is stored in the small single die zone in the first super block, and the small single die zone in the second super block is stored. By storing data with a relatively large capacity or low input/output frequency in the multi-die zone, performance of the storage device can be expected to improve.

Zones representing physical zones included in a super block, such as a small single-die zone or a small multi-die zone, may be classified into a full state, an empty state, and an active state. The full state may refer to a state in which data is stored in all areas in a zone and no empty areas in the zone exist. An empty state may mean a state in which a zone is empty without data stored in an area within the zone. In the case of an active state, it may mean a state in which data is stored only in a part of the zone, and may be in an open state or a closed state. The open state may mean a zone in which data is currently being programmed among zones in which data is stored only in some areas within the zone, and a closed state may mean a zone in which data is not currently being programmed among zones in which data is stored in only some areas in the zone.

In addition, in the case of a small multi-die zone, it may further have a ready to reset state. A reset operation for a zone may refer to an operation for creating an empty zone by erasing the zone. Erasing may be performed in units of memory blocks. As shown in FIG. 5 , the small multi-die zone 112b includes only a portion of each of a plurality of memory blocks. On the other hand, in the case of the small single die zone 112a, one or more memory blocks may all be included. Accordingly, when a specific small single die zone 112a is to be reset, the corresponding zone can be immediately erased. On the other hand, when a specific small multi-die zone 112b is to be reset, when all pages of each of the memory blocks partially included in the corresponding zone can be erased, that is, the entire zone of the super block including the corresponding zone can be erased. When possible, the corresponding zone may be erased. Therefore, when a reset operation is performed on the small multi-die zone 112b, the corresponding zone is not immediately erased, but is converted into a ready to reset state, and the first zone including the small multi-die zone 112b is switched to a ready to reset state. When all the small multi-die zones 112b in the second super block 111b are converted to the reset preparation state, all the small multi-die zones 112b in the corresponding super block are erased at once and converted to an empty state. have.

6 is a diagram for explaining the structure of a section allocated by a file system.

Referring to FIG. 6 , a section may include a plurality of logical addresses. Logical addresses included in one section may be contiguous addresses or non-contiguous addresses. Allocating a section to data may mean allocating a logical address within the section. Information on addresses included in each section may be included in a memory in a host or a memory in a storage device. Logical addresses may be sequentially allocated according to the size of write-requested data. For example, if there is a write request for data D1 and D2 of a specific size, and the section of FIG. 5 is allocated to both data D1 and D2, logical addresses LA1 to LA3 may be allocated for D1, and D2 Logical addresses of LA4 and LA5 may be allocated for .

7 is a diagram for explaining a process of allocating a new section of a first section group by a file system.

Referring to FIG. 7 , a section group to which a new section can be allocated may be defined as a first section group 421a regardless of the order of sections within the section group. In this case, the logical addresses included in the sections in the section group may be consecutive to each other, and the logical addresses may increase as the number of sections in the section group increases. Accordingly, the section order may mean the order of section numbers in a section group, which may mean the order in the direction of increasing logical addresses. Alternatively, logical addresses included in sections in a section group may not be consecutive to each other. In this case, the section order may be determined based on information about sections stored in a separate memory and logical addresses included in each section group. In the case of the first section group 421a, since the sections are allocated and logical addresses can be assigned regardless of the section order, the third section (Section#3) is assigned first and all logical addresses in the third section are assigned. After becoming a full section, a first section (Section#1) may be allocated and a logical address for new data may be assigned. When all the logical addresses of the first section, which is an open section, are assigned to data and the first section becomes a full section, the file system 420 creates an empty section, section 0 (Section#0). Alternatively, any one of the second sections (Section#2) may be allocated as a new section and a logical address included therein may be assigned to data.

8 and 9 are diagrams for explaining a process of allocating a new section of a second section group by a file system.

Referring to FIGS. 8 and 9 , a section group to which new sections can be allocated according to the order of sections within the section group may be defined as a second section group 421b. As shown in FIG. 8, in the second section group, the 0th section (Section#0) is opened first and logical addresses included therein are given to data. The first section (Section#1) may be allocated as a new section to store data. If all the sections in the second section group 421b are full sections as shown in FIG. 9, the file system 420 allocates a new second section group 421b, and then the first section in the new second section group The 0th section (Section#0) may be allocated as a new section, and a logical address included therein may be assigned to data. At this time, in the case of the second section 421b, sections are allocated according to the order of sections in the section group. If the last section, the third section (Section#3), is a full section, among the previous sections, empty sections (Empty Section) ) cannot exist. Therefore, in the case of the second section group 421b, there is no need to find an empty section in the section group, and if the next section in the second section group 421b does not exist, the file system 420 starts a new second section. The group 421b is assigned.

10 is a diagram for explaining a reset process of a first section group by a file system.

Referring to FIG. 10, in the first section group 421a, 1) when the 0th section (Section#0) is reset, 2) by discarding all data corresponding to logical addresses in the 0th section. , the 0th section becomes an empty section and the reset operation is completed. In addition, 3) when resetting the first section (Section#1), 4) by discarding all data corresponding to logical addresses in the first section, the first section becomes an empty section. The reset operation is complete. In addition, 5) when the second section (Section#2) is reset, 6) by discarding all data corresponding to logical addresses in the second section, the second section becomes an empty section. The reset operation is complete. That is, when a reset operation is performed on one section included in the first section group 421a, in response to this, data corresponding to logical addresses in the corresponding section are discarded, and the corresponding section is immediately empty ( empty) section, and thus the reset operation can be completed. At this time, discarding data corresponding to the logical addresses in the reset operation for the section may mean canceling a mapping relationship between logical addresses and data. The reset operation is performed when all data corresponding to logical addresses in a specific section are invalid. If there is valid data, it is mapped to a logical address in another section, and the data corresponding to the corresponding logical address is invalid. ) After processing, a reset operation may be performed. Logical addresses included in the reset-completed section may be assigned again for new data. This reset operation may be performed by a file system.

11 is a diagram for explaining a reset process of a second section group by a file system.

5 and 11, in the second section group 421b, 1) when the 0th section (Section#0) is reset, 2) data corresponding to logical addresses in the 0th section are not immediately discarded. and information indicating that the 0th section is ready to reset is stored in the bitmap. In addition, 3) when the first section (Section#1) is reset, 4) data corresponding to logical addresses in the first section are not immediately discarded, indicating that the first section is preparing for reset (Ready to Reset). Information is stored in a bitmap. In addition, 5) when the second section (Section#2) is reset, 6) data corresponding to logical addresses in the second section are not immediately discarded, indicating that the second section is preparing for reset (Ready to Reset). Information is stored in a bitmap. In addition, 7) when the third section (Section#3) is reset, 8) data corresponding to logical addresses in the third section are not discarded as waves, indicating that the third section is preparing for reset (Ready to Reset). Information is stored in a bitmap. 9) Accordingly, when information indicating that resetting is being prepared for all sections of the second section group 421b is stored in the bitmap, all data corresponding to all logical addresses in all sections are discarded, All sections in the second section group 421b become empty sections at once, so that the reset operation can be completed. That is, in the case of the second section group 421b, when only some of the sections are reset, the data is not immediately discarded, so the section does not become an empty section, but all sections in the second section group 421b After a reset operation is performed on all sections, i.e., after information indicating that resetting is being prepared for all sections is stored, data corresponding to logical addresses of all sections included in the second section group 421b are discarded, thereby discarding the second section group. All sections in 421b can be empty at the same time. When the reset operation is completed, information indicating that resetting is being prepared may be deleted for all sections in the second section group 421b. At this time, a bitmap storing information indicating that resetting is being prepared may be included in an arbitrary location in the storage device. At this time, discarding data corresponding to the logical addresses in the reset operation for the section may mean canceling a mapping relationship between logical addresses and data. The reset operation is performed when all data corresponding to logical addresses in a specific section are invalid. If there is valid data, it is mapped to a logical address in another section, and the data corresponding to the corresponding logical address is invalid. ) After processing, a reset operation may be performed. Logical addresses included in the reset-completed section may be assigned again for new data. This reset operation may be performed by a file system. That is, the reset operation of the second section corresponds to the reset operation of the small multi-die zone 112b in the second super block 111b in FIG. 5 . That is, when a reset operation is performed on the second section 422b, the second section becomes ready to reset, and accordingly, the small multi-die zone 112b corresponding to the second section 422b also It is not immediately erased, but converted to a ready to reset state. When all the second sections 422b in the second section group 421b including the second section 422b are converted to a ready to reset state, that is, the small multi-die zone 112b is included. Data corresponding to the logical addresses of all second sections 422b in the second section group 421b when all the small multi-die zones 112b in the second super block 111b are converted to the reset preparation state. As they are discarded, all sections in the second section group 421b simultaneously become empty sections, and all small multi-die zones 112b in the second super block 111b corresponding thereto are erased, leaving an empty state. do.

12 is a diagram for explaining garbage collection in a storage device according to an embodiment of the present invention.

Referring to FIGS. 1 , 4 and 12 , the host 400 includes a host garbage collection controller 430 . The host garbage collection control unit 430 may be included in the file system 420 or may be included in the host 400 as a separate component from the file system 420 . The host garbage collection controller 430 may include information on sections and section groups allocated by the file system 420 and information on super blocks and zones corresponding thereto. Also, information on each page included in the zones may be included. For example, information about validity or invalidity of data stored in each page may be included.

The host garbage collection control unit 430 may provide a garbage collection performance request to the storage device 50 . The garbage collection execution request may include information on each page included in the zones, and in an embodiment, information on valid pages included in the small multi-die zone may be included. More specifically, information on valid pages included in small multi-die zones in a full state may be included, for example, the number of valid pages included in small multi-die zones in a full state and a predetermined number of valid pages. A list of small multi-die zones including the above may be included.

The memory controller 200 in the storage device 50 may include a zone manager 210 and a device garbage collection controller 220 . The zone management unit 210 may allocate and manage zones and super blocks corresponding to sections and section groups allocated by the host. Corresponding to the first section 422a in the first section group 421a, the small single die zone 112a in the first super block 111a may be allocated and mapped, and the second section group 421b in the second section group 421b may be allocated and mapped. Corresponding to section 2 422b, the small multi-die zone 112b in the second super block 111b may be allocated and mapped. The device garbage collection controller 220 may perform garbage collection in response to a garbage collection request received by the storage device 50 from the host 400 . The device garbage collection control unit 220 may receive information about the allocated super block and zones from the zone management unit 210 and select a victim super block based on this. The sacrificial super block may be selected from the second super blocks 111b including the small multi-die zones 112b. The device garbage collection control unit 220 may select a victim super block from among super blocks composed of only zones in a full state and a reset preparation state. The device garbage collection control unit 220 may select a victim super block in consideration of the number of zones in a reset preparing state. Information on the number of zones in the reset preparing state may be received from the zone manager 210 or the host garbage collection controller 430 . For example, the possibility of being selected as a victim super block may increase as the number of zones in the preparing for reset state increases. Also, the device garbage collection control unit 220 may select a victim super block by considering information on valid pages included in zones in a full state. Information on valid pages included in zones in a full state may be received from the host garbage collection controller 430, and such information may be received along with a garbage collection execution request. For example, as the number of valid pages included in zones in a full state increases, the possibility of being selected as a victim super block increases. In the case of the zone management unit 210, information on whether pages included in the zone are valid or invalid may not be managed, and accordingly, related information may be received from the host garbage collection controller 430. When a victim super block is selected by the device garbage collection control unit 220, data stored in zones in a full state in the victim super block may be copied and stored in another super block by the zone management unit 210. If the victim super block is the second super block 111b including the small multi-die zones 112b, another super block in which the data of the full zone in the victim super block is copied and stored is also the second super block 111b. can be In addition, at this time, the zone management unit 210 may not manage information on whether pages included in the zone are valid or invalid, and thus data may be copied and stored in units of zones. Alternatively, data may be copied and stored in units of pages based on information on valid pages received from the host garbage collection controller 430 . That is, only data stored in valid pages among full zones included in the victim super block may be copied and stored in another super block.

13 is a flowchart illustrating a process of selecting a victim super block in a storage device according to an embodiment of the present invention.

Referring to FIGS. 12 and 13 , in step S1301 , the storage device 50 may receive a garbage collection request from the host 400 . In response to this, in step S1303, the memory controller 200 may select candidate super blocks. Candidate super blocks may be super blocks including a plurality of small multi-die zones. In an embodiment, super blocks composed of only small multi-die zones in a full state and a reset preparing state may be selected as candidate super blocks.

In step S1305, a cost for garbage collection for each of the candidate super blocks may be calculated. At this time, the cost for garbage collection may be calculated by considering the number of small multi-die zones in the reset preparation state in the super block.

In step S1307, the cost of each of the candidate super blocks may be modified based on the number of valid pages included in the full small multi-die zone included in each of the candidate super blocks. For example, as the number of valid pages included in the small multi-die zone in the full state increases, the probability of being selected as a victim super block may be increased by reducing cost by giving a weight. In this case, information on the number of valid pages may be included in the request for performing garbage collection. For example, the information on valid pages may include the number of valid pages included in full small multi-die zones and a list of small multi-die zones including a predetermined number or more of valid pages. First, it is checked whether the zone included in the candidate super block is in the list of small multi-die zones including a predetermined number or more of valid pages, and if it exists in the list, a weight is given based on the number of valid pages to determine the cost of the candidate super block. can reduce

In step S1309, costs of each of the candidate super blocks determined after being modified in step S1307 may be compared. Accordingly, a candidate super block having the lowest cost may be selected as a victim super block in step S1311.

14 is a flowchart illustrating a process of performing garbage collection on a victim super block in a storage device according to an embodiment of the present invention.

Referring to FIGS. 13 and 14 , data stored in full-state zones in the victim super block selected by the process shown in FIG. 13 may be copied in step S1401 and stored in another super block. If the victim super block is a second super block including small multi-die zones, another super block to which data moves may also be a second super block. In this case, copying of data may be performed in units of zones or pages.

In step S1403, erasure may be performed on the super block to which data movement is completed. Accordingly, all zones included in the victim super block may be converted to an empty state.

15 is a diagram illustrating another embodiment of the memory controller of FIG. 1 .

Referring to FIG. 15 , the memory controller 1000 includes a processor 1010, an internal memory 1020, an error correction code circuit 1030, a host interface 1040, A buffer memory interface (Buffer Memory Interface) 1050 and a memory interface (Memory Interface; 1060) may be included.

The processor 1010 may perform various operations for controlling the memory device 100 or generate various commands. Upon receiving a request from the host 400, the processor 1010 may generate a command according to the received request and transmit the generated command to a queue controller (not shown). Also, in response to a zone allocation request from the host 400, the processor 1010 may allocate a super block in a memory device in which data received from the host is to be stored and a zone included therein, and allocate the allocated super block and zone. can manage Also, the processor 1010 may perform garbage collection in response to a garbage collection request from the host 400 .

The internal memory 1020 may store various pieces of information necessary for the operation of the memory controller 1000 . For example, internal memory 1020 may include logical and physical address map tables. The internal memory 1020 may include at least one of random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), cache, and tightly coupled memory (TCM). .

The error correction code circuit 1030 is configured to detect and correct an error in data received from the memory device 100 using an error correction code (ECC). The processor 1010 may adjust a read voltage according to an error detection result of the error correction code circuit 1030 and control the memory device 100 to perform rereading. As an exemplary embodiment, the error correction block may be provided as a component of the memory controller 1000 .

The host interface 1040 may exchange commands, addresses, and data between the memory controller 1000 and the host 400 . For example, the host interface 1040 may receive a request, address, data, etc. from the host 400 and output data read from the memory device 100 to the host 400 . The host interface 1040 includes USB (Universal Serial Bus), SATA (Serial AT Attachment), SAS (Serial Attached SCSI), HSIC (High Speed Interchip), SCSI (Small Computer System Interface), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe (NonVolatile Memory express), UFS (Universal Flash Storage), SD (Secure Digital), MMC (MultiMedia Card), eMMC (embedded MMC), DIMM (Dual In-line Memory Module), RDIMM (Registered DIMM), LRDIMM (Load Reduced DIMM), ESDI (Enhanced Small Disk Interface), or IDE (Integrated Drive Electronics) protocols may be used to communicate with the host 400 . The host interface 1040 may receive a request to allocate a zone corresponding to a section allocated for data by the host 400 . The host interface 1040 may receive a request to perform garbage collection from the host 400, and at this time, may also receive information on valid pages included in the small multi-die zone of the memory device 100. .

The buffer memory interface 1050 may transmit data between the processor 1010 and the buffer memory. The buffer memory may be used as an operation memory or cache memory of the memory controller 1000 and may store data used in the storage device 50 . The buffer memory interface 1050 by the processor 1010 may use the buffer memory as a read buffer, a write buffer, a map buffer, and the like. Depending on the embodiment, the buffer memory is DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), DDR4 SDRAM, LPDDR4 (Low Power Double Data Rate 4) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, LPDDR (Low Power DDR), or It may include Rambus Dynamic Random Access Memory (RDRAM). When the buffer memory is included in the memory controller 1000, the buffer memory interface 1050 may be omitted.

The memory interface 1060 may exchange commands, addresses, and data between the memory controller 1000 and the memory device 100 . For example, the memory interface 1060 may transmit commands, addresses, and data to the memory device 100 through a channel and may receive data from the memory device 100 . The memory interface 1060 may transmit/receive commands, addresses, data, etc. to or from the memory device 100 based on super blocks and zones allocated and managed by the processor 1010 . Also, when garbage collection is performed, some data in a super block selected as a victim super block may be moved to another super block, and an erase operation may be performed on the victim super block.

16 is a block diagram illustrating a memory card system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 16 , a memory card system 2000 includes a memory controller 2100 , a memory device 2200 , and a connector 2300 .

The memory controller 2100 is connected to the memory device 2200 . The memory controller 2100 is configured to access the memory device 2200 . For example, the memory controller 2100 may be configured to control read, program, erase, and background operations of the memory device 2200 . The memory controller 2100 is configured to provide an interface between the memory device 2200 and a host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200 . The memory controller 2100 may be implemented identically to the memory controller 200 described with reference to FIG. 1 . For example, the memory controller 2100 may allocate a zone and a super block including the zone in the memory device 2200 and control the memory device 2200 in units of zones and super blocks.

Illustratively, the memory controller 2100 may include components such as a random access memory (RAM), a processing unit, a host interface, a memory interface, and an error correction unit. can

The memory controller 2100 may communicate with an external device through the connector 2300 . The memory controller 2100 may communicate with an external device (eg, a host) according to a specific communication standard. For example, the memory controller 2100 may include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), and advanced technology attachment (ATA). ), Serial-ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, It is configured to communicate with an external device through at least one of various communication standards such as NVMe. Illustratively, the connector 2300 may be defined by at least one of the above-described various communication standards.

For example, the memory device 2200 may include electrically erasable and programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase-change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and STT-MRAM. (Spin Transfer Torque Magnetic RAM) and the like.

The memory controller 2100 and the memory device 2200 may be integrated into a single semiconductor device to form a memory card. For example, the memory controller 2100 and the memory device 2200 are integrated into a single semiconductor device such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), or a smart media card (SM, SMC). ), memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro, eMMC), SD cards (SD, miniSD, microSD, SDHC), and universal flash memory (UFS).

17 is a block diagram illustrating a solid state drive (SSD) system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 17 , an SSD system 3000 includes a host 3100 and an SSD 3200 . The SSD 3200 exchanges signals with the host 3100 through the signal connector 3001 and receives power through the power connector 3002 . The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power supply 3230, and a buffer memory 3240.

According to an embodiment of the present invention, the SSD controller 3210 may perform the function of the memory controller 200 described with reference to FIG. 1 .

The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to a signal received from the host 3100 . The SSD controller 3210 may control the plurality of flash memories through a plurality of channels CH1 to CHn. One or more memory dies may be connected to each channel. For example, the signals may be signals based on an interface between the host 3100 and the SSD 3200 . For example, signals include universal serial bus (USB), multimedia card (MMC), embedded MMC (eMMC), peripheral component interconnection (PCI), PCI-express (PCI-E), advanced technology attachment (ATA), serial- Interfaces such as ATA, Parallel-ATA, SCSI (small computer system interface), ESDI (enhanced small disk interface), IDE (Integrated Drive Electronics), Firewire, UFS (Universal Flash Storage), WIFI, Bluetooth, NVMe, etc. It may be a signal defined by at least one of them. The SSD controller 3210 may perform garbage collection according to a garbage collection request received from the host 3100 .

The auxiliary power supply 3230 is connected to the host 3100 through a power connector 3002 . The auxiliary power supply 3230 can receive power from the host 3100 and charge it. The auxiliary power supply 3230 may provide power to the SSD 3200 when power supply from the host 3100 is not smooth. For example, the auxiliary power supply 3230 may be located inside the SSD 3200 or outside the SSD 3200 . For example, the auxiliary power supply 3230 is located on the main board and may provide auxiliary power to the SSD 3200.

The buffer memory 3240 operates as a buffer memory of the SSD 3200. For example, the buffer memory 3240 temporarily stores data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or metadata (metadata) of the flash memories 3221 to 322n. For example, a mapping table) may be temporarily stored. The buffer memory 3240 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

18 is a block diagram illustrating a user system to which a storage device according to an embodiment of the present invention is applied.

Referring to FIG. 18 , a user system 4000 includes an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

The application processor 4100 may drive components included in the user system 4000, an operating system (OS), a user program, or a file system. Illustratively, the application processor 4100 may include controllers, interfaces, graphic engines, and the like that control components included in the user system 4000 . The application processor 4100 may be provided as a System-on-Chip (SoC). The application processor 4100 may generate a log for data requested by a user to write, allocate section groups and sections based on the logs, and provide data to which the sections are allocated to the storage module 4400 .

The memory module 4200 may operate as a main memory, working memory, buffer memory, or cache memory of the user system 4000 . The memory module 4200 includes volatile random access memory such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, LPDDR SDARM, LPDDR2 SDRAM, and LPDDR3 SDRAM, or non-volatile random access memory such as PRAM, ReRAM, MRAM, FRAM, and the like. can do. For example, the application processor 4100 and the memory module 4200 may be packaged based on a package on package (POP) and provided as a single semiconductor package.

The network module 4300 may communicate with external devices. Illustratively, the network module 4300 may include code division multiple access (CDMA), global system for mobile communication (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), and long term evolution (LTE). ), wireless communication such as Wimax, WLAN, UWB, Bluetooth, Wi-Fi, etc. may be supported. For example, the network module 4300 may be included in the application processor 4100 .

The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100 . Alternatively, the storage module 4400 may transmit data stored in the storage module 4400 to the application processor 4100 . For example, the storage module 4400 is a non-volatile semiconductor memory device such as a phase-change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), a NAND flash, a NOR flash, a 3D NAND flash, and the like. can be implemented For example, the storage module 4400 may be provided as a removable storage medium such as a memory card or an external drive of the user system 4000 .

For example, the storage module 4400 may include a plurality of nonvolatile memory devices, and the plurality of nonvolatile memory devices may operate in the same way as the memory device 100 described with reference to FIG. 1 . The storage module 4400 may operate in the same way as the storage device 50 described with reference to FIG. 1 .

The user interface 4500 may include interfaces for inputting data or commands to the application processor 4100 or outputting data to an external device. For example, the user interface 4500 may include user input interfaces such as a keyboard, keypad, button, touch panel, touch screen, touch pad, touch ball, camera, microphone, gyroscope sensor, vibration sensor, piezoelectric element, and the like. have. The user interface 4500 may include user output interfaces such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an active matrix OLED (AMOLED) display device, an LED, a speaker, and a monitor.

50: storage device
100: memory device
200: memory controller
400: host

Claims (20)

a memory device including a plurality of memory dies; and
A memory controller controlling the memory device in units of super blocks including two or more memory blocks included in the memory device;
At least one of the super blocks is a super block including a plurality of small multi-die zones including portions of each of memory blocks included in different memory dies;
The memory controller,
In response to a garbage collection request received from an external host, a victim super block is selected;
The garbage collection request,
A storage device including information about valid pages included in the small multi-die zone.
According to claim 1,
The sacrificial super block is selected from super blocks including a plurality of small multi-die zones.
The method of claim 2, wherein the small multi-die zones,
Full state in which there is no empty area within the zone, Empty state in which the zone is empty, Active state in which data is stored only in some areas within the zone, and A storage device having a ready to reset state in which a reset operation has been performed, but the reset operation has not been completed according to the state of another zone in a super block including the zone.
The method of claim 3, wherein the sacrificial super block,
A storage device that is selected from a super block consisting of only small multi-die zones in full state and reset preparation state.
According to claim 3,
When a reset operation is performed on any one small multi-die zone, the one small multi-die zone is switched to a reset preparation state;
When all small multi-die zones in the super block including the small multi-die zone are converted to a reset preparation state, all small multi-die zones in the super block are erased to become empty.
The method of claim 4, wherein the information on valid pages included in the small multi-die zone comprises:
The storage device including information about valid pages included in the small multi-die zones in the full state.
The method of claim 6, wherein the sacrificial super block,
A storage device selected based on information about valid pages included in the small multi-die zones in the full state.
7. The method of claim 6, wherein the information about valid pages included in the small multi-die zones in the full state comprises:
and a list of small multi-die zones including the number of valid pages included in the full small multi-die zones and a predetermined number or more of valid pages.
The method of claim 6, wherein the sacrificial super block,
A storage device selected based on the number of small multi-die zones in the reset preparing state.
The method of claim 4 , wherein the memory controller comprises:
A storage device that copies data stored in small multi-die zones in a full state among small multi-die zones included in the victim super block and stores them in another super block including a plurality of small multi-die zones.
The method of claim 1, wherein one or more of the super blocks,
A storage device that is a super block including a plurality of small single-die zones including one or more memory blocks in one memory die.
A method of operating a storage device including a memory device including a plurality of memory dies and a memory controller controlling the memory device in units of super blocks including two or more memory blocks included in the memory device, the method comprising:
Receiving a garbage collection request from an external host; and
Selecting a victim super block from among super blocks based on information on valid pages included in the garbage collection performance request;
At least one of the super blocks is a super block including a plurality of small multi-die zones including portions of each of memory blocks included in different memory dies.
According to claim 12,
The victim super block is selected from super blocks including a plurality of small multi-die zones.
The method of claim 13, wherein the small multi-die zones,
Full state in which there is no empty area within the zone, Empty state in which the zone is empty, Active state in which data is stored only in some areas within the zone, and A reset operation has been performed, but the reset operation has not been completed according to the state of other zones in the super block including the zone, and has a state of Ready to reset,
The sacrificial super block,
An operation method selected from super blocks consisting of only small multi-die zones in a full state and in a reset preparation state.
14. The method of claim 13, wherein selecting the victim super block comprises:
selecting super blocks composed of only the small multi-die zones in the full state and the reset preparing state as candidate super blocks; and
and selecting a victim super block based on the number of valid pages included in full state small multi-die zones in the candidate super blocks.
16. The method of claim 15, wherein the information on the valid pages comprises:
and information related to the number of valid pages included in the small multi-die zones in the full state.
16. The method of claim 15, wherein selecting a victim super block based on the number of valid pages included in full small multi-die zones in the candidate super blocks comprises:
calculating a cost based on the number of small multi-die zones included in each of the candidate super blocks and in a reset preparation state;
modifying the cost based on the number of valid pages included in a full small multi-die zone included in each of the candidate super blocks; and
and comparing modified costs of the candidate super blocks.
According to claim 15,
copying data stored in full small multi-die zones included in the victim super block;
storing the copied data in another super block; and
The operation method further comprising erasing the victim super block.
The method of claim 18, wherein the other super block,
A method of operating a super block including a plurality of small multi-die zones.
The method of claim 12, wherein one or more of the super blocks,
A method of operating a super block including a plurality of small single die zones including one or more memory blocks in one memory die.

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