KR20080061969A - Semiconductor package and method for manufacturing semiconductor package - Google Patents

Semiconductor package and method for manufacturing semiconductor package Download PDF

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Publication number
KR20080061969A
KR20080061969A KR1020060137184A KR20060137184A KR20080061969A KR 20080061969 A KR20080061969 A KR 20080061969A KR 1020060137184 A KR1020060137184 A KR 1020060137184A KR 20060137184 A KR20060137184 A KR 20060137184A KR 20080061969 A KR20080061969 A KR 20080061969A
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KR
South Korea
Prior art keywords
semiconductor chip
bumps
bump
substrate
pads
Prior art date
Application number
KR1020060137184A
Other languages
Korean (ko)
Inventor
박신영
Original Assignee
주식회사 하이닉스반도체
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 주식회사 하이닉스반도체 filed Critical 주식회사 하이닉스반도체
Priority to KR1020060137184A priority Critical patent/KR20080061969A/en
Publication of KR20080061969A publication Critical patent/KR20080061969A/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

A semiconductor package and a method of manufacturing the same are disclosed. The disclosed semiconductor package includes a semiconductor chip having bump pads formed on one surface thereof, bumps formed on the bump pads so as to protrude from the bump pads, and having grooves for increasing area on the surface thereof, the semiconductor chip being bonded, and the semiconductor chip electrically connected to the semiconductor chip. A semiconductor chip having an external connection terminal connected to the substrate, wherein the semiconductor chip is electrically connected to the external connection terminals and covers the upper surface of the substrate including the semiconductor chip, the pads having the bonding pads corresponding to the bumps among the upper surfaces on which the semiconductor chip is bonded. It includes a molding structure to protect the from the external environment.

Description

Semiconductor package and manufacturing method therefor {SEMICONDUCTOR PACKAGE AND METHOD FOR MANUFACTURING SEMICONDUCTOR PACKAGE}

1 is a cross-sectional view of a semiconductor package according to the present invention.

2 is an enlarged view illustrating an enlarged portion A of FIG. 1;

3 is a cross-sectional view showing a step of forming a bump on a semiconductor chip according to the present invention.

4 is a cross-sectional view showing a groove for increasing an area formed on a surface of the bump shown in FIG. 3;

FIG. 5 is a sectional view showing the semiconductor chip shown in FIG. 4 attached to a substrate. FIG.

6 is a cross-sectional view of the underfill portion formed between the semiconductor chip and the substrate according to the present invention.

The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly, to a semiconductor package and a method for manufacturing the same by increasing the connection area of the base substrate and the semiconductor chip to minimize the connection failure.

In the semiconductor industry, a semiconductor package generally refers to a form in which a semiconductor chip, in which a microcircuit is designed, is sealed with a mold resin or ceramic so as to be protected from an external environment and mounted on an electronic device. In recent years, semiconductor chips are packaged for the purpose of improving the performance and quality of electronic devices through miniaturization, thinning, and multifunctionality of electronic devices, rather than packaging semiconductor chips for the purpose of enclosing, protecting, or simply mounting electronic devices. Doing. Therefore, the importance of semiconductor packages is increasing.

In accordance with the demand for miniaturization, thinning, and multifunction of electronic devices, flip chip type ball grid array (BGA) packages having a semiconductor package size of about 100% to 120% of semiconductor chips have been developed.

The flip chip type BGA package includes a semiconductor chip having bumps arranged on one surface thereof, an underfill portion filled between the semiconductor chip and the base substrate, on which the semiconductor chip is mounted and bonding pads are formed corresponding to the bumps of the semiconductor chip. A sealing portion covering and protecting the upper surface of the substrate, the solder ball is connected to the lower surface of the substrate and electrically connected to the bonding pads.

Here, the bump of the semiconductor chip is formed of, for example, gold, and is a stud bump having a diamond shape, and is formed at a predetermined height on a bump pad formed on the lower surface of the semiconductor chip. The solder for connecting the stud bumps and the bonding pads is coated on the upper surfaces of the bonding pads to which the stud bumps are connected.

A method of manufacturing a flip chip type BGA package having the above-described configuration will be described below.

Stud bumps are formed on bump pads disposed on the bottom surface of the semiconductor chip, the semiconductor chip is positioned on top of the substrate, and the bonding pads and the stud bumps are bonded. Then, the solder applied to the upper surface of the bonding pads surrounds the stud bumps formed of gold, and the bonding pads and the stud bumps are interconnected.

When the semiconductor chip is mounted on the substrate by a flip chip method, a gap formed between the substrate and the semiconductor chip is filled with a liquid underfill resin to form an underfill portion, and the molding structure is wrapped with a molding resin on the upper surface of the substrate including the semiconductor chip. To form. Thereafter, solder balls used as external connection terminals are connected to the lower surface of the substrate.

However, in the case of the conventional flip chip type BGA package, since the solder surrounds the stud bump formed of gold and interconnects the stud bump and the bonding pad, a poor connection between the stud bump and the bonding pad is easily generated, which degrades the reliability of the product. There is a problem. This is because when the material is bonded to two different kinds of metals, that is, gold and solder, the bonding properties are lower than interconnecting the same kinds of metals.

In order to solve this problem, when forming a bump using solder, a process of forming a solder bump having a predetermined height is very difficult due to the spreadability of the solder, and thus a problem in which solder bump defects are frequently generated in the process of forming solder bumps.

Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to provide a semiconductor package in which bumps and bonding pads are minimized by forming grooves in bumps of a semiconductor chip to increase a connection area between bumps and bonding pads; It is to provide a method for producing the same.

A semiconductor package for realizing the object of the present invention is a semiconductor chip having bump pads formed on one surface thereof, bumps formed on the bump pads so as to protrude from the bump pads, and having grooves for increasing area on a surface thereof, the semiconductor chip. A substrate having an external connection terminal bonded to the semiconductor chip and electrically connected to the semiconductor chip, and having bonding pads formed to correspond to the bumps among upper surfaces electrically connected to the external connection terminals and bonded to the semiconductor chip; And a molding structure covering an upper surface of the substrate including the semiconductor chip to protect the semiconductor chip from an external environment.

In addition, the method of manufacturing a semiconductor package for implementing the object of the present invention comprises the steps of forming bumps protruding on the bump pad disposed on the lower surface of the semiconductor chip, forming grooves for increasing the area on the surface of the bumps, Positioning the bumps and the bonding pads on the upper surface of the substrate corresponding to the bumps so as to face the lower surface of the semiconductor chip, and connecting the bumps and the bonding pads to the upper surface of the substrate including the semiconductor chips. Forming a molding structure to protect the chip.

Hereinafter, a semiconductor package and a method of manufacturing the same according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a cross-sectional view of a semiconductor package according to the present invention, and FIG. 2 is an enlarged view of an enlarged portion A of FIG. 1.

1 and 2, the semiconductor package 200 according to the present invention includes a semiconductor chip 100, a bump 110 having an area increasing groove, a substrate 120, an underfill unit 130, and a molding structure ( 140 and a solder ball 150 which is an external connection terminal.

A plurality of bump pads 102 are arranged on the bottom surface of the semiconductor chip 100, that is, the surface facing the substrate 120 when the semiconductor chip 100 is mounted, and the area increases on each bump pad 102. Bumps 110 having dragon grooves 112 are disposed. Here, the bumps 110 protrude from the bump pads 102 because they are formed at a predetermined height.

Preferably, the bump 110 is formed of gold and is a stud bump having a diamond shape or a ball shape shown in FIG. 2.

The above-described area increasing grooves 112 are formed at a predetermined depth on the surface of the bump 110, and their shapes and depths are not the same and are irregularly formed. For example, the area increasing groove 112 is formed using a fine needle, or in another example using a laser. Or by corroding the surface of the bumps.

Preferably, the area increasing grooves 112 are formed only to a point up to 2/3 from the bottom surface of the bumps 110 toward the bump pad 102. If the area-increasing grooves 112 are formed at a point more than two-thirds toward the bump pad 102, the solder 124, which will be described later, rises to the vicinity of the bump pad 102 and spreads laterally to form another adjacent bump pad 102. ) May be electrically shorted or may damage other areas of the semiconductor chip 100.

The semiconductor chip 100 having the bumps 110 disposed thereon is bonded to the substrate 120 by a flip chip method, and the bonding pads 122 are disposed on the upper surface on which the semiconductor chips 100 are mounted to correspond to the bumps 110. Are formed. Preferably, a solder 124 is coated on the upper surface of the bonding pad 122 to stably connect the bonding pad 122 and the bump 110.

Meanwhile, ball lands 126 to which solder balls 150 used as external connection terminals of the semiconductor package 200 are attached are formed on the lower surface of the substrate 120, and the ball lands 126 are circuit patterns (not shown). And vias (not shown) to electrically connect the bonding pads 122.

The underfill unit 130 is formed in the gap generated between the bottom surface of the semiconductor chip 100 and the substrate 120 by the connection of the bumps 110 and the bonding pads 122 and the interconnection pads 122 and It secures the bumps 110 and protects them from the external environment.

The molding structure 140 covers the upper surface of the substrate 120 including the semiconductor chip 100 to protect the semiconductor chip 100 from an external environment. The molding structure 140 is formed of an epoxy molding compound resin.

Forming a large number of area increasing grooves 112 on the surface of the bump 110 as in the present invention, the bonding pads 122 and bumps 120 by the solder 124 as shown in FIG. When the solders are bonded, the solder 124 flows into each of the area increasing grooves 112, resulting in an increase in the connection area between the solder 124 and the bumps 110.

A method of manufacturing a semiconductor package according to the present invention will be described with reference to FIGS. 1 to 6 as follows.

3 is a cross-sectional view showing a process of forming a bump on a semiconductor chip according to the present invention.

Referring to FIG. 3, a bump 110 having a predetermined height is formed on the bump pad 102 arranged on the bottom surface of the semiconductor chip 100. Preferably, bump 110 is formed of gold and is a stud bump having a diamond shape or a ball shape.

FIG. 4 is a cross-sectional view illustrating an area increasing groove formed on a surface of the bump illustrated in FIG. 3.

Referring to FIG. 4, after the bumps 110 are formed on the bottom surface of the semiconductor chip 100, the grooves 112 for increasing an area having a predetermined depth are formed on the surface of the bumps 110 as much as possible. Its shape and depth are not the same and are formed irregularly.

For example, heat and pressure are applied to the fine needles to form the surface 112 for increasing the surface of the bumps 110. As another example, a laser having a temperature of melting gold is irradiated onto the surface of the bump 110 to form a groove 112 for increasing an area. In another example, the bump 110 is immersed in a solution that corrodes gold to a certain portion to form the groove 112 for increasing the area on the surface of the bump 110.

Preferably, the area increasing grooves 112 are formed only to a point up to 2/3 from the bottom surface of the bumps 110 toward the bump pad 102. When the area increasing grooves 112 are formed at a point higher than about 2/3 toward the bump pad 102, a flip chip bonding process, that is, a semiconductor chip 100 having the bumps 110 formed thereon, is formed on the substrate 120. In the mounting process, the solder 124 may rise to the vicinity of the bump pad 102 and spread laterally to be connected to other adjacent bump pads 102 to electrically short or damage other regions of the semiconductor chip 100.

FIG. 5 is a cross-sectional view illustrating the semiconductor chip shown in FIG. 4 attached to a substrate.

When bumps 110 having an area increasing groove 112 are formed on the bottom surface of the semiconductor chip 100, the bottom surface of the semiconductor chip 100 on which the bumps 110 are formed is formed as a substrate (as shown in FIG. 5). The semiconductor chip 100 is mounted on the upper surface of the substrate 120 by positioning the upper surface of the substrate 120 to face the flip chip bonding process.

In more detail, the semiconductor chip 100 and the substrate 120 are introduced into a bonding facility having a high temperature at a temperature higher than the melting temperature of the solder 124 applied on the bonding pad 122, and then the semiconductor chip 100 and the substrate 120. Align 120. Then, bumps 110 formed on the bottom surface of the semiconductor chip 100 are positioned on the respective bonding pads 122 formed on the top surface of the substrate 120.

Thereafter, a predetermined pressure is applied to the upper portion of the semiconductor chip 100. Then, the bump 110 of the semiconductor chip 100 is introduced into the molten solder 124 at a high temperature, and the solder is spread laterally by solder wetting of the solder to the bonding pad 122 and the bump. Bonding pad 122 and bump 110 are connected to surround 110. At this time, the solder 124 melted in a liquid state as shown in FIG. 2 is introduced into the area increasing groove 112 formed on the surface of the bump 110 to fill the area increasing groove 112 and the solder 124. ) And the connection area of the bump 110 is increased, so that the bump 110 is firmly attached to the bonding pad 122.

6 is a cross-sectional view of the underfill portion formed between the semiconductor chip and the substrate according to the present invention.

Referring to FIG. 6, the gap formed between the bottom surface of the semiconductor chip 100 and the substrate 120 is filled with the bumps 110 and the bonding pads 122, and the underfill resin is filled with the underfill resin. Hardening to form an underfill unit 130 between the semiconductor chip 100 and the substrate 120. The underfill 130 firmly secures the interconnecting bonding pads 122 and bumps 110 and protects them from the external environment.

When the underfill portion is formed, the molding process is performed as shown in FIG. 1, the entire surface of the substrate 120 including the semiconductor chip 100 is covered with an epoxy molding compound resin, and the epoxy molding compound resin is cured to seal the sealing structure. 140 is formed. Finally, the solder ball 150 used as an external connection terminal is placed on the ball land 126 formed on the lower surface of the substrate 120, and then the solder ball 150 is viewed through the reflow process. It connects to 136, and manufacture of the semiconductor package 200 by this invention is completed.

As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

As described in detail above, when the groove for increasing the area is formed on the surface of the bump, the connection area between the bump and the solder is increased, thereby improving the connection reliability between the bump and the bonding pad.

Claims (7)

A semiconductor chip having bump pads formed on one surface thereof; Bumps formed on the bump pad so as to protrude from the bump pads and having grooves for increasing area on a surface thereof; The semiconductor chip is bonded and has external connection terminals electrically connected to the semiconductor chip, and bonding pads are formed to correspond to the bumps of upper surfaces electrically connected to the external connection terminals and bonded to the semiconductor chip. Formed substrate; And A molding structure covering an upper surface of the substrate including the semiconductor chip to protect the semiconductor chip from an external environment; Semiconductor package comprising a. The method of claim 1, And the area increasing grooves are formed up to two thirds from the lower surface of the bumps to the upper surface of the bumps. The method of claim 1, And a solder is applied on the bonding pads to connect the bonding pads and the bumps. Forming bumps on the bump pads disposed on the bottom surface of the semiconductor chip; Forming grooves for increasing area in the surfaces of the bumps; Connecting the bumps and the bonding pads after positioning the lower surface of the semiconductor chip to face the upper surface of the substrate on which the bonding pads are formed corresponding to the bumps; And Forming a molding structure for protecting the semiconductor chip on an upper surface of the substrate including the semiconductor chip; Semiconductor package manufacturing method comprising a. The method of claim 4, wherein And the area increasing grooves are formed in the upper surface of the bumps up to two thirds from the lower surface of the bumps. The method of claim 4, wherein The method of manufacturing a semiconductor package, characterized in that the solder is applied on the bonding pads connecting the bonding pad and the bump. The method of claim 4, wherein And the area increasing grooves are formed by any one of a needle, a laser, and surface corrosions.
KR1020060137184A 2006-12-28 2006-12-28 Semiconductor package and method for manufacturing semiconductor package KR20080061969A (en)

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KR1020060137184A KR20080061969A (en) 2006-12-28 2006-12-28 Semiconductor package and method for manufacturing semiconductor package

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9252076B2 (en) 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9691745B2 (en) 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
US10643931B2 (en) 2016-09-02 2020-05-05 Samsung Display Co., Ltd. Semiconductor chip, electronic device including the same, and method of connecting the semiconductor chip to the electronic device

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9691745B2 (en) 2013-06-26 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure for forming a package on package (PoP) structure and method for forming the same
US10109618B2 (en) 2013-06-26 2018-10-23 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding structure between semiconductor device package
US9252076B2 (en) 2013-08-07 2016-02-02 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9543284B2 (en) 2013-08-07 2017-01-10 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US10643931B2 (en) 2016-09-02 2020-05-05 Samsung Display Co., Ltd. Semiconductor chip, electronic device including the same, and method of connecting the semiconductor chip to the electronic device

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