KR100818090B1 - Semiconductor package - Google Patents

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KR100818090B1
KR100818090B1 KR1020060092535A KR20060092535A KR100818090B1 KR 100818090 B1 KR100818090 B1 KR 100818090B1 KR 1020060092535 A KR1020060092535 A KR 1020060092535A KR 20060092535 A KR20060092535 A KR 20060092535A KR 100818090 B1 KR100818090 B1 KR 100818090B1
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semiconductor chip
base substrate
bumps
semiconductor
spacer block
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KR1020060092535A
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Korean (ko)
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KR20080027081A (en
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박명근
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주식회사 하이닉스반도체
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

반도체 칩이 베이스 기판에 실장될 때 반도체 칩에 배열된 범프들이 베이스 기판에 형성된 본딩패드에 직접적으로 접촉되는 것을 방지하는 반도체 패키지가 개시되어 있다. 개시된 본 발명에 의한 반도체 패키지는 이와 같은 본 발명의 목적을 구현하기 위한 반도체 패키지는 일면에 배열된 복수개의 패드들 및 각각의 패드들에 접속되는 범프들을 포함하는 반도체 칩, 반도체 칩이 실장되며, 반도체 칩이 실장되는 상부면에 형성되고 범프들이 접속되는 본딩패드들, 본딩패드들 상에 도포되어 본딩패드 및 범프를 연결시키는 접속부재 및 외부 접속 단자를 포함하는 베이스 기판, 반도체 칩 및 베이스 기판 사이에 배치되어 반도체 칩의 범프들이 베이스 기판의 본딩패드에 직접 접촉되는 것을 방지하는 스페이서 블럭, 스페이서 블럭이 배치된 부분을 제외한 반도체 칩 및 상기 베이스 기판 사이에 충진되는 언더필부 및 반도체 칩을 포함한 베이스 기판의 상부면을 덮어 반도체 칩을 외부환경으로부터 보호하는 몰딩부를 포함한다.A semiconductor package is disclosed which prevents bumps arranged on a semiconductor chip from directly contacting a bonding pad formed on a base substrate when the semiconductor chip is mounted on a base substrate. In the semiconductor package according to the present invention disclosed herein, a semiconductor package for realizing the object of the present invention includes a semiconductor chip and a semiconductor chip including a plurality of pads arranged on one surface and bumps connected to the respective pads. Bonding pads formed on the upper surface on which the semiconductor chip is mounted and connected to bumps, a base substrate including a connection member and external connection terminals applied on the bonding pads to connect the bonding pads and bumps, between the semiconductor chip and the base substrate. A base substrate including a semiconductor block and an underfill portion filled between the semiconductor chip and the base substrate except for a portion where the spacer block is disposed, the spacer block preventing the bumps of the semiconductor chip from directly contacting the bonding pads of the base substrate. Covering the upper surface of the mold to protect the semiconductor chip from the external environment The.

Description

반도체 패키지{SEMICONDUCTOR PACKAGE}Semiconductor Package {SEMICONDUCTOR PACKAGE}

도 1은 종래에 의한 반도체 칩의 범프들이 본딩패드에 직접 접촉되어 패드에 크랙이 발생된 상태를 나타낸 단면도이다.1 is a cross-sectional view illustrating a state in which bumps of a semiconductor chip according to the related art are in direct contact with a bonding pad and cracks are generated in the pad.

도 2는 본 발명에 의한 베이스 기판 상에 스페이서가 부착된 상태를 나타낸반도체 칩이 실장된 상태를 나타낸 단면도이다.2 is a cross-sectional view showing a semiconductor chip mounted on the base substrate according to the present invention.

도 3a는 도 2의 스페이서의 상부에 반도체 칩이 배치되고 플립칩 방식으로 베이스 기판에 실장된 상태를 나타낸 단면도이다.3A is a cross-sectional view illustrating a semiconductor chip disposed on the spacer of FIG. 2 and mounted on a base substrate by a flip chip method.

3b는 도 3a의 A부분을 확대한 확대도이다.3B is an enlarged view enlarging part A of FIG. 3A.

도 4는 본 발명에 의한 반도체 패키지의 단면도이다.4 is a cross-sectional view of a semiconductor package according to the present invention.

본 발명은 반도체 패키지에 관한 것으로, 더욱 상세하게는 반도체 칩의 패드에 크랙 발생을 방지시키는 반도체 패키지에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package, and more particularly, to a semiconductor package that prevents crack generation on pads of a semiconductor chip.

반도체 산업에서 반도체 패키지란 일반적으로 미세회로가 설계된 반도체 칩을 외부환경으로부터 보호하고 전자기기에 실장하여 사용할 수 있도록 몰드 수지나 세라믹 등으로 밀봉한 형태를 말한다. 최근에는 반도체 칩을 감싸 보호하거나 단순 히 전자기기에 실장하기 위한 목적으로 반도체 칩을 패키징하기보다는 전자기기의 소형화, 박형화 및 다기능화를 통해 전자기기의 성능 및 품질을 향상시키기 위한 목적으로 반도체 칩을 패키징하고 있다. 따라서, 반도체 패키지의 중요성이 커지고 있다.In the semiconductor industry, a semiconductor package generally refers to a form in which a semiconductor chip, in which a microcircuit is designed, is sealed with a mold resin or ceramic so as to be protected from an external environment and mounted on an electronic device. In recent years, semiconductor chips have been used for the purpose of improving the performance and quality of electronic devices through miniaturization, thinning, and multifunctionality of electronic devices, rather than packaging semiconductor chips for the purpose of enclosing, protecting, or simply mounting electronic devices. I'm packaging. Therefore, the importance of semiconductor packages is increasing.

이러한, 전자기기의 소형화, 박형화 및 다기능화의 요구에 따라 반도체 패키지의 크기가 반도체 칩의 약 100% 내지 120%에 불과한 플립칩 방식의 BGA((Ball Grid Array)패키지가 개발되고 있다.In accordance with the demand for miniaturization, thinning, and multifunction of electronic devices, flip chip type ball grid array (BGA) packages having a semiconductor package size of about 100% to 120% of semiconductor chips have been developed.

플립칩 방식의 BGA 패키지는 일면에 범프들이 배열된 반도체 칩, 반도체 칩의 범프들과 접속되는 본딩패드들이 인쇄되며 반도체 칩이 실장되는 베이스 기판, 반도체 칩 및 베이스 기판 사이에 충진되어 반도체 칩을 지지하는 언더필부 및 반도체 칩을 덮어 외부환경으로부터 보호하는 밀봉부를 포함한다.The flip chip type BGA package supports a semiconductor chip in which bumps are arranged on one surface, bonding pads connected to bumps of the semiconductor chip, and is filled between the base substrate on which the semiconductor chip is mounted, the semiconductor chip, and the base substrate. And an underfill portion and a sealing portion covering the semiconductor chip to protect it from the external environment.

여기서, 반도체 칩의 범프, 예를 들어 금으로 형성된 스터드 범프(stud bump)는 알루미늄으로 형성된 접속패드에 형성되며, 솔더가 도포된 본딩패드와 플립칩 방식에 의해 접속된다. 이를 좀더 언급하면, 반도체 칩을 베이스 기판에 얼라인시켜 반도체 칩의 스터드 범프들을 베이스 기판의 본딩패드들 상에 올려놓는다. 이후 베이스 기판의 하부에서 열을 가하여 본딩패드 상에 도포된 솔더를 녹이고, 반도체 칩의 상부에서는 소정의 압력을 가하면 녹은 솔더의 내부로 스터드 범프가 들어가 본딩패드와 접속된다.Here, bumps of semiconductor chips, for example, stud bumps formed of gold are formed on connection pads made of aluminum, and are connected to a bonding pad coated with solder by a flip chip method. More specifically, the semiconductor chip is aligned with the base substrate so that stud bumps of the semiconductor chip are placed on the bonding pads of the base substrate. Then, the solder applied on the bonding pad is melted by applying heat at the lower portion of the base substrate, and when a predetermined pressure is applied at the upper portion of the semiconductor chip, stud bumps enter the molten solder and are connected to the bonding pad.

그러나, 도 1에 도시된 바와 같이 반도체 칩의 상부에서 가해지는 압력을 포함한 여러가지 공정 변수에 의해 용융된 솔더(51)의 내부로 스터드 범프(53)가 너 무 깊이 들어갈 경우 스터드 범프(53)가 본딩패드(50)에 부딪치게 되며, 그 충격에 의해 금으로 형성된 스터드 범프(53)보다 상대적으로 강도가 약한 접속패드(5)에 크랙이 발생되어 제품의 신뢰성을 저하시키는 문제점이 있다.However, as shown in FIG. 1, when the stud bumps 53 are too deeply inserted into the molten solder 51 due to various process variables including the pressure exerted on the upper portion of the semiconductor chip, the stud bumps 53 are formed. The impact on the bonding pads 50 may cause cracks in the connection pads 5 having a relatively weaker strength than the stud bumps 53 formed of gold, thereby degrading reliability of the product.

이를 해결하기 위해 종래에는 스터드 범프(53)의 크기 및 여러가지 공정 변수 등을 변경하고 있지만 그래도 상술한 문제점이 빈번하게 발생된다.In order to solve this problem, the size of the stud bump 53 and various process variables are changed in the related art, but the above-described problems are frequently generated.

따라서, 본 발명은 이와 같은 종래 문제점을 감안한 것으로서, 본 발명의 목적은 베이스 기판에 반도체 칩을 실장할 때 반도체 칩의 범프가 본딩패드에 접촉되지 않도록 하여 범프가 형성되는 접속패드에 크랙이 발생되는 것을 방지한 반도체 패키지를 제공한다.Accordingly, the present invention has been made in view of such a conventional problem, and an object of the present invention is to prevent a bump of a semiconductor chip from contacting a bonding pad when a semiconductor chip is mounted on a base substrate, thereby causing cracks in a connection pad where bumps are formed. The semiconductor package which prevented it is provided.

이와 같은 본 발명의 목적을 구현하기 위한 반도체 패키지는 일면에 배열된 복수개의 패드들 및 각각의 패드들에 접속되는 범프들을 포함하는 반도체 칩, 반도체 칩이 실장되며, 반도체 칩이 실장되는 상부면에 형성되고 범프들이 접속되는 본딩패드들, 본딩패드들 상에 도포되어 본딩패드 및 범프를 연결시키는 접속부재 및 외부 접속 단자를 포함하는 베이스 기판, 반도체 칩 및 베이스 기판 사이에 배치되어 반도체 칩의 범프들이 베이스 기판의 본딩패드에 직접 접촉되는 것을 방지하는 스페이서 블럭, 스페이서 블럭이 배치된 부분을 제외한 반도체 칩 및 상기 베이스 기판 사이에 충진되는 언더필부 및 반도체 칩을 포함한 베이스 기판의 상부면을 덮어 반도체 칩을 외부환경으로부터 보호하는 몰딩부를 포함한다.The semiconductor package for realizing the object of the present invention is a semiconductor chip including a plurality of pads arranged on one surface and bumps connected to the respective pads, the semiconductor chip is mounted, on the upper surface on which the semiconductor chip is mounted Bumps of the semiconductor chip formed between the semiconductor substrate and the base substrate including the bonding pads formed and the bumps to which the bumps are connected, a connection member coated on the bonding pads to connect the bonding pad and the bump, and an external connection terminal. The semiconductor chip is covered by covering a top surface of the base substrate including a spacer block to prevent direct contact with a bonding pad of the base substrate, a semiconductor chip except a portion where the spacer block is disposed, and an underfill portion and a semiconductor chip filled between the base substrate. It includes a molding to protect from the external environment.

바람직하게, 본딩패드 상에 도포된 상기 접속부재는 솔더이다. Preferably, the connection member applied on the bonding pad is solder.

바람직하게, 스페이서 블럭의 높이는 패드의 높이와 범프의 높이를 합한 높이보다 높게 형성된다.Preferably, the height of the spacer block is formed higher than the sum of the height of the pad and the height of the bump.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들에 따른 반도체 패키지에 대하여 상세하게 설명한다. Hereinafter, a semiconductor package according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

반도체 패키지Semiconductor package

실시예Example 1 One

도 2 내지 도 4는 본 발명에 의한 반도체 패키지의 제조 공정을 설명하기 위한 공정 순서도로, 도 4는 본 발명에 의한 반도체 패키지의 단면도이다.2 to 4 are process flowcharts for explaining the manufacturing process of the semiconductor package according to the present invention, and FIG. 4 is a cross-sectional view of the semiconductor package according to the present invention.

도 4를 참조하면, 본 발명에 의한 반도체 패키지(1)는 반도체 칩(10), 베이스 기판(100), 스페이서 블럭(200), 언더필부(210) 및 몰딩부(220)를 포함한다.Referring to FIG. 4, the semiconductor package 1 according to the present invention includes a semiconductor chip 10, a base substrate 100, a spacer block 200, an underfill unit 210, and a molding unit 220.

반도체 칩(10)의 일면, 즉, 반도체 칩(10)이 실장될 때 베이스 기판(100)과 마주보는 면에는 복수개의 패드(20)들이 배열되고, 각각의 패드(20)들 상에는 범프(30)들이 형성된다. 바람직하게, 패드(20)는 알루미늄으로 형성되고, 범프(30)는 금으로 형성되며 다이아몬드 형상을 갖는 스터드 범프(stud bump)이다.A plurality of pads 20 are arranged on one surface of the semiconductor chip 10, that is, a surface facing the base substrate 100 when the semiconductor chip 10 is mounted, and bumps 30 are formed on the respective pads 20. ) Are formed. Preferably, the pad 20 is made of aluminum and the bump 30 is made of gold and is a stud bump having a diamond shape.

베이스 기판(100)에는 플립칩 방식에 의해 반도체 칩(10)이 실장되며, 반도체 칩(10)이 실장되는 상부면에는 범프(30; 이하, "스터드 범프"라함)들과 전기적으로 연결되는 본딩패드(120)들이 형성되는데, 본딩패드(120)들은 반도체 칩(10)에서 스터드 범프(30)들이 형성된 방향과 동일한 방향으로 배열된다. 그리고, 본딩패드(120)들 상에는 본딩패드(120) 및 스터드 범프(30)를 전기적으로 연결시키는 접 속부재(130)가 형성된다. 바람직하게, 접속부재(130)는 솔더이다.The semiconductor chip 10 is mounted on the base substrate 100 by a flip chip method, and a bonding is electrically connected to bumps 30 (hereinafter referred to as “stud bumps”) on an upper surface on which the semiconductor chip 10 is mounted. The pads 120 are formed, and the bonding pads 120 are arranged in the same direction as the direction in which the stud bumps 30 are formed in the semiconductor chip 10. And, on the bonding pads 120, a connection member 130 for electrically connecting the bonding pads 120 and the stud bumps 30 is formed. Preferably, the connecting member 130 is solder.

그리고, 베이스 기판(100)의 하부면에는 반도체 패키지(1)의 외부 접속 단자로 사용되는 솔더볼(230)이 부착되는 볼 랜드(140)들이 형성되는데, 볼 랜드(140)들은 비아홀(도시 안됨)에 의해 본딩패드(120)들과 전기적으로 연결된다.In addition, ball lands 140 to which solder balls 230 used as external connection terminals of the semiconductor package 1 are attached are formed on the lower surface of the base substrate 100, and the ball lands 140 are via holes (not shown). It is electrically connected to the bonding pads 120 by.

스페이서 블럭(200)은 반도체 칩(10)의 스터드 범프(30)들이 본딩패드(120)에 접속될 때 반도체 칩(10)의 스터드 범프(30)가 본딩패드(120)에 직접적으로 접촉되는 것을 방지하기 위한 것으로, 도 2에 도시된 바와 같이 접착부재(101)에 의해 베이스 기판(100)의 상부면에 직접 부착된다. 도시되지는 않았지만, 스페이서 블럭(200)을 베이스 기판(100)의 상부면에 부착시키기 않고, 스터드 범프(30)들이 배열된 반도체 칩(10)의 하부면에 부착시켜도 무방하다.The spacer block 200 may allow the stud bumps 30 of the semiconductor chip 10 to directly contact the bonding pads 120 when the stud bumps 30 of the semiconductor chip 10 are connected to the bonding pads 120. To prevent this, as shown in FIG. 2, the adhesive member 101 is directly attached to the upper surface of the base substrate 100. Although not shown, the spacer block 200 may be attached to the lower surface of the semiconductor chip 10 on which the stud bumps 30 are arranged without attaching the spacer block 200 to the upper surface of the base substrate 100.

반도체 칩(10)을 베이스 기판(100) 상에 실장할 때 반도체 칩(10)의 스터드 범프(30)들이 베이스 기판(100)의 본딩패드(120)에 직접적으로 접촉되지 않도록 하기 위해서는 도 3a에 도시된 바와 같이 패드(20)의 높이와 스터드 범프(30)의 높이를 합한 높이(ℓ´)보다 스페이서 블럭(200)의 높이(ℓ)가 더 높아야 한다.When the semiconductor chip 10 is mounted on the base substrate 100, the stud bumps 30 of the semiconductor chip 10 do not directly contact the bonding pads 120 of the base substrate 100. As shown, the height l of the spacer block 200 must be higher than the height l ', which is the sum of the height of the pad 20 and the height of the stud bumps 30.

이와 같이 스페이서 블럭(200)부의 높이(ℓ)를 패드의 높이와 범프의 높이를 합한 높이(ℓ´)보다 높게 형성하면, 스페이서 블럭(200)의 높이(ℓ)에 의해 반도체 칩(10)의 스터드 범프(30)가 본딩패드(120)까지 파고 들어가지 못하고, 도 3b에 도시된 바와 같이 스터드 범프(30)와 본딩패드(120) 사이에 갭이 발생된다. As such, when the height l of the spacer block 200 is formed higher than the height l ′ of the sum of the height of the pad and the height of the bump, the height of the spacer block 200 increases the height of the semiconductor chip 10. The stud bumps 30 do not penetrate into the bonding pads 120, and a gap is generated between the stud bumps 30 and the bonding pads 120 as illustrated in FIG. 3B.

언더필부(210)는 스페이서 블럭(200)이 배치된 부분을 제외한 반도체 칩(10) 및 베이스 기판(100) 사이의 빈 공간에 충진되어 반도체 칩(10)을 베이스 기 판(100)의 상부면에 견고히 고정시키며 반도체 칩(10)을 지지한다.The underfill portion 210 is filled in an empty space between the semiconductor chip 10 and the base substrate 100 except for the portion where the spacer block 200 is disposed, so that the semiconductor chip 10 is formed on the upper surface of the base substrate 100. The semiconductor chip 10 is firmly fixed to the semiconductor chip 10.

바람직하게, 언더필부(210)는 스페이서 블럭(200)과 동일한 물질로 형성되며, 그 물질은 에폭시 몰딩 컴파운드 수지이다.Preferably, the underfill portion 210 is formed of the same material as the spacer block 200, and the material is an epoxy molding compound resin.

마지막으로, 몰딩부(220)는 반도체 칩(10)을 포함한 베이스 기판(100)의 상부면을 덮어 반도체 칩(10)을 외부환경으로부터 보호하며, 몰딩부(220)는 에폭시 몰딩 컴파운드 수지를 이용하여 형성하는 것이 가장 바람직하다.Finally, the molding part 220 covers the upper surface of the base substrate 100 including the semiconductor chip 10 to protect the semiconductor chip 10 from the external environment, and the molding part 220 uses an epoxy molding compound resin. It is most preferable to form.

반도체 패키지 제조 방법Semiconductor Package Manufacturing Method

도 2 내지 도 4를 참조하여 본 발명에 의한 반도체 패키지 제조 방법에 대해 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor package according to the present invention will be described with reference to FIGS. 2 to 4.

도 2는 본 발명에 의한 베이스 기판 상에 스페이서가 부착된 상태를 나타낸 단면도로, 베이스 기판(100)의 상부면 중앙부분에 에폭시 계열의 접착부재(101)를 도포하고, 접착부재(100)의 상부면에 스페이서 블럭(200)을 부착한다. 여기서, 스페이서 블럭(200)의 높이(ℓ)는 반도체 칩(10)의 패드(20) 높이와 스터드 범프(30) 높이를 합한 높이(ℓ´)보다 높게 형성한다. 2 is a cross-sectional view showing a state in which a spacer is attached on the base substrate according to the present invention, the epoxy-based adhesive member 101 is applied to the central portion of the upper surface of the base substrate 100, the adhesive member 100 The spacer block 200 is attached to the upper surface. Herein, the height l of the spacer block 200 is formed to be higher than the height l ′ of the sum of the height of the pad 20 and the height of the stud bumps 30 of the semiconductor chip 10.

도 3a는 도 2의 스페이서의 상부에 반도체 칩이 배치되고 플립칩 방식으로 베이스 기판에 실장된 상태를 나타낸 단면도이며, 도 3b는 도 3a의 A부분을 확대한 확대도이다.3A is a cross-sectional view illustrating a state in which a semiconductor chip is disposed on a spacer of FIG. 2 and mounted on a base substrate in a flip chip manner, and FIG. 3B is an enlarged view illustrating part A of FIG. 3A.

도 3a를 참조하면, 스페이서 블럭(200)의 상부면에 에폭시 계열의 접착부재(201)를 도포하고, 접착부재(201)의 상부면에 스터드 범프(30)들이 배열된 반도 체 칩(10)의 하부면을 위치시킨 후 반도체 칩(10)을 스페이서 블럭(200)의 상부면에 부착시킴과 아울러 플립칩 방식으로 반도체 칩(10)의 스터드 범프(30)들을 각각의 본딩패드(120)들에 연결시킨다. Referring to FIG. 3A, a semiconductor chip 10 having an epoxy-based adhesive member 201 applied to an upper surface of a spacer block 200 and stud bumps 30 arranged on an upper surface of the adhesive member 201 is illustrated. After positioning the bottom surface of the semiconductor chip 10 is attached to the upper surface of the spacer block 200, and the stud bumps 30 of the semiconductor chip 10 in a flip chip method to each of the bonding pads 120 To.

이를 좀더 상세히 설명하면, 베이스 기판(100)의 하부에서 접속부재(130)인 솔더가 녹는 온도 이상의 열을 가한 후에 반도체 칩(10)을 베이스 기판(100)에 얼라인시킨다. 그러면, 반도체 칩(10)의 하부면에 배열된 스터드 범프(30)들이 베이스 기판(100)의 상부면에 형성된 각각의 본딩패드(120)들 상에 위치한다. In more detail, the semiconductor chip 10 is aligned with the base substrate 100 after applying heat above the melting temperature of the solder, which is the connection member 130, under the base substrate 100. Then, stud bumps 30 arranged on the bottom surface of the semiconductor chip 10 are positioned on the respective bonding pads 120 formed on the top surface of the base substrate 100.

이후, 반도체 칩(10)의 상부에서 소정의 압력을 가하여 반도체 칩(10)을 스페이서 블럭(200)의 상부면에 접착시킨다. 그러면, 반도체 칩(10)의 스터드 범프(30)가 반도체 칩(10)에 가해지는 압력에 의해 용융된 접속부재(130)의 내부로 파고든다. 그러나, 종래와 다르게 본 발명에서는 반도체 칩(10)의 패드(20) 높이와 스터드 범프(30) 높이를 합한 높이(ℓ´)보다 높게 형성된 스페이서 블럭(200)이 반도체 칩(10)과 베이스 기판(100) 사이에 배치되어 있기 때문에 반도체 칩(10)의 상부면에서 과도한 압력이 가해져도 스터드 범프(30)가 접속부재(130)를 파고 들어갈 수 있는 깊이는 한정되어 있다. 따라서, 도 3b에 도시된 바와 같이 반도체 칩(10)의 스터드 범프(30)와 본딩패드(120) 사이에는 갭이 발생되고, 이로 인해 스터드 범프(30)는 본딩패드(120)에 직접적으로 접촉되지 못한다. 즉, 스터드 범프(30)가 본딩패드(120)에 부딪치는 충격에 의해 상대적으로 강도가 약한 패드(130)가 깨지는 것을 방지할 수 있다.Thereafter, a predetermined pressure is applied on the upper portion of the semiconductor chip 10 to bond the semiconductor chip 10 to the upper surface of the spacer block 200. Then, the stud bumps 30 of the semiconductor chip 10 dig into the molten connection member 130 by the pressure applied to the semiconductor chip 10. However, unlike the prior art, in the present invention, the spacer block 200 formed higher than the sum of the height of the pad 20 and the height of the stud bumps 30 of the semiconductor chip 10 (l ′) is the semiconductor chip 10 and the base substrate. Since it is disposed between the (100), even if excessive pressure is applied from the upper surface of the semiconductor chip 10, the depth that the stud bump 30 can penetrate the connection member 130 is limited. Accordingly, as shown in FIG. 3B, a gap is generated between the stud bump 30 and the bonding pad 120 of the semiconductor chip 10, which causes the stud bump 30 to directly contact the bonding pad 120. I can't. That is, it is possible to prevent the pads 130 having relatively low strength from being broken by the impact of the stud bumps 30 hitting the bonding pads 120.

상술한 바와 같이 플립칩 방식에 의해 반도체 칩(10)이 베이스 기판(100) 상 에 실장되면, 반도체 칩(10) 및 베이스 기판(100) 사이에 발생된 빈 공간에 에폭시 몰딩 컴파운드 수지를 채워 넣고 이를 경화시켜 반도체 칩(10)을 베이스 기판(100)의 상부면에 견고히 고정시키고 반도체 칩(10)을 지지하는 언더필부를 형성한다. When the semiconductor chip 10 is mounted on the base substrate 100 by the flip chip method as described above, the epoxy molding compound resin is filled in the empty space generated between the semiconductor chip 10 and the base substrate 100. By hardening this, the semiconductor chip 10 is firmly fixed to the upper surface of the base substrate 100 and an underfill portion for supporting the semiconductor chip 10 is formed.

이후, 도 4에 도시된 바와 같이 몰딩공정을 진행하여 반도체 칩(10)을 포함한 베이스 기판(100)의 상부면에 전체를 에폭시 몰딩 컴파운드 수지로 감싸고, 에폭시 몰딩 컴파운드 수지를 경화시켜 밀봉부(220)를 형성한다. 그리고, 리플로우(reflow) 공정을 통해 베이스 기판(100)의 하부면에 형성된 볼 랜드(140)에 외부 접속 단자로 사용되는 솔더볼(230)을 접속시켜 본 발명에 의한 반도체 패키지(1)의 제조를 완료한다.Thereafter, as shown in FIG. 4, the molding process is performed to cover the entire surface of the base substrate 100 including the semiconductor chip 10 with an epoxy molding compound resin, and the epoxy molding compound resin is cured to seal the sealing unit 220. ). The solder ball 230 used as an external connection terminal is connected to the ball land 140 formed on the lower surface of the base substrate 100 through a reflow process to manufacture the semiconductor package 1 according to the present invention. To complete.

이상, 여기에서는 본 발명을 특정 실시예에 관련하여 도시하고 설명하였지만, 본 발명이 그에 한정되는 것은 아니며, 이하의 특허청구의 범위는 본 발명의 정신과 분야를 이탈하지 않는 한도 내에서 본 발명이 다양하게 개조 및 변형될 수 있다는 것을 당업계에서 통상의 지식을 가진 자가 용이하게 알 수 있다. As mentioned above, although the present invention has been illustrated and described with reference to specific embodiments, the present invention is not limited thereto, and the following claims are not limited to the scope of the present invention without departing from the spirit and scope of the present invention. It can be easily understood by those skilled in the art that can be modified and modified.

이상에서 상세하게 설명한 바와 같이 반도체 칩과 베이스 기판 사이에 반도체 칩의 패드 높이와 범프 높이를 합한 높이보다 높게 형성된 스페이서 블럭을 설치하면, 반도체 칩의 범프가 본딩패드에 직접 접촉되는 것을 방지할 수 있어 충격에 약한 패드에 크랙이 발생되는 것을 방지할 수 있는 효과가 있다.As described in detail above, if a spacer block formed between the semiconductor chip and the base substrate is formed higher than the sum of the pad height and the bump height of the semiconductor chip, the bumps of the semiconductor chip can be prevented from directly contacting the bonding pads. There is an effect that can prevent cracks in the pads susceptible to impact.

또한, 반도체 칩과 베이스 기판 사이에 설치된 스페이서 블럭에 의해 반도체 칩과 베이스 기판 사이에 빈 공간이 적게 발생됨으로써, 빈 공간을 채우는 수지의 사용량을 줄일 수 있고, 균일한 충진을 할 수 있어 제품의 신뢰성을 향상시킬 수 있다.In addition, since a small amount of empty space is generated between the semiconductor chip and the base substrate by the spacer block provided between the semiconductor chip and the base substrate, the amount of resin used to fill the empty space can be reduced, and uniform filling can be achieved. Can improve.

또한, 본 발명을 적용할 경우 몰딩공정에서 발생되는 휨을 최소화할 수 있다.In addition, when applying the present invention it is possible to minimize the warpage generated in the molding process.

Claims (5)

일면에 배열된 복수개의 패드들 및 각각의 상기 패드들에 접속되는 범프들을 포함하는 반도체 칩;A semiconductor chip including a plurality of pads arranged on one surface and bumps connected to the pads; 상기 반도체 칩이 실장되며, 상기 반도체 칩이 실장되는 상부면에 형성되고 상기 범프들이 접속되는 본딩패드들, 상기 본딩패드들 상에 도포되어 상기 본딩패드 및 상기 범프를 연결시키는 솔더 및 외부 접속 단자를 포함하는 베이스 기판;Bonding pads formed on an upper surface of the semiconductor chip, on which the semiconductor chip is mounted, to which the bumps are connected, and coated on the bonding pads to connect solder and external connection terminals. A base substrate comprising; 상기 반도체 칩 및 상기 베이스 기판 사이에 배치되어 상기 반도체 칩의 범프들이 상기 베이스 기판의 본딩패드에 직접 접촉되는 것을 방지하는 스페이서 블럭;A spacer block disposed between the semiconductor chip and the base substrate to prevent bumps of the semiconductor chip from directly contacting a bonding pad of the base substrate; 상기 스페이서 블럭이 배치된 부분을 제외한 상기 반도체 칩 및 상기 베이스 기판 사이에 충진되는 언더필부; 및An underfill portion filled between the semiconductor chip and the base substrate except for a portion where the spacer block is disposed; And 상기 반도체 칩을 포함한 상기 베이스 기판의 상부면을 덮어 상기 반도체 칩을 외부환경으로부터 보호하는 몰딩부를 포함하는 반도체 패키지.And a molding part covering an upper surface of the base substrate including the semiconductor chip to protect the semiconductor chip from an external environment. 삭제delete 제 1 항에 있어서, The method of claim 1, 상기 스페이서 블럭의 높이는 상기 패드의 높이와 상기 범프의 높이를 합한 높이보다 높은 것을 특징으로 하는 반도체 패키지.The height of the spacer block is a semiconductor package, characterized in that higher than the height of the height of the pad and the height of the bump. 제 1 항에 있어서, The method of claim 1, 상기 스페이서 블럭은 상기 언더필부와 동일한 물질로 형성되는 것을 특징으로 하는 반도체 패키지.The spacer block is formed of the same material as the underfill portion. 제 4 항에 있어서, The method of claim 4, wherein 상기 스페이서 블럭 및 상기 언더필부는 에폭시 몰딩 컴파운드 수지로 형성되는 것을 특징으로 하는 반도체 패키지.And the spacer block and the underfill portion are formed of an epoxy molding compound resin.
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US11315863B2 (en) 2019-10-22 2022-04-26 Samsung Electronics Co., Ltd. Package substrate and method of manufacturing the package substrate, and semiconductor package including the package substrate and method of manufacturing the semiconductor package

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KR19990069950A (en) * 1998-02-16 1999-09-06 윤종용 Flip chip bonding structure and manufacturing method of solder bump using same
JP2004235472A (en) * 2003-01-30 2004-08-19 Mitsubishi Electric Corp Semiconductor device manufacturing method

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Publication number Priority date Publication date Assignee Title
KR19990069950A (en) * 1998-02-16 1999-09-06 윤종용 Flip chip bonding structure and manufacturing method of solder bump using same
JP2004235472A (en) * 2003-01-30 2004-08-19 Mitsubishi Electric Corp Semiconductor device manufacturing method

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11315863B2 (en) 2019-10-22 2022-04-26 Samsung Electronics Co., Ltd. Package substrate and method of manufacturing the package substrate, and semiconductor package including the package substrate and method of manufacturing the semiconductor package
US11823995B2 (en) 2019-10-22 2023-11-21 Samsung Electronics Co., Ltd. Package substrate, and semiconductor package including the package substrate

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