KR20020054134A - Device for detecting errors of communication system and method for controlling the same - Google Patents

Abstract

PURPOSE: An error monitoring apparatus and its operating method are provided to easily detect a state of a processor and perform a warning function for an abnormal state to a processor operator by collecting and analyzing a message output through the processor of an exchange or a communication device. CONSTITUTION: An operator executes an operation program in a control system(S10). The operator sets information on a port installed in an error monitoring apparatus in the initial execution process of the operation program(S12). The operator monitors a processor inside an exchange by using the information set for each port of the error monitoring apparatus(S14), and stores a message output through each processor(S16). The operator analyzes the message output from the processor of the exchange to analyze a state of the processor in case that an error occurs(S18). The operator outputs the error message of the processor of the exchange or the analysis result through a screen(S20). In case that an error message occurs from the processor inside the exchange, the error message and a corresponding control method are provided to a manager of an exchange processor(S24). The operation program of the error monitoring apparatus has a function to control the exchange processor, so that the processor inside the exchange is controlled by the operation program in case that there is a request form the processor manager(S26).

Description

DEVICE FOR DETECTING ERRORS OF COMMUNICATION SYSTEM AND METHOD FOR CONTROLLING THE SAME}

The present invention relates to an exchange or a communication device, and more particularly, to an apparatus for monitoring an error of an exchange or a communication device and a method of operating the same.

Among the exchanges used for mobile communication, TDX (Time Division eXchange) series has a hierarchical structure of Inter Processor Communication (IPC) system, and OMP (Operation and Maintenance Processor), which is the highest processor, periodically processes all processors in the exchange. The state of the exchange is managed using the IPC signal.

In particular, the TDX-10 has the features and functions of a distributed system in terms of structure. This has the advantage that it can provide more stable and efficient service than the centralized system.

The TDX-10 uses IPC to exchange messages between multiple distributed processors. In order to achieve this, a CI (Control Interworking) block is in charge of IPC message exchange. The CI block is connected to each processor through the U-link.

Figure 1 shows a block diagram of the IPC structure of the TDX-10. Referring to FIG. 1, the IPC structure of the TDX-10 includes a basic module called an Inter Processor Communication Unit (IPCU), which accommodates CI blocks of a subsystem, and a Control Interworking Extender (CIE) block that is responsible for connection between IPCUs.

The IPCU accepts up to 26 CI blocks and exchanges IPC messages over the D-bus, a high-speed bus. The exchange of messages with other IPCUs is done through the CI block which is responsible for the gateway function. For example, two CI nodes for connecting to an Inter Inter Processor Communication Unit (IIPCU) are allocated to an ASS (Access Switching Subsystem) IPCU, and the remaining 24 CI nodes include processors such as an access switching processor (ASP), an ASIP, and a TSP. Each is redundantly connected.

The CIE block is composed of IIPCU and CIPCU (Central IPCU). The IIPCU is connected to ASS IPCU and CIPCU to handle IPC message exchange, and the structure is same as that of IPCU. Up to 11 IPCUs can be connected to the IIPCU. CIPUC accommodates up to five IIPCUs, two IPCUs (INS IPCUs, CCS IPCUs), and one Main Processor Hardware (MPH) block. Each IPCU, IIPCU and CIPCU has a CIPH (Control Interworking Processor Hardware) block, which is responsible for maintenance and repair of CI blocks, and exchanges maintenance-related messages through the M-bus.

This IPC message has a bit-oriented protocol structure. 2 shows a frame structure and an address of an IPC message used in a TDX-10 exchange.

The IPCU is hardwarely composed of an INDC (IPC Node Board Assembly), an IPC Management Processor Assembly (IMPA), an IPC Management Interface Assembly (IMIA), and an IPC Management Back Board (IMBB).

The INDA is a basic unit that constitutes an IPC node, and includes a buffer module, a frame address check (FAC) module, a multi-frame selector, a D-bus interface, an M-bus interface, a U-link interface, a node controller, Fault center, etc. IMPA monitors the CI status through the M-bus and is responsible for controlling and troubleshooting each node in the subsystem. IMIA collects alarm signals from up to 26 CI blocks and raises alarms to FI (Fault Interface) blocks. It monitors the tripled D-bus and provides a bus arbitration signal to the CI block. IMBB is equipped with 26 INDA, IMPA, two IMIA, two power packs, D-bus, M-bus, U-link and signal lines.

This structure has a problem in that if an abnormality occurs in the intermediate node, the lower nodes without any abnormality cannot operate normally. In order to solve this problem, the TDX-10 works by dualizing all IPC systems such as links and nodes between upper and lower nodes.

However, during the operation of the TDX-10, IPC transmission processing due to hardware failure and IPC transmission processing due to traffic jam rarely occur due to hardware failure at the intermediate node of the IPC system. The incapacity due to such hardware failure can be detected immediately by the current alarm system. However, in the case of incapacity due to the traffic jam, it is difficult to detect it and it is difficult to determine the location of the failure. Therefore, the operator may not recognize the occurrence of a failure for a long time may occur.

As such, serious problems such as processing delay or interruption of service have occurred due to a failure of the processor due to an unknown cause such as a processor down, abnormal state or state transition occurring while operating an exchange.

Until now, when the abnormal state of such a processor occurs, the problem has been solved by shutting down the processor, operating, resetting, or powering down / up to recover the problem. However, the reason for the failure is not clearly understood. Similar problems continue to arise.

This phenomenon is a problem that occurs not only in the TDX series switch but also in other communication devices.

The present invention is to solve the above problems, by analyzing the status of the message output through the port of the exchange or communication device, the exchange error monitoring device that can determine the cause of the transition to an abnormal state and the exchange or It is an object of the present invention to provide an operation method capable of pluralizing a communication device in a normal state.

Another object of the present invention is to provide an error monitoring device and a method of operating the same, which perform periodic tests on an exchange or a communication device and can preemptively handle errors and defects that may occur even without an administrator.

1 is a block diagram of an IPC structure of a TDX-10.

2 shows a frame structure and an address of an IPC message used in a TDX-10 exchange.

3 is an overall block diagram when using an error monitoring apparatus according to a preferred embodiment of the present invention.

4 is a block diagram of a centralized error monitoring apparatus according to a preferred embodiment of the present invention.

5 is an ISBB block diagram of an error monitoring apparatus according to a preferred embodiment of the present invention.

6A and 6B are diagrams showing signals used for CMIA in the error monitoring apparatus according to the preferred embodiment of the present invention.

7 is a RSIA block diagram of an error monitoring apparatus according to a preferred embodiment of the present invention.

8 is a block diagram of a receiving FPGA in RSIA in an error monitoring apparatus according to a preferred embodiment of the present invention.

9 is a view illustrating a selection signal for selecting eight FPGAs in an error monitoring apparatus according to a preferred embodiment of the present invention.

10 is a block diagram of a transmission FPGA in RSIA in the error monitoring apparatus according to the preferred embodiment of the present invention.

11 is a view illustrating a selection signal for performing a loop back function in a transmission FPGA in an error monitoring apparatus according to a preferred embodiment of the present invention.

12 is a diagram illustrating a state in which data is received according to a mode state in an error monitoring apparatus according to a preferred embodiment of the present invention.

13 is a diagram illustrating a memory map of a CMIA in the error monitoring apparatus according to the preferred embodiment of the present invention.

14A and 14B show an address of a port for double buffer 0 and double buffer 1, respectively, in an error monitoring apparatus according to a preferred embodiment of the present invention.

Fig. 15 is a diagram showing a memory map of DPRAM in the error monitoring apparatus according to the preferred embodiment of the present invention.

16 is a flowchart illustrating a method of operating an error monitoring apparatus according to a preferred embodiment of the present invention.

FIG. 17 is a view showing an initial screen when an operating program is executed in an operating method of an error monitoring apparatus according to a preferred embodiment of the present invention. FIG.

18A to 18C are screen diagrams illustrating a process of setting information on each port of an error monitoring apparatus through an operation program in the error monitoring apparatus operating method according to an exemplary embodiment of the present invention.

19A and 19B illustrate screen examples of a process of checking a message collected from a processor by an operator in a method of operating an error monitoring apparatus according to an exemplary embodiment of the present invention.

20A and 20B illustrate screen examples when an operator controls a processor in an operating method of an error monitoring apparatus according to a preferred embodiment of the present invention.

21A to 21E are diagrams illustrating an IPC log control screen in an operating method of an error monitoring apparatus according to a preferred embodiment of the present invention;

FIG. 22 is a diagram illustrating a screen when an operator monitors an input / output message in an operating method of an error monitoring apparatus according to a preferred embodiment of the present invention. FIG.

(Name of the code for the main part of the drawing)

100: exchange 200: error monitoring device

300: control system

In order to achieve the above object, the error monitoring apparatus of the present invention is matched with a processor or a subsystem in a communication device to perform asynchronous data transmission, and a matching unit for synchronizing the received data with an internal clock, and the matching unit; A control unit for receiving data and converting the data into a data format usable by the operator control system, a control system matching unit matching with the operator control system to perform asynchronous transmission of the data converted by the control unit with the operator control system, and a communication device. An operator control system may be configured to determine an error state according to output data of an internal processor or a subsystem and to transmit an alarm signal or a control signal to a communication device accordingly.

The matching unit may include an RS-232 interface unit having a plurality of RS-232 ports for asynchronous transmission with a communication device.

The RS-232 interface unit may include a plurality of receiving FPGAs for receiving data output from the communication device, and a transmission FPGA for transmitting data to the communication device.

The receiving FPGA includes a bit synchronization unit for retiming the received data in units of bits in each RS-232 port, and a start signal and a stop bit in the data synchronized through the bit synchronization unit to detect a byte synchronization signal. It may include a byte synchronizer for generating a.

The byte synchronizer may include a latch unit for latching input data for a predetermined time, and a converter for converting an order of data bits except start and stop bits from the data of the latch unit.

The FPGA for transmitting transmits a loop back test unit for testing a loop back function with respect to an RS-232 port, a monitor unit for monitoring the state of a clock signal and a frame synchronization signal of the receiving FPGA, and transmits RS-232 data to an exchange. It may include a transmission unit.

The control unit may include a memory unit for storing the data received from the matching unit, a buffer unit for buffering the received data before processing the data, and converting the data transmitted through the buffer unit into parallel data. It may include a data conversion unit for converting to the HDLC type used or RS-232 type used in the communication device.

The control system matching unit may include an RS-232 interface unit having a plurality of RS-232 ports for data transmission with an operator control system.

The RS-232 interface unit may include a plurality of receiving FPGAs for receiving data output from an operator control system, and a transmitting FPGA for transmitting data to an exchange.

The receiving FPGA includes a bit synchronization unit for retiming the received data in units of bits in each RS-232 port, and a start signal and a stop bit in the data synchronized through the bit synchronization unit to detect a byte synchronization signal. It may include a byte synchronizer for generating a.

The byte synchronizer may include a latch unit for latching input data for a predetermined time, and a converter for converting an order of data bits except start and stop bits from the data of the latch unit.

The transmitting FPGA includes a loop back test unit for testing a loop back function for an RS-232 port, a monitor unit for monitoring the state of clock signals and frame synchronization signals of a receiving FPGA, and an RS-232 data operator control system. It may include a transmission unit for transmitting to.

In addition, the operating method of the error monitoring device of the present invention comprises the steps of setting one or more port information provided in the error monitoring device respectively connected to a processor or a subsystem in the communication device, and corresponding communication device according to the set port information Receiving an output message of an internal processor or subsystem, analyzing the received message to analyze a state of a corresponding processor or subsystem, and alerting a processor or subsystem in which an error occurs according to the analysis result The method may include transmitting a message and controlling an operation of a processor or a subsystem in which an error occurs at the request of a processor or a subsystem manager.

The port information may include module information used for a port connected to a processor or a subsystem in a communication device and a corresponding port number.

Receiving an output message of a processor or subsystem within the communication device may further include storing the received message in a database.

Controlling the operation of the failed processor or subsystem may further include resetting the corresponding processor or subsystem.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Hereinafter, an apparatus for monitoring an error of an exchange and a method of operating the same will be described.

3 is a block diagram illustrating a case where an error monitoring apparatus according to a preferred embodiment of the present invention is used. Referring to FIG. 3, the error monitoring apparatus 200 of the present invention is connected to a switch 100 belonging to a TDX series or another series to receive and determine an output signal generated at an input / output port of the switch. In this case, when the error monitoring apparatus 200 is connected to the switch 100 at a short distance, the error monitoring apparatus 200 may generally use an RS-232 port.

In addition, it may include a separate control system 300 to analyze and determine the error occurred in the switch 100.

In this case, the error monitoring apparatus 200 may include an RS-232 interface unit for interfacing with the exchange 100. Similarly, the control system 300 may include a remote interface unit for interfacing with the error monitoring apparatus 200.

The function to be implemented through the error monitoring apparatus 200 is a message processing function of each processor inside the switchboard, an operator matching function through a dummy terminal, a system port control function of the switchboard, and an IPC communication state between the processors. Check function and processor check function.

The processor's message processing function collects and displays messages generated by anomalies in the exchange and peripheral I / O processors for each processor. In addition, the collected messages are classified and stored, and searched and analyzed according to the messages according to time zones so that an alarm can be alerted when a failure occurs. Therefore, it is possible to block the error in advance or to recover early even if a failure occurs. At this time, the messages collected in the input and output ports of the processor can be utilized as a clue to the occurrence of the system to complement the system.

The operator matching function enables matching and release of each processor in real time through an operator control system. That is, a plurality of dummy terminals are provided to activate and monitor each processor connected to a port of the operator system in a separate window and to transmit a command to the processor.

The system port control function changes the configuration of the access port appropriately according to the structure of the exchange provided by each company (Samsung, Hyundai, LG, etc.), and checks whether the port information is normally input according to each configuration.

The IPC communication status check function between processors can input, change and delete IPC check information, and perform IPC test according to the operator's request. It also stores IPC check information and outputs it on demand. If an error occurs during the IPC check, an alarm message is generated and the IPC log automatic test function is included to check the exchange at a fixed time every day.

The processor check function is a function that periodically requests a response from the processor in order to prevent each processor from falling into a sleeping state. The processor check function detects and notifies an alarm state of the processor.

3 illustrates a centralized structure in which error messages generated by the switch 100 are not collected in the middle, but collected directly by the error monitoring apparatus 200 and provided to the control system 300. On the other hand, each ASS, INS or CCS unit of the exchange can be configured in a distributed type that primaryly aggregates the RS-232 port at a predetermined ratio and then secondaryly aggregates through the exchanger error monitoring apparatus 200.

The centralized structure as shown in FIG. 3 is composed of only an error monitoring apparatus, and the overall configuration is simple since the interface method is simple. In addition, there is an advantage that the development period of hardware and software is shorter than the distributed structure. In addition, by configuring and installing all of the error monitoring apparatus in one rack, the main body becomes large, but there is an advantage of low maintenance and management costs. On the other hand, in the distributed structure, since the devices concentrating the error of the exchange port are distributed in the primary and the secondary, the main body is small, but the overall structure is complicated, so the probability of failure is high, and maintenance and management are difficult. In addition, the interface protocols become complicated, and the development period of hardware and software becomes long.

4 is a block diagram of a centralized error monitoring apparatus according to a preferred embodiment of the present invention. Referring to FIG. 4, the error monitoring apparatus 200 of the present invention may include up to 512 RS-232C cables for connection with an exchanger. In addition, it has an internal configuration so that the message of the debug (RS-232C) port generated at the exchange can be directly collected by the error monitoring apparatus 200 and transmitted to the control system 300.

The error monitoring apparatus 200 may be provided with an IPC supervision and operation back board (ISBB) and a power pack (PWR) on each of two shelves. Each of the two ISBBs may be provided with four RSIA interface board assemblies (RSIAs), and one control and memory interface board assembly (CMIA) may be provided in one side of the ISBB. Accordingly, the error monitoring apparatus 200 may be composed of two ISBBs, one CMIA, and eight RSIAs.

At this time, the data transmission rate for the RS-232 port between the error monitoring device 200 and the switch 100 is generally 9,600 bps, the data transmission amount of the control system 300 is 230.40 Kbps, Ethernet Can be transmitted at speeds of up to 10Mbps.

For example, in order to store 4 days of transmission data in the control system 300, a memory capacity of up to 230.40 Kbps x 3,600 sec x 24 hours x 4 days = 7.96 G bytes is required. Such memory capacity will vary depending on the data storage period.

5 is a block diagram of an ISBB in the error monitoring apparatus according to the preferred embodiment of the present invention. Referring to FIG. 5, four RSIAs in ISBB communicate asynchronously with an exchange through an RS-232 connector. CMIA uses HDLC (High level Data Link Control) format and is in charge of control system and LAN interface through RJ-42 connector.

Each RSIA can accommodate 64 RS-232 ports, so one ISBB can accommodate 256 RS-232 ports, and the fault monitor 200 can accommodate a total of 512 RS-232 ports. Can be. The RSIA receives the asynchronous serial data 64 bits transmitted from the switch 100 at 9,600 bps and synchronizes the system clock of the error monitoring apparatus 200. Then, the received signal is converted into parallel data and multiplexed to 512: 64 and transmitted to the CMIA. Meanwhile, the CMIA receives the data transmitted from the control system 300 and transmits the data to the RSIA through the UART port of the MC68360 provided in the CMIA by 9,600 bps data along with the RS-232 port number. Accordingly, RSIA demultiplexes the RS-232 port number to transmit the UART Tx signal provided from the CMIA to the corresponding port. 5 shows an ISBB with a CMIA.

6A and 6B are tables showing definitions of signals used in the ISBB shown in FIG. 5 in the error monitoring apparatus according to the preferred embodiment of the present invention.

6A and 6B, all signals used in the CMIA may be used as a TTL (Transistor Transistor Logic) signal.

The UARTTX signal provided from the CMIA to the outside is an RS-232 Rx signal to be output in the exchange direction, and is demultiplexed to the corresponding port by the corresponding DMXSEL signal received from the RSIA. The RS_TX +,-signal is an RS-485 Tx signal that interfaces with the control system 300, and the RS_RX +,-signal is an RS-485 Rx signal that interfaces with the control system 300.

The RSIAOPEN 3,2,1,0 signal is the PBA open signal of the self-side RSIA, and the RSIAOPEN D, C, B, A signal is the RSIA PBA open signal of the other side. The RSIAFF 3,2,1,0 signal is a signal indicating a functional error of the self-side RSIA, and the RSIAFF D, C, B, A signals are a signal indicating a functional error with respect to RSIA of the other side.

The RS_DPRAMDATA [7: 0] signal is multiplexed Rx data transmitted from RSIA, and the OUTDMXSEL [8: 0] signal is a signal for decoding the UARTTX signal, which is an RS-232 Tx signal transmitted to RSIA.

The CMIAOPEN 2,1,0 signal is the PBA open signal of the CMIA, and the FRAMESYNC + and − signals are signals for synchronization in RSIA. The OUTCLK49152M +,-signal is a clock signal for re-adjusting clock timing in RSIA, and the OUTCLK49152K +,-signal is a clock signal for synchronizing bytes in RSIA. In addition, the OUTCLK1536K +,-and OUTCLK96K signals are clock signals for bit synchronization in RSIA. The CPUDOGCLK signal is a clock signal for monitoring the clock of RSIA, and the RS_ADDCOUNT [7: 0] signal is a data count value of RS_DPRAMDATA.

7 is a block diagram of RSIA in the error monitoring apparatus according to the preferred embodiment of the present invention. Referring to FIG. 7, the RSIA of the present invention is connected to 64 RS-232C ports having a transmission rate of 9,600 bps for data transmission with the exchange 100. That is, RSIA multiplexes 64-bit RS-232 asynchronous data received from the exchange 100 to the CMIA, and receives RS-232 asynchronous data from the CMIA and transmits the same to the exchange.

At this time, RSIA uses 64-bit RS-232 received data by 8 receiving FPGAs (Field Programmable Gate Array: FPGA-RX0, ..., FPGA-RX7) respectively processing 8-bit RS-232 Rx data. To process The 64-bit data to be transmitted to the switch 100 is processed by one transmitting FPGA (FPGA-TX) that processes 64-bit RS-232 Tx data. In addition, a transmission FPGA (FPGA-TX) for RS-232 transmission data collects clock and function errors in RSIA and transmits them to the CMIA.

8 is an internal block diagram of an RSIA receiving FPGA in an error monitoring apparatus according to a preferred embodiment of the present invention.

Referring to Figure 8, the receiving FPGA is composed of eight FPGAs (OR2C12A-2S208), each FPGA is matched with 8-bit RS-232 Rx data transmitted from the exchange. Each receiving port further comprises a bit synchronizer for inducing bit synchronization and a byte synchronizer for inducing byte synchronization for the received data.

The bit synchronizer re-times the received RS-232 Rx data of 9,600 bps to 38.4 KHz, thereby performing bit synchronization for 9,600 bps of data. When the bit synchronization is achieved, the start bit detector detects the start bit. When the start bit is detected, 10 bits of data are recognized as valid data after the detection, and the SP converter SPCON generates a bytesynsig signal for enabling data. In other words, 10 bits of data consisting of 1 bit of start bit, 8 bits of data and 1 bit of stop bit are latched at 9600 Hz in the latch section and are enabled by the bytesynsig signal. The data that has passed through the latch section is cleared without being held continuously according to the clock of 9600/10, that is, 960 Hz.

The data from which the start bit is detected is converted into 10-bit parallel data through the SP converter (SPCON), and the parallel-converted 10-bit data is MSB (Most Significant Bit) and LSB for 8-bit data except for the start bit and the stop bit. The order of (Least Significant Bit) is converted. This is because the MSB and LSB cross each other because the received RS-232 Rx data is received in the order of start bits, D0 to D7, and stop bits. That is, when the MSB is Q1 and the LSB is Q8 in the data of Q1 to Q8 received through the RS-232 port, the bit stream is converted so that the MSB becomes Q7 and the LSB becomes Q0. Therefore, in order to process the data in the control system 300 it is necessary to convert it again, it is preferable to convert in hardware.

The converted 8-bit data is latched at a time interval of one serial bit (r9.6 KHz) and outputted by an enable signal (En491.52K) having a 1/512 time width for a time interval of serial 10 bits. Synchronization and multiplexing are done. In addition, the output 8-bit data is output from the FPGA, connected to the other seven FPGAs processing RS-232 Rx data in a tri-state and transmitted back to the CMIA through 74ABT16374.

When the start bit and the stop bit are normally detected, the 8-bit counter (8 bit CNT) is incremented by 1, and is enabled by the enable signal En491.52K having a 1/512 time width for the time interval of serial 10 bits. The count signal is output and sent to the CMIA. This signal means a count of transmission data for 8-bit data transmitted in parallel by the CMIA. In other words, the start bit and stop bit are used as enable signals of the 8-bit counter. The 8-bit counter (8 bit CNT) counts only valid data having a start bit of 0 and a stop bit of 1, and transmits a count signal to the CMIA using the 512: 1 enable signal 49152Ken. The transmitted counter value is used as the DMA count value in the CMIA.

The 8-bit counter (8 bit CNT) transmits up to 256 bytes of data for 256/960 us and is cleared periodically by the rfp signal.

In this way, an FPGA that processes eight RS-232 Rx data is operated.

9 illustrates a selection signal for selecting eight FPGAs in the error monitoring apparatus of the present invention. As shown in Fig. 9, three bits of selection signals ID0, ID1, and ID2 are required to select eight FPGAs.

FIG. 10 shows an internal block diagram of the FPGA for transmitting RSIA in the error monitoring apparatus according to the preferred embodiment of the present invention.

Referring to FIG. 10, a transmission FPGA (FPGA-TX) performs a function of transmitting RS-232 data from a CMIA to an exchange, a loop back test function, and a clock monitor function.

11 illustrates a selection signal for performing a loop back function in a transmission FPGA in an error monitoring apparatus. Referring to FIG. 11, if the loopall signal is low (0), the UARTTX signal is looped back from the CMIA to TXOUT [63: 0], and if the loopone signal is low (0). The loop back test function is performed only for the transmission port selected by the DMXSEL signal. If both the Loopall and Loopone signals are high (1), this is normal operation.

In addition, RSIA transmit FPGA monitors the clock by receiving the monitorclk [7: 0] signal from each receiving FPGA in common by outputting a monitorclkout signal in order to detect an error condition of the clock monitor and each receiving FPGA. . In addition, the Cpudogclk signal is received from the CMIA to monitor the Framesync signal. It also monitors the PBA open state by receiving RSIAOPEN signals from the top, middle, and bottom of the edge pin, respectively. According to such a monitor state, a PBA function error signal is output through a combination of logics.

12 illustrates a state of receiving data according to a mode state. Referring to FIG. 12, when the mode signal is in a low state (0), the mode signal operates in a slave mode in which data is downloaded to the FPGA through a download cable. On the other hand, when the mode signal (mode) is in the high state (1), the FPGA operates in a master mode for downloading data from a read only memory (ROM).

The CMIA may be divided into a central processing unit, a memory unit, and a control unit.

The central processing unit is digital x86 from companies including Alpha, MIPS Technologies, NEC, IDT, Siemens, MIPS, Intel and Cyrix, AMD and Nexgen. And a processor having various architectures such as IBM and Motorola's PowerPC, but the present invention employs the MC68360.

The memory unit is a high speed main memory, which is generally a type of storage medium such as random access memory (RAM) and read only memory (ROM), and long-term such as floppy disk, hard disk, tape, CD-ROM, and flash memory. Auxiliary storage devices in the form of storage media and devices for storing data using electrical, magnetic, optical or other storage media. In addition, the main memory may include a video display memory for displaying an image through the display device.

In the present invention, as shown in FIG. 13, two 512K bits of ROM or one 1M bit ROM are used, and 64K bytes of SRAM (Static RAM), 256K bytes of SRAM for program download, and RS- from RS- are used. It consists of two 128K-byte SRAMs operated by Double Buffering for 232 Rx data processing, and a 2K-Byte Dual Port RAM (DPRAM) for storing the count values of the transmitted data.

The control unit is configured as an FPGA to generate double buffering, DPRAM control, RSIA functional error collection and demultiplexing select signals for RS-232 transmission.

The RSIA converts the RS-232 Rx of the 512 port from the switch 100 into 8-bit parallel data, multiplexes it, and transmits the same to the CMIA. The CMIA converts it into HDLC format and provides it to the control system 300 through Ethernet. In addition, the CMIA receives data to be transmitted from the control system 300 to the switch 100 via Ethernet, decodes the data into RS-232 data, and transmits the data to RSIA.

At this time, the CMIA is designed to handle 128K bytes (512 ports × 256 bytes) of data during synchronization of one frame. That is, frame synchronization has a time interval of 1/960 us × 256 bytes, and one port has a period (491.52 KHz) of 1 / (960 Hz × 512) = 2.0345 us.

In addition, the CMIA is provided with 8-bit parallel data multiplexed by 64 ports x 256 bytes each from eight RSIAs, and a transmission count value for the data. Data transmitted from RSIA is double buffered through two SRAMs each having a capacity of 128K bytes (1M bits). First, data is read randomly through the lower buffer in the sequential write operation of the upper buffer, and data is read randomly through the upper buffer in the operation of continuously writing the data into the lower buffer. At this time, each port has a size of 256 bytes.

14A and 14B show addresses of respective ports for the double buffer 0 and the double buffer 1, respectively. 14A and 14B, the upper DBUFFER0 starts at 200,000 and the lower DBUFFER1 starts at 220,000. The continuous write address of each port is composed of Base Address [7: 0] + addcount [7: 0].

Fig. 15 shows the memory map of the DPRAM in the error monitoring apparatus of the present invention. Referring to FIG. 15, a 2K byte DPRAM is for storing the number of transmitted bytes of each port transmitted during one frame sync. Similarly, the DPRAM is operated by sequential write random read, a write operation is performed through the left port, and a read operation is performed through the right port.

The left port of DPRAM is addressed to Base Address [8: 0] and addcount is data and is written to DPRAM. That is, the transferred count value is stored in DPRAM to indicate how many bytes of data have been transmitted for each port.

Let's take a closer look at the behavior of DPUFFER for DBUFFER0 and DBUFFER1 for transfer data and for transfer data count values.

First, the RSIA is synchronized with the Frame sync signal and transmits data and count values of each port to the CMIA. CMIA sequentially stores data in DBUFFER, and count values are stored in DPRAM. As such, when a write operation for one frame is completed, an interrupt is generated to perform a read operation as much as the count transmitted for each port in the central processing unit. Since DBUFFER0 and DBUFFER1 are double buffers that operate in pairs, interrupt 6 is generated to perform random read operations to the lower buffer DBUFFER1 when continuous writing is performed to the upper buffer DBUFFER0. When an interrupt occurs, the central processing unit reads the data count value transferred to each port from DPRAM and reads data from DBUFFER0 by the count value. Then, it is converted into HDLC format and transmitted to the control system 300 by RS-422.

In this way, up to 256 bytes of data are transmitted over 1/960 us for each port. That is, up to 512 x 256 bytes = 128 K bytes of data for the 512 port for 256/960 us is transmitted to the control system 300.

Similarly, in order to perform a random read operation for the upper buffer DBUFFER0 in the continuous writing process for the lower buffer DBUFFER1, interrupt 7 is generated, and the operation is the same as the method described above.

In addition, the data received from the control system 300 via Ethernet transmits the data and the address of the data to RSIA in the form of start bit 1 bit, data bit 8 bit, stop bit 1 bit using the MC68360 of the central processing unit. The CMIA also reads RSIA's PBA open and RSIA's functional failure status from the FPGA.

16 is a flowchart illustrating a method of operating an error monitoring apparatus according to a preferred embodiment of the present invention. Referring to Figure 16, the error monitoring device operating method of the present invention will be described.

An operation program for operating the error monitoring apparatus of the present invention may be installed inside the error monitoring apparatus or may be installed in a control system connected to the error monitoring apparatus. Here, the operation program will be installed in a separate control system connected to the error monitoring device and used.

The control system may be a general personal computer or computer system such as a workstation. The operator may monitor an error message output from each port of the error monitoring device by using an operating program installed in the error monitoring device or the control system, analyze the error message, and control the processor in a proper manner or notify the exchange manager.

First, an error monitoring device is installed between the exchange and the control system, and an operator installs an operation program for controlling the error monitoring device in the control system. The operator may execute the operation program in the control system (s10), and adjust the initial setting of the operation program.

17 shows an initial screen when an operating program is executed in the operating method of the error monitoring apparatus of the present invention. Referring to FIG. 17, an operation program provides a menu for using system control, message retrieval, processor control, IPC LOG control, and a remote operator terminal function. During the initial installation of the operating program, you will set up information about the processor inside the exchange and about each port of the fault monitoring device. At this time, the message collected from the port through the error monitoring device is operated based on the port setting information, and the message collected from the port without the set information will be processed by the information about the port number provided by the operating program. .

During the initial execution of the operating program, the operator will set information on the ports installed in the error monitoring apparatus, respectively (s12).

18A to 18C are screen diagrams illustrating a process of setting information on each port of an error monitoring apparatus through an operation program in the error monitoring apparatus operating method according to an exemplary embodiment of the present invention. First, referring to FIG. 18A, an operator may set or change basic information about each port and output information set on the port through a screen. That is, in order to operate the operation program normally, information setting on the port of the error monitoring apparatus should be made first.

At this time, the port of the error monitoring device and the exchange processor will be connected to RS-232C, LAN (Local Area Network) or TTL.

18B illustrates an example of a screen for an operator to input switch processor information on a port of an error monitoring apparatus in an operation program.

For each port, the operator specifies the RSIA card number and the port of the RSIA card, selects a processor inside the exchange, and enters information about the corresponding port. The operator monitors each processor inside the exchange by classifying, storing and analyzing the information collected through each port. At this time, the operator's input information on the port of the error monitoring apparatus is used to collect messages of the exchange.

Information about the port entered by the operator and information about the processor inside the exchange is output on the port setting status screen so that the operator can check this directly.

18C illustrates an example of a screen on which an operator outputs processor information set in ports installed in an error monitoring apparatus. By specifying the subsystem of the RSIA card or exchange, the operator can output the port information assigned to it according to the selected method.

The operator can assign a new port or change the configured information by using the port setting / change control screen.

The operator may monitor the processor inside the corresponding exchange by using the setting information of each port of the error monitoring apparatus (s14), and store each message output through each processor (s16). The operator will analyze the message output from the processor inside the exchange, and analyze the processor status in case of an error (s18). At this time, when the error message output from the processor inside the switch is the same as the error message occurred in the past, it may be determined to be the same error and the error may be easily corrected. Therefore, the error message output from the processor inside the switch is stored in the memory unit, it is preferable to extract and use as needed.

In addition, the operator may confirm this by outputting an error message or an analysis result of the internal processor of the exchange through a screen (s20).

19A and 19B illustrate screen examples of a process in which an operator checks a message collected from a processor inside an exchange in a method of operating an error monitoring apparatus according to an exemplary embodiment of the present invention. Referring to FIG. 19A, an operator may open a screen for controlling a message collected through an error monitoring apparatus. At this time, the operating program may analyze the capacity of the message stored in the control system and inform the operator of the available memory space.

Referring to FIG. 19B, an operator may output a message collected / analyzed through an error monitoring device to a screen. That is, the operator may check the stored message by designating a processor inside the switch or designating a port of an error monitoring apparatus and inputting date and time information to be searched. At this time, the retrieved message can be printed using an output device such as a printer, and the size of the printable message will be sufficiently expandable.

If the message about the processor collected through the port of the error monitoring device is a normal message, the process of monitoring the processor will be repeated. On the other hand, when an error message is generated from the processor inside the exchange, the error message and the corresponding control method will be provided to the manager of the exchange processor (S24).

On the other hand, the operating program of the error monitoring device itself has a function to control the exchange processor, it will be able to control the operation of the processor inside the exchange by the operating program at the request of the processor administrator (s26). .

20A and 20B illustrate screen examples when an operator controls a processor inside an exchange in an operating method of an error monitoring apparatus according to an exemplary embodiment of the present invention.

First, referring to FIG. 20A, an operation program provides a function of setting each processor of an exchange for each subsystem, a function of providing a dummy terminal to an operator, and a function of monitoring an output state of collected messages. Accordingly, the operator can check the state of the processor by analyzing the collected messages.

In addition, the operating program may include a function of resetting a processor in an abnormal state among the processors inside the exchange through the control system.

Referring to FIG. 20B, an operator may check information on a processor or a subsystem within an exchange, respectively. That is, when the operator inputs the subsystem type of the exchange, the operator may check the information of the processor or the subsystem connected to the port of the error monitoring apparatus. At this time, the operator can delete a processor that is not installed in the exchange.

In addition, when the operator selects a processor to be checked by the operator through the processor connection screen inside the exchange, the operating program will provide a screen for monitoring the corresponding processor. Through this, the operator may directly control the corresponding processor.

Meanwhile, when an operator inputs a command on the screen, the operating program may transmit a corresponding command to a processor inside the exchange. For example, the operator can reset the exchange processor in an abnormal state. In addition, the operation program may output information about the processor on a screen according to the request of the operator.

The operator may release the processor connection screen inside the exchange through the processor release screen. The operation program may output the state of the processor or the subsystem in the exchange as a result of analyzing the collected message through the processor state output screen in the exchange. The processor may be classified into a normal state and an abnormal state, and the abnormal state may be divided into a down state, an operating system (OS) loading state, a user loading state, an IPC communication disconnection state, and a loop state.

The operating program may reset the processor in an abnormal state following the operator's request. That is, the operator receives a command input from the screen and transmits it to the corresponding processor, and outputs a message output from the processor to the screen in real time. At this time, the reset function of the processor may target the processor and the subsystem within the processor.

21A to 21E illustrate an IPC log control screen in a method of operating an error monitoring apparatus according to a preferred embodiment of the present invention.

Referring to FIG. 21A, an operator may open a screen for an IPC log test and input information. The operation program may include a function of performing an IPC log test according to the input information, outputting the result, and generating an alarm according to the test result. At this time, the operator can adjust the alarm rating ratio. At this time, the IPC log function is possible when the processor is in a normal state. The operator can directly test the IPC log through the processor connection screen, and an alarm is generated according to the result.

Referring to FIG. 21B, for the IPC log test of the processor, an operator may input necessary information or change the input information. The input information or changed information is valid after the set time, and the change will not be applied to the processor performing IPC log test at the moment of changing the information.

When the operator inputs the information for the IPC log test, the test function is performed according to the input information. If the operator designates the test period, the IPC log test will be performed at intervals of the designated time. At this time, it is desirable that the test period be between 10 minutes and 24 hours. The IPC log test function is not limited to one processor but can be applied to a plurality of processors at the same time.

21C is a screen for outputting IPC log test information. If the operator selects a particular processor, the registration information for the IPC log test of the selected processor is output. The operator can select a processor and perform an instant IPC log test.

21D is a screen for outputting a result of an IPC log test. The operator specifies subsystem or processor information to verify the IPC log test results of the processor. Based on the IPC log test results, the operator will determine the normal state of the processor and take action accordingly. For example, the operating program may alert an administrator of an error processor to an error and change a state of the processor to a normal state.

21E is a screen of controlling an alarm to be generated to an administrator of a corresponding processor according to the IPC log test result of the processor. The operator inputs information on the alarm that occurs according to the IPC log test results for each processor. That is, the operator may be divided into a critical alarm, a major alarm, or a minor alarm according to an error state.

22 is a diagram illustrating an example of a case where an operator monitors an input / output message of an exchange in an operating method of an error monitoring apparatus according to a preferred embodiment of the present invention. Referring to Figure 22, the operator can monitor one or more exchanges through the control system.

In the above description, the case of the exchange has been described as an example, but the error monitoring apparatus of the present invention is not limited to the case of the exchange, and it will be apparent that all of them can be applied to a general communication apparatus.

As described above, according to the error monitoring apparatus and the method of operating the same of the present invention, it is easy to detect the state of the processor by collecting and analyzing the messages output through the processor inside the exchange or the communication device, and gives an abnormal state to the processor manager. Can perform alarm function for.

In addition, by controlling the operation of the processor in which the error occurs through the operating program, it is possible to effectively manage the corresponding processor.

Therefore, it is possible to prevent the occurrence of an error in the processor inside the switch or the communication device, and to ensure reliability of the switch or the communication system.

In addition, because processors and subsystems within an exchange or communication device can be managed through remote systems that are spaced from the exchange, operators can facilitate error checking, error elimination, and prevention without having to directly check the exchange or communication device. Can be done.

In addition, the present invention can perform an IPC log test automatically for an exchange or a communication device to check the system for errors, so that preventive measures can be taken in advance for errors that may occur in the system, thereby improving reliability of the system. Can be.

In the above, the error monitoring apparatus of the present invention and a preferred embodiment of the method for operating the same have been described in detail, but the contents are not limited to the field of the present invention described in the following claims. In addition, it will be apparent to those skilled in the art that various changes and modifications can be made within the scope of the present invention.

Claims (17)

A matching unit configured to mate with a processor or a subsystem within the communication device to perform asynchronous data transmission, and to synchronize the received data with an internal clock; A control unit which receives data of the matching unit and converts the data into a data format usable by an operator control system; A control system matching unit matching with an operator control system to perform asynchronous transmission of the data converted by the controller with the operator control system; And An operator control system that determines an error condition in accordance with output data of a processor or a subsystem within the communication device, and accordingly sends an alarm signal or control signal to the communication device. Error monitoring device comprising a. The method of claim 1, The matching part RS-232 interface unit with a plurality of RS-232 ports for asynchronous transmission with the communication device Error monitoring device comprising a. The method of claim 2, The RS-232 interface unit A plurality of receiving FPGAs for receiving data output from the communication device; And Transmitting FPGAs for Transferring Data to Communication Devices Error monitoring device comprising a. The method of claim 3, The receiving FPGA Each RS-232 port, comprising: a bit synchronizer for retiming the received data bit by bit; And A byte synchronizer for detecting start and stop bits from data synchronized through the bit synchronizer and generating a sync signal in units of bytes. Error monitoring device comprising a. The method of claim 4, wherein The byte synchronizer A latch unit for latching input data for a predetermined time; And A converter for converting the order of the data bits except for the start bit and the stop bit from the latch data Error monitoring device comprising a. The method of claim 3, The transmission FPGA A loop back test unit for testing a loop back function with respect to an RS-232 port; A monitor unit configured to monitor a state of a clock signal and a frame synchronization signal of a receiving FPGA; And Transmitter that transmits RS-232 data to the exchange Error monitoring device comprising a. The method of claim 1, The control unit A memory unit for storing data received by the matching unit; A buffer unit for buffering the received data before processing; And Data converting unit converts the data transmitted through the buffer unit to parallel data, and then converts the data transmitted to the HDLC type used in the operator control system or the RS-232 type used in the exchange. Error monitoring device comprising a. The method of claim 1, The control system matching unit LAN interface unit having a plurality of LAN ports for data transmission with the operator control system Error monitoring device comprising a. The method of claim 8, The LAN interface unit A plurality of receiving FPGAs for receiving data output from an operator control system; And Transmitting FPGA to Transfer Data to Exchange Error monitoring device comprising a. The method of claim 9, The receiving FPGA In each LAN port, a bit synchronizer for retiming the received data bit by bit; And A byte synchronizer for detecting start and stop bits from data synchronized through the bit synchronizer and generating a sync signal in units of bytes. Error monitoring device comprising a. The method of claim 10, The byte synchronizer A latch unit for latching input data for a predetermined time; And A converter for converting the order of the data bits except for the start bit and the stop bit from the latch data Error monitoring device comprising a. The method of claim 9, The transmission FPGA A loop back test unit for testing a loop back function with respect to a LAN port; A monitor unit configured to monitor a state of a clock signal and a frame synchronization signal of a receiving FPGA; And Transmission unit for transmitting data provided through the LAN to the operator control system Error monitoring device comprising a. A method for monitoring an output message of a processor or a subsystem inside a communication device through an error monitoring device connected to the communication device, Setting one or more port information included in an error monitoring device respectively connected to a processor or a subsystem in a communication device; Receiving an output message of a processor or a subsystem in a corresponding communication device according to the set port information; Analyzing the received message to analyze a state of a corresponding processor or subsystem; Transmitting an alarm message to a processor or a subsystem in which an error occurs according to the analysis result; And Controlling the operation of the failed processor or subsystem at the request of a processor or subsystem manager within the communication device; Operation method of the error monitoring device comprising a. The method of claim 13, The port information is Module information used for a port connected to a processor or subsystem within a communication device; And The corresponding port number Operation method of the error monitoring device comprising a. The method of claim 13, Receiving an output message from a processor or subsystem within the communication device Steps for storing received messages in the database Operation method of the error monitoring device further comprising. The method of claim 13, Controlling the operation of the failed processor or subsystem Resetting the corresponding processor or subsystem Operation method of the error monitoring device further comprising. In the recording medium tangibly embodied and readable by the digital processing apparatus, a program of instructions that can be executed by the digital processing apparatus is implemented so that the error monitoring apparatus can be operated through a network. The operation method of the error monitoring device, Setting one or more port information included in an error monitoring device respectively connected to a processor or a subsystem in a communication device; Receiving an output message of a corresponding processor or subsystem according to the set port information; Analyzing the received message to analyze a state of a corresponding processor or subsystem; Transmitting an alarm message to a processor or a subsystem in which an error occurs according to the analysis result; And Controlling the operation of the failed processor or subsystem at the request of the processor or subsystem administrator Computer recording medium comprising a.