KR20000076351A - Integrated circuit and method for testing the same - Google Patents

Abstract

The present invention relates to an integrated circuit having a CPU and a user-ROM, wherein the circuit comprises a test-ROM, a CPU-external RAM and a switching means whose address range is within the user-ROM-address range, The switching means can be irreversibly displaced to only allow access to the user-ROM or access to the test-ROM and only allow access to the user-ROM.

Description

INTEGRATED CIRCUIT AND METHOD FOR TESTING THE SAME}

First chip card generations such as phone cards or medical cards could actually only perform memory functions. Later, relatively simple logic functions such as comparison of numbers or formation of pseudo random numbers were added. In safety-related areas, such as in banking operations where some significant values are stored or particularly in the case of reliable data, micro-capable of performing complex safety functions, encryption functions and / or verification functions as the use of chip cards increases. The use of processors is increasing. The use of cryptography (and decryption) methods, which require significant costs, is also increasing.

Semiconductor chips included in modern chip cards include expensive and complex circuits, which are generally partly additional modules, such as CPUs, ROMs, EEPROMs (or EPROMs) and UARTs, or coprocessors and devices. It is formed with a bus connecting them. The CPU is allocated at least one RAM, which is formed mostly as static RAM. Since static RAM requires significant space, most of these RAMs are very small and have less than 1 KByte of memory. Another feature of chip card products is that they have only one or two serial interfaces to the outside world, making data transfer very slow. Since 8-bit parallel processing is performed internally, serial / parallel conversion, which is controlled in a software manner using an accumulator to the CPU, is required, so that the conversion is also very slow. However, since normal data transfer is specified by ISO regulations and only consists of a few kilobytes per second, this is not necessary for normal operation, i.e. for operation to ensure that the user uses it in compliance, for example as a rechargeable cash trader. No problem.

However, the complex integrated circuits described must be delivered to customers with sufficient quality, and consequently extensive testing is essential.

Testing of such products is carried out by magnetic test-software. As such, the chip card product includes test memory that is executed as a ROM. The test memory includes magnetic test-software, whereby various parts of the chip can be tested after a power-on-reset. Magnetic test-software consists of different test routines that are called via test vectors. This test vector is input through the IO-port. Because the size of the test memory is limited and varies within different products, the memory generally cannot contain all test routines. As such, the rest of the test routine must be reloaded into the EEPROM and executed from there. This requires a large number of programming and erasing processes that last much longer than native tests.

The test memory executed by the ROM is a component part of the ROM present on the semiconductor chip, and the ROM also includes a user program such as an operating device, and a frequently used subprogram such as an EEPROM-write program and an erase program. Error or intentional and exploitation in the address area, even if the test memory area requires a portion of the address space of the ROM, consequently attempting to deny access to the address area of the ROM by a prescribed measure after the test is executed. Savings are possible.

To date, the realization has the disadvantage that on the one hand it is too slow and consequently the test lasts too long and on the other hand it is possible to enable access to the test routine even after the test, because the test routine is a ROM Either it is fixed almost internally or can be left on the chip in a non-volatile manner in a way that is possible within the EEPROM.

The present invention relates to an integrated circuit comprising a CPU, a user-ROM and a bus connecting the elements and a test method of the circuit.

1 is a block circuit diagram of an integrated circuit according to the present invention,

2 is a detailed circuit diagram of a preferred embodiment of the present invention.

It is an object of the present invention to provide a circuit arrangement that can enable rapid testing and increase the degree of protection against abuse.

This object is achieved by an integrated circuit comprising at least one CPU, a user-ROM, a test-ROM and a CPU-internal RAM. In this case, the address space of the test-ROM is inside the address space of the user-ROM, and in this case, the method according to the present invention is provided with a switching means enabling only access to the user-ROM or the test-ROM. In a preferred embodiment the switching means can be irreversibly displaced with only allowing access to the user-ROM. In this way, after the end of the test phase, the test-ROM may be blocked while the previous address space of the test-ROM is no longer occupied. As a result, there is no empty space in the used address area where the blocked memory area can be placed, and the attacker cannot use it.

In a refinement of the invention there are only test start programs which are absolutely necessary to start a test inside the test-ROM. Thus, the unique test routine is written into the additional RAM outside the CPU, so-called X-RAM, and then executed there.

The manufacturing method according to the invention is described in claim 7. However, storing the test routine only in the X-RAM has the advantage that the test routine can be erased by blocking the supply voltage after the test, because the X-RAM is volatile.

When applied to a chip card, only serial input ports / output ports are generally used, since only a limited number of contacts are provided there for communication with the outside world. Serial / parallel conversion or parallel / serial conversion is handled by an accumulator controlled by the CPU. This conversion is software controlled and correspondingly slow. Thus an improvement of the present invention provides an enable and disable shift register, which further connects the input port / output port with an internal bus. As a result, the test routine is written into the X-RAM much faster.

In a further embodiment of the invention, the shift register is used to transfer the monitoring signal appearing during the test to the inside of the test apparatus. This makes testing safer and faster. In this case, it is desirable to encrypt the signal before transmission, which encryption can be done in a preferred manner by back-coupling the shift register, eg linearly or nonlinearly, by means of an XOR-gate. However, other gate functions are possible.

The invention is described in detail below with reference to the embodiments with reference to the drawings.

According to FIG. 1, the CPUs are coupled to each other via a bus with RAMs, additional X-RAMs and non-volatile EEPROMs belonging to it. The serial input port / output port (I / O) is connected via the bus to an accumulator (not shown) contained within the CPU that is also used for serial / parallel-to-transformation. ROMs and test-ROMs containing mainly user software are likewise connected to the bus via a switching means (MUX), which can be a multiplexer. The switching means MUX may for example be triggered via an input port / output port I / O controlled by the CPU, this operation being indicated by an arrow St.

In the method according to the invention, only the ROM or the test-ROM can be addressed in connection with the bus at any time via the switching means (MUX). The address addressable to the ROM is at least partially identical to the address addressable to the test-ROM. Therefore, only referring to the address cannot detect whether the ROM or the test-ROM is addressed.

The bus can be irreversibly connected to the ROM via the switching means MUX, so that the test-ROM can be completely disconnected from the bus after the test phase has ended.

The test-ROM preferably stores only one test initiation program needed to start the test. Since this program is called after a power-on-reset, the test routine can be filled from the outside into the X-RAM and run from there. Writing test routines into the X-RAM is a much faster process on the one hand and volatile on the other hand, so that the test routines inside the X-RAM are interrupted, for example, in the distribution voltage. Can be quickly erased again. After the end of the test the switching means MUX is irreversibly displaced in a state that disables access to the test-ROM via the bus.

2 shows in more detail a preferred refinement of the integrated circuit according to the invention. The input port / output port (I / O), as already mentioned, can be addressed by a CPU connected in parallel to the bus via a bus by means of a special function register (SFR) -address via an address decoder. When an input port / output port (I / O) is triggered through the SFR-address, the input and output data is transferred over the bus to or from the CPU. In the CPU, serial / parallel conversion or parallel / serial conversion of data input and output by program control by the accumulator may be performed.

In the method according to the invention, a shift register SR is connected in parallel to the transmission path, by which a rapid serial / parallel conversion or parallel / serial conversion can be made during the test phase. The shift register SR is likewise responded and read through the SFR-address by the CPU. For this purpose a corresponding address decoder SFR is provided to the shift register SR. The shift register can also be activated and deactivated by the CPU via the SFR-address.

Thus, when the word to be converted is written into the shift register SR can be detected, the information is written into the shift register SR, the clock C1 is counted, and a signal is generated according to each word of the CPU. Counter Z is provided, and the CPU controls write input into the X-RAM.

Since a CPU can typically be parallelized in 8 bits in an integrated circuit, an 8 bit long shift register is sufficient in principle. A few start bits should be sufficient to synchronize the data flow. After 8 clocks respectively counted by the counter Z, the contents of the shift register SR are provided to the bus in parallel, thereby performing serial / parallel conversion at the time of write input.

However, since it is also possible to send a start bit before each byte to be read in and input, using a personal computer as a tester is simplified. This requires a 9-bit long shift register. Otherwise the data rate will be smaller.

The invention can in principle also be applied to 16-bit central units and 32-bit central units, in particular in the case where the word width that can be processed by the CPU is arbitrary. In that case, the shift register should just have a corresponding length.

The possible progression of the test proceeds as follows: First, the tester sends a logic "0" to indicate the start of data transfer. Thereby, the counter Z is released indicating that one byte can be collected after eight clocks each. The CPU can experience this with a special signal, but it is possible to set the time interval by software as accurately as possible. Before that, the address counter of the X-RAM is set to its beginning in a wait loop, where the CPU waits for the start of the transfer. After the transfer, the test routine is called first, and then the CPU jumps back into the receive-wait loop.

It is possible to continue operating the counter Z during the rest period between the two transmissions. Thereby the internal signal is combined with the system clock C1 having the contents of the shift register SR for eight clocks, for example, through an arbitrary function such as XOR (collecting step) and sent out for the next eight clocks (sending step). This combination is indicated by a double arrow from the shift register SR to the XOR-gate. In practice, the output signal of the shift register SR is back-coupled to the input of the register via XOR. XOR can be controlled by the CPU and switched on and off for encryption purposes. This is indicated by the arrow Pf. For each acquisition step this process can be interrupted by the start bit, so that a new data flow can be received as a result. The connection of the contents of the shift register SR and the internal signal during the acquisition phase has two reasons. On the one hand all eight values linked by the collection stage can thereby be checked for its accuracy; On the other hand, the original signal is no longer transmitted to the outside world, making it impossible to exploit the information for potential attackers.

This preferred refinement improves the satisfaction of the test and allows earlier recognition of the defective chip if a defect can be recognized in the observed internal signal.

Claims (8)

An integrated circuit comprising a CPU, a user-ROM and a bus connecting the elements, Similarly, a test-ROM connected to the bus and whose address space is inside the user-ROM address space, a CPU-external RAM (XRAM) connected to the bus, and a switching means that only allow access to the user-ROM or test-ROM ( MUX). It includes a CPU, a user-ROM, and a bus that connects the devices, and access to an integrated circuit is only possible through at least one serial input port / output port (I / O), and internal serial / parallel of the input data. In an integrated circuit configured to perform program-controlled parallel / serial conversion of data to be converted and outputted by the CPU, Similarly, a test-ROM, a CPU-external RAM (XRAM), which is connected to the bus and whose address space is inside the user-ROM-address space, and a switching means (MUX) which only allows access to the user-ROM or test-ROM Integrated circuit comprising a. The method according to claim 1 or 2, And said switching means (MUX) can be irreversibly displaced with only allowing access to the user-ROM. The method of claim 2 or 3, An integrated circuit, characterized in that a serial input port / output port (I / O) for serial / parallel conversion can be further connected to an internal bus via an enable and disable shift register (SR). The method of claim 4, wherein And the deactivation of the shift register SR can be performed irreversibly. The method of claim 4, wherein The shift register (SR) is back-coupled through a logic gate (XOR). A method for testing an integrated circuit comprising a CPU, a test-ROM, and a CPU-external RAM, the method comprising Operating a test start program set in the test-ROM after a power-on-reset, Controlled by the test initiation program to fill test routines into RAM and to execute there from the CPU, and -Erasing the test routine in the RAM after the end of the test and irreversibly inhibiting the execution of the test start program set in the test-ROM. The method of claim 7, wherein And writing test routines into RAM through serial input port / output port (I / O) and connectable serial / parallel-converter.