CN1251183A

CN1251183A - Integrated circuit and method for testing the same

Info

Publication number: CN1251183A
Application number: CN98803503A
Authority: CN
Inventors: J·诺勒斯; H·H·菲曼
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1997-03-19
Filing date: 1998-03-02
Publication date: 2000-04-19
Also published as: WO1998041880A3; JP2001527669A; BR9808381A; KR20000076351A; DE19711478A1; EP0968436A2; WO1998041880A2

Abstract

The invention relates to an integrated circuit with a CPU and a user ROM characterized by a test ROM whose address range is located inside the user ROM address range, a RAM located outside the CPU and switching means enabling access to either the user ROM or the test ROM and which can be irreversibly placed in a state allowing access to the user ROM only.

Description

The method of testing of integrated circuit and this integrated circuit

Chip card the earliest as phonecard or ward card etc., can only be realized memory function basically.Increased better simply logic function afterwards again, relatively or produce pseudo random number etc. as numeral.Along with the use of chip card in great security fields day by day increases, for example in banking industry, need partly store big numerical quantity, sometimes even will store the data of secret, just need add a microprocessor for this reason, and should handle and to realize complicated insurance, coding and/or differentiate operation.Simultaneously, encryption method also will be tried to achieve more and more, and this has just improved and assesses the cost.

Semi-conductor chip in the current chip card contain not only expensive and but also complicated circuit, according to the rules, these circuit are by a CPU, a ROM, an EEPROM (or EPROM) and some modules, and a bus that connects the said equipment is formed, here the module of indication is a UART, or an associative processor.CPU is a dispensing one RAM at the most, and this RAM is generally static RAM (SRAM) during enforcement.Because static RAM (SRAM) expends a large amount of spaces, so they all do very for a short time usually, and memory capacity is less than 1KB.In addition, the chip card product also has characteristics, is exactly that they and the external world have only one to the dual serial interface, and the speed of data transmission is very slow thus.Because inner concurrent working is 8, so must carry out the serial conversion, this conversion is realized by totalizer by software control that in CPU therefore this transfer process is also moved very slowly.Usually, data transmit and all to define according to an iso standard, and per second has only several thousand bytes, so this is unchallenged to normal operations, the user also can use this operation according to the rules, make it become a moneybag that adds money again.

Yet when submitting to client, above-mentioned complicated integrated circuit must guarantee enough quality, and therefore a large amount of test jobs is absolutely necessary.

This product test work realizes by the software of testing oneself.For this reason, the chip card product all contains a testing memory, is a ROM during enforcement.This storer has the software of testing oneself, and the power-on-reset element in the chip utilizes this software to test.The software of testing oneself is made up of each test procedure, and test procedure then calls by test vector.This test vector can be imported via the IO port.Because the size of testing memory is restricted, and each product interior size is all inconsistent, according to the rules, does not comprise all test procedures in the testing memory.Therefore, remaining test procedure benefit is loaded in the EEPROM and from then on calls.Just increased many programmings and delete procedure, these original test process duration are longer for this reason.

Many ROM are arranged on semi-conductor chip, are parts above it as the ROM testing memory, and it also contains user program, as operating system, also often has the subroutine of use, writes, deletes program etc. as EEPROM.The testing memory area requirement takies the part of whole ROM address space, like this, when situations such as appearance mistake or intentional and misuse, just can enter this address realm, according to the measure of determining, this part of access ROM address realm during realizing interrupt test.

Implementation method up to now has some shortcomings, be exactly slower on the one hand, test duration continues long and costs dearly again like this, on the other hand, for can the access test program at test period, these test procedures must quite firmly insert among the ROM or possible words, and it is kept in the EEPROM on the chip, make it non-volatile.

Therefore, task of the present invention is, a circuit arrangement is provided, and its test speed is very fast, and has the very high anti-error function of using.

This task is realized by an integrated circuit, which comprises at least a CPU, a user ROM, a test ROM and a CPU internal RAM.At this, the address space of test ROM is positioned within the address space of user ROM, and method of the present invention provides a switching device shifter, make or the access user is ROM, or access test ROM.Preferably continue in the development in the present invention, its switching device shifter can be moved to an irreversible state, only allows access user ROM.In this manner, test ROM can close after test phase finishes, and no longer takies former address space.Therefore, do not had the room in the existing available address realm, the memory range of closing can be put in the above-mentioned available address and go, thereby can't produce interference thus.

In improvement of the present invention, test ROM has only one to start the essential test starting program of test job.To this, the test procedure of itself writes on one outside the CPU and is named as among the additional RAM of X-RAM, and from then on program is carried out during work.

Provided method of the present invention in the claim 7.Test procedure only is stored in individual advantage among the X-RAM, because X-RAM is easily mistake, so just can delete test procedure as long as cut off supply voltage after test finishes.

Because chip card is limited with extraneous connection contact number, so only use a serial I/O port usually.Serial or parallel/serial conversion are taken over by the totalizer of CPU control.It needs software control and slower.For this reason, contain a register that can activate and can deactivate in improvement of the present invention, they link to each other with I/O port and an internal bus.Therefore test procedure can write X-RAM very fast.

In another embodiment of the present invention, the signal that can utilize this register will test generation is sent in the outside testing tool and goes, to play supervisory function bit.Like this, test job is not only safe but also rapid.This signal is preferably encoded before transmission, and they can carry out linearity or nonlinear feedback by register, for example, can adopt an XOR gate circuit to feed back.But also can adopt other gate circuit function.

Typical embodiments is with reference to the accompanying drawings set forth the present invention.Wherein:

Accompanying drawing 1 is the frame circuit diagram of integrated circuit of the present invention,

Accompanying drawing 2 is the detailed circuit diagram of the preferred embodiment of the invention.

Accompanying drawing 1 shows the EEPROM of a CPU and RAM, an additional X-RAM and a non-volatile effect, and they are connected with each other by a bus.Serial I/O port I/O couples together by the totalizer (not shown) in bus and the CPU, and totalizer also is used for carrying out the serial conversion.One ROM that contains a large number of users software is connected on the bus by switching device shifter MUX with test ROM, and diverter tool MUX can be more than one kind of converter.Typically, switching device shifter MUX is controlled by I/O port I/O by CPU, represents with an arrow St among the figure.

The method according to this invention, ROM and test ROM wherein have only one by switching device shifter MUX and bus is joined and carry out addressing.ROM is addressed to the addressing that a rare part equals to test ROM.Or actually therefore this part address with regard to the addressing of the addressing test ROM that can not determine ROM.

Bus is irreversible when being connected with ROM by switching device shifter MUX, so in test process, test ROM keeps apart fully with bus.

Preferably, test ROM only stores the test starting program of a startup test.After the power-on-reset, this program is called, and just can load the test procedure among the outside X-RAM then and is carried out at this.Test procedure writes on individual advantage in the X-RAM, be exactly that this operational process is very fast, and be again fugitive, and therefore, after supply voltage cut off, the test procedure among the X-RAM again can be deleted rapidly.After the end of test (EOT), switching device shifter MUX enters irreversible state, can not access test ROM by bus.

Accompanying drawing 2 shows another preferred integrated circuit of the present invention in more detail.As mentioned above, CPU can be compiled SFR (special function register) address to I/O port I/O by address decoder by bus, and the one side is connected in parallel on the bus.When by the SFR address I/O port I/O being controlled, inputoutput data just flows into through bus or outflow CPU.In CPU inside,, produce by the serial of totalizer or parallel/serial conversion and to input or output data by programming Control.

The method according to this invention, a shift register SR in parallel in transmission circuit, like this, in test process, serial or parallel/serial conversion can become faster.Equally, CPU responds and read operation shift register SR by the SFR address.For this reason, shift register SR is in requisition for an address decoder SFR.CPU also can be by the operation that shift register activated and deactivate of these SFR addresses.

Counter Z paired pulses Cl counts, and send a signal later at each word and give CPU, with the work that writes of control X-RAM, simultaneously also utilize counter Z that information is write shift register SR, so just can know when the word that will change to be write among the shift register SR and go.

Usually, because the CPU in the integrated circuit is 8 bit parallel working methods, so one 8 long shift registers just can meet the demands in principle.For data stream is reached synchronously, must reserve a start bit.After intact 8 pulses of the every meter of counter Z, read in and just produce serial conversion, thus the content of shift register SR is delivered on the bus concurrently.

Certainly, also can before reading in each byte, send a start bit, so that make personal computer obtain simplifying as tester.But this needs one 9 long shift registers.The transfer rate of data also can diminish in addition.

The present invention all is suitable for for various CPU work words are wide on principle, and specifically, it also is applicable to 16,32 CPU (central processing unit).And shift register only needs once length is passable accordingly.

The operational process of test job is as follows substantially: at first, tester sends a logical zero signal, shows that data transmit beginning.This hour counter Z opens, and it receives a byte with regard to showing 8 pulses of every mistake.CPU can be known above-mentioned situation by a special signal, but also can adjust this time with a software, and is more accurate like this, better effects if.In latent period, CPU is waiting for and is transmitting beginning, and the address counter of X-RAM is modulated to initial state before this.And then just call test procedure after transmission finishes, CPU jumps into the reception latent period again afterwards.

In two are transmitted intermittently, can allow counter Z continue operation.Like this, in 8 burst lengths after the pulse Cl of system, by any functional device, internal signal can be connected (collection phase) with the content in the shift register, in ensuing 8 pulses, again signal is sent (output stage), typification, the above-mentioned functions device can adopt an XOR.This kind connection is represented from the double-head arrow of shift register SR sensing XOR gate circuit with one.In fact, the output signal of shift register SR is to feed back on its input circuit by XOR.XOR can be turned on and off by CPU control by coding.Represent by an arrow P f at this.In each collection phase, this process is all interrupted by a start bit, so that receive data updated stream.Internal signal is connected with two reasons with shift register in collection phase.One, whether 8 numerical value can checking collection phase connect to produce correct, its two, do not have source signal to reach the external world, these information also just can not be by misuse for the current potential interference source.

This improvement of the present invention has improved the defencive function of test, as long as by observing internal signal to identify fault, just can find the chip of tape jam earlier.

Claims

1. integrated circuit has a CPU, a user ROM and one and connects their bus, it is characterized in that,

Test ROM also links to each other with bus, and its address space is positioned within the address space of user ROM, and CPU external RAM (XRAM) is connected on the bus, switching device shifter (MUX) make access can only at user ROM or test ROM one of them.

2. integrated circuit, have the bus that a CPU, a user ROM and connect them, only just can carry out access to it by at least one serial I/O port (I/O), and by the CPU programming Control, produce the input data by inner serial conversion, perhaps produce output data, it is characterized in that by parallel/serial conversion

Test ROM also links to each other with bus, and its address space is positioned within the address space of user ROM, and a CPU external RAM (XRAM) and switching device shifter (MUX) are arranged, switching device shifter make access can only at user ROM or test ROM one of them.

3. according to the integrated circuit of claim 1 or 2, it is characterized in that,

Switching device shifter (MUX) can be moved to an irreversible state, only allows access user ROM.

4. according to the integrated circuit of claim 2 or 3, it is characterized in that,

Serial I/O port (I/O) also can activate by one and the shift register (SR) that can deactivate couples together with internal bus, to produce the serial conversion.

5. according to the integrated circuit of claim 4, it is characterized in that, irreversibly realize the deactivation of shift register (SR).

6. according to the integrated circuit of claim 4, it is characterized in that shift register (SR) is fed back by logic gate (XOR).

7. the method for testing integrated circuits, this method contain a CPU, a test ROM and a CPU external RAM, and step is as follows:

After-the power-on-reset, the test starting program that is implemented among the test ROM activates,

-by the test starting programmed control test procedure RAM that packs into, and by CPU executive routine from then on,

After-the end of test (EOT), leave out the test procedure among the RAM, the test starting program interrupt that is implemented among the test ROM is carried out, and this interruption is in irreversible state.

8. according to the method for claim 7, it is characterized in that test procedure writes among the RAM through a serial I/O port (I/O) and the serial converter that can connect.