KR19990042281A - Error Tracking Device for Software Module - Google Patents

Abstract

The present invention relates to an error tracking device capable of tracking an error of a software module outside the central processing unit (CPU). The error tracking device according to the present invention comprises: an address register which stores the applied address information controlled by the central processing unit when an address and / or data to be tracked through the command application unit is applied; A data register for storing the data controlled by the central processing unit; An address comparator which compares an address generated while the central processing unit is normally operated with an address stored in the address register and outputs a comparison result only when the address is the same; A data comparator for comparing the data generated while the central processing unit is normally operated with the data stored in the data register and outputting a comparison result only when the same is the same; A comparison result control unit which counts the comparison results output from the address comparator and the data comparator, respectively, and outputs a comparison result of the address comparator and the data comparator when each count value reaches a predetermined value; And an interrupt processor for generating a predetermined interrupt to the central processing unit when the comparison result is transmitted from the address comparator or data comparator. Therefore, the simple hardware structure can accurately track the error occurrence status while online.

Description

Error Tracking Device for Software Module

The present invention relates to an electronic device that is operated by various software modules, and more particularly, to an error tracking device that can accurately track the location of an error in an on-line state when an error occurs in the software module operated in the electronic device. It is about.

When an electronic device operated by various software modules generates an error during operation, the error occurrence state was tracked by using a software solution or expensive measurement equipment. In other words, an example of a software solution is a method of causing an exception by placing a breakpoint in a certain area of memory. That is, when an error occurs, the operator controls the CPU (Central Processing Unit, hereinafter referred to as CPU) to replace the predetermined OP (OPeration) code with an exception code and execute the program. If a code that catches an exception is executed while the program is running, the CPU stops normal program execution, sets the system offline, and then goes to the debugging routine to track the error.

However, since this method is debugged in the offline state, the communication control equipment cannot provide the communication service to the subscriber during the debugging processing time. Therefore, a serious situation may occur when the debugging processing time is prolonged. In addition, due to an error in the software module, the information about the break point itself may not be stored in the corresponding region of the memory, or the recorded break point information may be damaged.

On the other hand, the method using the expensive measuring equipment does not cause the problem caused by the offline state as described above, but the equipment itself is expensive, but because of its large scale, the measuring equipment is moved to the side where the error has occurred and debugging. There is a lot of difficulty in doing this.

An object of the present invention is to provide an error tracking device for a software module that can accurately track the location of an error generated in an online state when an error occurs on the software module.

Another object of the present invention is to provide an error tracking device for a software module that can accurately track the location of an error generated on a software module with a simple hardware configuration without a separate measuring device.

In order to achieve the above objects, an error tracking device for a software module according to the present invention includes a central processing unit; A command applier which allows a user to apply an error tracking command for a predetermined address and / or data for a predetermined software module operated in the central processing unit to the central processing unit; A decoder for decoding the address output from the central processing unit and outputting a chip select signal; An address register which is driven by a chip select signal transmitted from the decoder and stores a predetermined address transmitted from the central processing unit via the data bus; A data register which is driven by a chip select signal transmitted from the decoder and stores predetermined data transmitted from the central processing unit via the data bus; An address comparator for outputting a comparison result signal whenever the address generated during operation of the central processing unit and the address provided from the address register are the same; A data comparator for outputting a comparison result signal whenever the data generated during operation of the central processing unit and the data provided from the data register are the same; An interrupt processor for generating a predetermined interrupt signal to the central processing unit when the comparison result signal is transmitted from the address comparator and / or the data comparator; A comparison result control unit for controlling the comparison result of the address comparator and the data comparator to be transmitted to the interrupt processor when the number of occurrences of the comparison result signal from the address comparator and the data comparator reaches a predetermined number; And a control register that stores and provides an enable control signal of an address comparator, a data comparator, and an interrupt processor driven by a chip select signal transmitted from a decoder and transmitted through a data bus.

1 is an error tracking device for a software module according to the present invention.

<Description of Symbols for Main Parts of Drawings>

102: command issuing unit 104: Central Processing Unit

106: decoder 108: control register

110: address register 112: data register

114: address comparator 116: data comparator

118: comparison result control unit 120: interrupt handler

122: output unit

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an error tracking device for a software module according to the present invention, in which a system is applied according to a command authorized from a command applier 102 and a command applier 102 capable of approving a desired command. An operating central processing unit (hereinafter referred to as CPU) 104, a decoder 106 which decodes an address output from the CPU 104 and outputs a select signal (CS) for a corresponding chip; From the control register 108 and the decoder 106 which are driven by the chip select signal CS transmitted from the decoder 106 and store and output the control signal transmitted via the data bus from the CPU 104. To the chip select signal CS transmitted from the decoder 106 and the address register 110 to store and output the address transmitted from the CPU 104 via the data bus driven by the chip select signal CS transmitted. of Is controlled by an enable control signal (ASEN *) transmitted from the data register 112 and the control register 108 to store and output data transmitted from the CPU 104 via the data bus. The data is controlled by the address comparator 114 comparing the address signal transmitted from the CPU 104 and the address transmitted from the address register 110, and the enable control signal DSEN * transmitted from the control register 108. The data comparator 116 compares the data transmitted from the CPU 104 and the data transmitted from the data register 112 via the bus, and is controlled by the chip select signal CS transmitted from the decoder 106 to control the address comparator ( Address comparison of a control signal for performing an operation according to the comparison result according to the signal output from the 114 and the signal output from the data comparator 116 Non-maskable interrupt (NMI) information when the comparison result is transmitted from the comparison result control unit 118, the address comparator 114, and / or the data comparator 116, respectively. An interrupt processor 120 for transmitting to the CPU 104, and an output unit 122 for outputting the error occurrence details output from the CPU (104).

The error tracking device configured as described above is operated as follows.

First, when the address information of the part to which error checking is desired from the command application unit 102 is applied, the CPU 104 sets the state where the address register 110 can write predetermined address information through the decoder 106. The chip select signal CS is provided. Then, the address information applied by the user is transmitted to the address register 110 through the data buses D0 to D31. Accordingly, the address designated by the user is stored in the address register 110.

The CPU 104 then transmits the address generated while operating normally to the address comparator 114 via the address buses A0 to A31. At this time, the CPU 104 performs synchronous control such that a time point at which an address generated during operation is transmitted to the address comparator 114 and a time point at which an address stored in the address register 110 are transmitted to the address comparator 114 are the same.

The address comparator 114 compares the addresses A0 to A31 transmitted from the CPU 104 and the addresses LA0 to LA31 transmitted from the address register 110, and compares the comparison result signal AMatch * whenever they have the same value. ) The comparison result signal output at this time is transmitted to the comparison result controller 118. The comparison result control unit 118 counts one by one whenever the comparison result signal is applied. To this end, the comparison result control unit 118 is configured to include an address counter (not shown) which counts by one each time a comparison result signal for the address is applied.

This address counter (not shown) operates by setting the value provided from the CPU 104 via the data buses D0 to D31 to the maximum count value. Therefore, the counter for the address not shown performs counting until the comparison result signal transmitted from the address comparator 114 reaches the above-described maximum count value. When the counting result reaches the above-mentioned maximum count value, the comparison result control unit 118 controls the signal comparator 114 to control the address comparator 114 so that the comparison result signal of the address comparator 114 is transmitted to the interrupt processor 120. Add Count Full) *).

When the comparison result signal is transmitted from the address comparator 114, the interrupt processor 120 transmits the NMI information to the CPU 104, and the CPU 104 outputs the trace for the corresponding address to the output unit 122. . At this time, the trace history output includes information such as the time taken for the CPU 104 to generate a predetermined number in the normal operation. Accordingly, the operator can grasp the outputted information to determine an error occurrence state for the corresponding address.

On the other hand, when the data of the part desired to error check is applied from the command application unit 102, the CPU 104 is set so that the data register 112 is set in a state in which the data register 112 can write predetermined data through the decoder 106. Provide the selection signal CS. The data applied by the user is transferred to the data register 112 through the data buses D0 to D31. Accordingly, the data designated by the user is stored in the data register 112.

The CPU 104 then transmits the data generated while operating normally to the data comparator 114 via the data buses D0 to D31. At this time, the CPU 104 performs synchronous control such that a time point at which data generated during operation is transmitted to the data comparator 116 and a time point at which data stored in the data register 112 are transmitted to the data comparator 116 are the same.

The data comparator 116 compares the data transmitted from the CPU 104 with the data transmitted from the data register 112, and outputs a comparison result signal whenever it has the same value. The comparison result signal output at this time is transmitted to the comparison result controller 118. The comparison result control unit 118 counts one by one as described above whenever the comparison result signal is applied. To this end, the comparison result control unit 118 is configured to further include a data counter (not shown) which performs a count by one whenever a comparison result signal for data is applied.

This data counter (not shown) operates by setting the value provided from the CPU 104 via the data buses D0 to D31 to the maximum count value. Therefore, the counter for data not shown performs counting until the comparison result signal transmitted from the data comparator 116 reaches the aforementioned maximum count value. When the counting result reaches the above-described maximum count value, the comparison result control unit 118 controls the data comparator 116 to transmit the comparison result signal of the data comparator 116 to the interrupt processor 120 (DCF ( Data Count Full) *)

When the comparison result signal is transmitted from the data comparator 116, the interrupt processor 120 transmits the NMI information to the CPU 104, and the CPU 104 outputs the trace for the corresponding data to the output unit 122. . At this time, the trace history output includes information such as the time taken for the corresponding number of data to be generated in the normal operation of the CPU 104. Accordingly, the operator can grasp the output information to determine the error occurrence situation for the data.

In this operation, the control register 108 is driven by the chip select signal CS transmitted from the decoder 106 to store the control signal transmitted through the data buses D0 to D31, and the stored control signal ASEN The enable states of the address comparator 114, the data comparator 116, and the interrupt handler 120 are controlled using (Add Signal Enable) *, Error Interrupt Enable * (EIEN) *, and Data Signal Enable (DSEN) *. .

The above operation may be performed simultaneously. That is, when the information on the address and the data to check the error occurrence condition is input at the same time, the above-described operation on the address and the data is performed at the same time. The control register 108, the address register 110, the data register 112, and the comparison result controller 118 may be designed to be provided in the decoder 106.

As described above, the present invention tracks an error occurrence state of a predetermined address and / or data of a software module by using simple hardware outside the CPU, thereby accurately identifying an error occurrence position while maintaining an online state, and expensive measuring equipment. There are also benefits to reduce the burden of use.

Claims (4)

A central processing unit; A command applier which allows a user to apply an error tracking command for a predetermined address and / or data for a predetermined software module operated in the central processing unit to the central processing unit; A decoder which decodes the address output from the central processing unit and outputs a chip select signal; An address register driven by a chip select signal transmitted from the decoder to store the predetermined address transmitted from the central processing unit via a data bus; A data register which is driven by a chip select signal transmitted from the decoder and stores the predetermined data transmitted from the central processing unit via the data bus; An address comparator for outputting a comparison result signal whenever an address generated during operation of the central processing unit and an address provided from the address register are the same; A data comparator outputting a comparison result signal whenever the data generated during operation of the central processing unit and the data provided from the data register are the same; An interrupt processor for generating a predetermined interrupt signal to the central processing unit when the comparison result signal is transmitted from the address comparator and / or the data comparator; A comparison result control unit for controlling the comparison result of the address comparator and the data comparator to be transmitted to the interrupt processor when the number of occurrences of the comparison result signal from the address comparator and the data comparator reaches a predetermined number; And And a control register configured to store and provide an enable control signal of the address comparator, the data comparator, and the interrupt processor transmitted by the chip select signal transmitted from the decoder and transmitted through the data bus. Error tracking device for software modules. The method of claim 1, wherein when the interrupt signal is transmitted from the interrupt processor, the CPU outputs error tracking details of the predetermined address and / or data applied by the user so that the user can view the interrupt signal. Error tracking device for software modules. The apparatus of claim 1 or 2, wherein the comparison result controller is further configured to compare the comparison result values transmitted from the address comparator and the data comparator to a maximum value for each of the address and data transmitted from the central processing unit through the data bus. Error tracking device for a software module, characterized in that it comprises a count means for counting each. 4. The error tracking device of claim 3, wherein the maximum value for each of the address and data is arbitrarily set by the user.