KR19980066531A - Method of reading data from processor and its device - Google Patents

Abstract

The present disclosure relates to a method and a device for reading data of a processor for efficiently reading a large amount of data from a device having a data bus smaller than the size of the processor's own data bus. The present invention provides a first step of reading data through an interface between a data bus of a device and a higher bit portion of a processor, and reading data through an interface between a data bus of a device and a lower bit portion of a processor. A second step and a third step of combining the data read alternately through the first step and the second step and combining them into one data. Accordingly, the present invention provides an effect that a processor can read data into a single data in a device through a simpler process.

Description

Method of reading data of processor and its device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data read of a processor, and more particularly, to a method of reading a data of a processor for more efficiently reading a large amount of data from a device having a data bus smaller than the size of the processor's own data bus and the same. Relates to a device.

In a processor such as a microprocessor or a digital signal processor, when data is read from a device having a data bus smaller than its own data bus, the data is read through an interface between the data bus of the device and the lower bit portion of the processor. After it is loaded, it is processed internally to produce data the size of its own databus. One example thereof is shown in FIG. 1.

FIG. 1 is a configuration diagram illustrating an example of an interface between a general processor and a device, and illustrates an example of an interface between a 32-bit processor 10 and a 16-bit device 20. Here, the 32-bit processor 10 reads 16-bit data through an interface between the lower 16-bit portion of the 32-bit data bus and the 16-bit data bus of the 16-bit device 20. The 32-bit processor 10 internally performs five steps to produce 32-bit data. That is, the 32-bit processor 10 reads 16-bit data from the 16-bit device 20 and stores the 16-bit data in the lower bit portion of the internal register A. The upper bit portion is shifted left by shifting the 16-bit data stored in the internal register A to the left. In the second step of moving to the second step, the 16-bit device 20 reads 16-bit data and stores the 16-bit data in the lower bit portion of the internal register B. Bit-wise ANDs the stored data of the internal register B and 0FFFFH. 32-bit word through the fourth step of masking the upper bit portion of the internal register B, and the fifth step of bit-logically ORing the stored data of the internal registers A and B and storing them in the internal register A. Create data

However, as described above, the conventional processor has to go through five steps to read data from a device having a data bus smaller than its own data bus and make one word unit data, which is inefficient when a large amount of data must be continuously read.

Accordingly, an object of the present invention is to provide a method for a processor to more efficiently read a large amount of data from a device having a data bus smaller than the size of its data bus.

Another object of the present invention is to provide an apparatus for implementing the above-described method for reading data of a processor in hardware.

1 is a configuration diagram showing an example of an interface between a general processor and a device;

2 is a block diagram showing an apparatus for reading data of a processor according to a preferred embodiment of the present invention.

Explanation of symbols for main parts of the drawings

10: 32-bit processor 20: 16-bit device

31,32: data transmission unit 33: inverter

A data reading method of a processor according to the present invention for achieving the above object, in the method of reading data from a device having a data bus smaller than the size of the processor's own data bus, (1) in the data bus of the device Reading data into the upper bit portion of the data bus of the processor; (2) reading data from the data bus of the device into the lower bit portion of the data bus of the processor; and (3) data of the processor. And logically combining the data read into the upper bit portion and the lower bit portion of the bus into a single data.

A data reading apparatus of a processor according to the present invention for achieving another object of the present invention is a device for reading data from a device having a data bus smaller than the size of the processor's own data bus, according to the selection signal inputted. A first data transfer unit that reads data from the data bus of the device and transfers the data to the upper bit portion of the processor, and reads data from the data bus of the device according to an input selection signal. And a second data transfer unit for transferring the portion to the second data transfer unit by inverting a state of a selection signal input to alternately operate the first data transfer unit and the second data transfer unit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a data reading apparatus of a processor according to the present invention. As shown, the apparatus of the present invention is connected between the upper 16-bit portion of the data bus of the 32-bit processor 10 and the 16-bit data bus of the 16-bit device 20, depending on the selection signal being input. A first data transfer unit 31 for reading data from the data transfer unit and transferring the data to the 32-bit processor 10. The apparatus of the present invention is also connected between the lower 16-bit portion of the data bus of the 32-bit processor 10 and the 16-bit data bus of the 16-bit device 20, and the data from the element 20 in accordance with an input selection signal. The second data transfer unit 32 reads the data and delivers it to the 32-bit processor 10. Here, the data transfer units 31 and 32 each consist of 16 logical AND elements. On the other hand, the second data transfer unit 32 is configured such that the inverter 33 for inverting the state of the selection signal so that the data transfer units 31 and 32 alternately operate.

The operation of the data reading apparatus of the processor according to the present invention configured as described above will be described in more detail.

First, the input clock pulse selection signal of a predetermined period is directly input to the AND products forming the first data transfer unit 31. The selection signal is also input to the inverter 33 to allow the first data transfer unit 31 and the second data transfer unit 32 to operate alternately. The inverter 33 inverts the selection signal of the predetermined periodic clock pulse and inputs the same to the AND products constituting the second data transfer unit 32. The first data transfer unit 31 reads data from the 16-bit device 20 and transmits the data to the upper data bus portion of the 32-bit processor 10 during the period in which the selection signal is at a high (H) level. The 32-bit processor 10 stores 16-bit data transferred to the upper data bus in the upper bit portion of the internal register A. At this time, the second data transfer unit 32 does not operate by receiving a selection signal of a low level through the inverter 33. On the other hand, the first data transfer unit 31 does not operate during the period in which the selection signal is at the low (L) level, and at this time, the second data transfer unit 32 is selected by the inverter 33 at the high (H) level. It operates by inputting. The second data transfer unit 32 reads data from the 16-bit device 20 and transfers the data to the lower data bus portion of the 32-bit processor 10 during the period in which the selection signal is at the high (H) level. The 32-bit processor 10 stores 16-bit data transferred to the lower data bus in the lower bit portion of the internal register B. Thereafter, the 32-bit processor 10 logically operates the internal register A and the internal register B to combine the data stored in the upper bit portion of the internal register A and the lower bit portion of the internal register B to form 32-bit data.

As described above, the present invention relates to a method and a device for reading a data of a processor. In the related art, when a data is read from a device having a data bus smaller than the size of the processor's own data bus, a single word data is created in five steps. Compared to this, one word data can be generated through three steps of two read operations and an operation of logical sum of read data, so that a large amount of data can be read more efficiently.

Claims (4)

In a method of reading data from a device having a data bus smaller than the processor's own data bus, (1) reading data from the data bus of the device into the upper bit portion of the data bus of the processor; (2) reading data from the data bus of the device into the lower bit portion of the data bus of the processor; And And (3) combining the data read into the upper bit portion and the lower bit portion of the data bus of the processor and combining the data into one data. The method of claim 1, wherein the steps (1) and (2) are alternately performed. In an apparatus for reading data from a device having a data bus smaller than the processor's own data bus, A first data transfer unit which reads data from the data bus of the device according to an input selection signal and transfers the data to an upper bit portion of the data bus of the processor; A second data transfer unit which reads data from the data bus of the device according to an input selection signal and transfers the data to a lower bit portion of the data bus of the processor; And And an inverter configured to invert a state of a selection signal input to alternately operate the first data transfer unit and the second data transfer unit, and apply the state to the second data transfer unit. 4. The data reading apparatus of claim 3, wherein the first data transfer unit and the second data transfer unit are each formed of a logical AND device equal to the size of the data bus of the device.