JP2937326B2 - Test circuit for logic circuits - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a logic circuit test facilitating circuit applicable to general arithmetic circuits having a bus structure.

2. Description of the Related Art A scan path method or an ad-hoc method is known as an effective method for testing a logic circuit of a large-scale integrated circuit (LSI), particularly a combination circuit. The former is
The flip-flop in the logic circuit is formed as a shift register as a scan path, and is controlled directly from the outside of the chip, and the result is observed to reconfigure the combinational circuit into a sequential circuit for testing. This method is a reliable and fairly effective test method when the time and hardware required for the test can be increased, and is often used as a test facilitation method for large-scale logic circuits.

For example, as shown in FIG. 6, an adder AD, various input registers A, B,..., A data register D, an output inverting device I, a bus B and a bus driver BL, and signals for controlling these members are represented by FF bits. It is assumed that the scan path method is applied to an arithmetic circuit system including a decoding circuit that decodes and generates a pattern by forming the registers A and B and the data registers D and FF as campuses as shown by broken lines. The circuit shown is a typical arithmetic circuit of a microprocessor having a bus structure. In this circuit, the signal path can be clearly divided into control signals C ₁ , C ₂ ,... C ₆ and a data path 32 bits. . Therefore, it is expected that a test circuit is designed by utilizing such features.

In the scan path method, the flip-flop (FF) group is simply handled as a shift register connected in series, so that the data path and the control signal path are not distinguished and are not efficient.

On the other hand, although the above-mentioned ad hoc method is not shown, for example, taking the example of FIG. 6, the decoding logic L and the adder AD
In this method, a test is performed by inserting a gate into a group of control lines (nodes) indicated by circles between the arithmetic units and directly controlling the nodes via external pins.

(Problems to be Solved by the Invention) However, in the former scan path method, when testing a large-scale logic circuit block including various arithmetic circuits, the test time is significantly increased due to data transfer. In addition, as the bit configuration of the system increases, the number of bits to be scan-passed also increases significantly, resulting in significantly lower test efficiency.

On the other hand, in the latter ad hoc method, since the same number of gates as control lines must be inserted to form test points, the number of external pins dedicated to testing is also required, and the number of arithmetic circuit systems increases. As a result, there was a problem that the price became remarkably large.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a test facilitating circuit capable of significantly improving test efficiency.

[Structure of the Invention] (Means for Solving the Problems) A logic circuit test facilitation circuit according to the present invention is operated by control signals from a plurality of control signal lines, receives input data from a data bus, and receives the control signal A circuit for performing a predetermined operation on the input data in accordance with a control signal on a line and outputting the result to a data bus for facilitating a test of a logic circuit, provided between an external pin for data input / output and the data bus; Bus switch, a plurality of flip-flops provided corresponding to each of the plurality of control signal lines, and connected in series with each other to form a shift register; Respectively connected between an output and the corresponding control signal line, and when the logic circuit performs a normal operation, a control signal of a normal operation is put on the control signal line; When performing the logic circuit test, a plurality of multiplexers each of which puts the signal held in the flip-flop on the control signal, the operation timing of the bus switch, and the signal held in the flip-flop Means for inputting data from the data bus, performing the predetermined operation according to the control signal, and outputting the result to the data bus by controlling the timing of supplying the data to the logic circuit.

(Function) In the circuit for facilitating test of a logic circuit according to the present invention, since the operation data is provided in parallel to the operation means as described above, a large-scale combination circuit such as an operation circuit of a microprocessor is provided. Good and bad tests can be performed at high speed.

(Embodiment) FIG. 1 shows a configuration of an embodiment of a test facilitation circuit according to the present invention. In this embodiment, a description will be given assuming that a 32-bit adder is used for convenience.

That is, the input register associated with the 32-bit adder 1
A2, input register B3, an input data inverting circuit 4, the output data inversion circuit 5, 32-bit internal data bus B has a bus driver 6 for outputting data, the adder 1 two operation control signals C _6, C ₇ It is assumed that there is an arithmetic mode controlled by

Note that a block indicated by a dotted line and including the above-described components surrounding the adder 1 is referred to as an operation block LB. And other control signals C ₁ C ₂ , C ₃ , C ₄ , C ₅ , C ₈ , C ₉
Is a signal for directly controlling the operation block LB except for the _first C ₁ C ₂ . Each flip-flop FF _i (i = 1,2,3 ...
7) the D input and the Q output terminal of to what FF adjacent except FF ₁ at the left end are connected in series, form a shift register, the D input of the FF ₁ is connected to the data input pin P ₁ , when the test mode signal S from the pin P ₂ is not input, i.e., when S = 0, from P ₁ to FF _i, FF from FF _{i i + 1 (i} =
1,2, ..., 7) to but data is gradually shifted, the data when S = 1 is set in the FF _i is held.

The output of control signals C ₁₀ ,..., C ₁₆ and FF ₁ ... FF ₇ for performing a normal operation is given to each multiplexer M _i (i = 1, 2, 3,... 7). = data set in the FF _i in 1 control signal C ₃ -C ₉
Given to.

When S = 0, C _{10 to} C ₁₆ are given to C _{3 to} C ₉ .

Further P ₃ in the figure shows the data pins, 7 denotes a bus switch for performing output control of data to the internal data bus B, the latter is composed of two buffers, the control signal C _1, C ₂ It is controlled. AND gate
G _{i (i} = 1,2,3,4,5) is a timing signal T _A which is generated during the test mode _{(S = 1), T B} , T C, the output or the T _D, T _E and FF _i An AND operation with the signal S is performed, and an output signal is generated depending on the condition.

FIG. 2 shows a configuration example of a timing signal generating circuit for generating the timing signal shown in FIG.
₁₀ and FF ₁₁ , two inverters I ₁ , II ₂ , two AND gates A ₁ , A ₂ , and the timing signals T _A , T _B , T _C shown in the figure by a test timing signal Tin and a clock signal CLK. , T _D , T _E
Occurs.

Next, the operation of the circuit for facilitating test of a logic circuit according to the present invention having the above-mentioned configuration will be described with reference to the timing chart of FIG.

During normal operation (S = 0), and transfers from the pin P ₁ sequentially FF _i data. That is, a bit pattern in which 1 bit, 3 bits, and 7 bits are 1 as in 1010001 is set to control the bus access timing.

Next, after the desired data has been transferred to the FF _i , the test mode signal S is set to 1 and a predetermined component of the operation block LB can be controlled by the contents of the shift register composed of the FF _i . Next, a test timing signal Tin is supplied to the timing generation circuit shown in FIG. 2 to generate timing signals T _A , T _{B ,.}
The logical product of the AND gates G ₁ , G ₂ , G ₃ , G ₄ , G ₅ is obtained, and the output thereof controls each member shown in FIG.

For example, test data given in cycles I sequence I of the test execution sequence data pin P ₃ is outputted to the internal data bus B, placed from the bus to the register A by T _C = 1. Similarly test data from P ₃ in cycle II is entered in the register B via the bus B. In cycle III, the data stored in both registers AB is added by adder 1 and the addition result is output to bus B via bus driver 6 when TE = 1.

At the same time, when T _B = 1, the bus switch 7 is switched,
The addition result data output to the bus B is applied to the data pin P ₃
Given to.

As described above, in the test facilitation circuit according to the present invention, the test of the adder can be executed once in three cycles I, II, and III. Therefore, an arbitrary test can be executed by repeating the test sequence as I, II,... That is, as can be seen from the timing chart of FIG. 3, one test of the adder can be performed at a high speed such that the test is completed in three clock cycles after entering the test mode (after setting S = 1). while being executed, if the data pin P ₃ already exists, pins necessary for the test requires only a small hardware over Hett so requires only 3 pins P _1, P _2, Tin.

FIG. 4 shows a second embodiment of the test facilitation circuit according to the present invention. In this embodiment, FF ₂ of the second first view for ease of illustration, the AND gate G _4, three sets of each component, such as a multiplexer M ₂ shown in F _1, the fifth, etc. of two sets of components, such as FF and the multiplexer M is indicated by F _2. The adder and its related components are indicated by an operation block LB.

The difference between this embodiment and the embodiment shown in FIG. 1 is that a decode logic circuit DL is connected to each control line (node) entering the operation block.
When the timing signals T _A , T _B , T _C … are issued based on the output signals from the respective FFs, the output signals are decoded and the decoded output is given to each member in the operation block. A similar test should be performed.

FIG. 5 shows a third embodiment of the test facilitation circuit according to the present invention.

In this embodiment, a plurality of operation blocks I, II, III
Each flip-flop is used when a test is required.
FF chains (shift registers) MI, M II, and M III are provided so that a specific operation block can be independently selected by each FF chain to perform a test. For example, when the operation block II is selected and tested, if the bit “O” is transferred to a portion related to the output control of the FF chain MI and MIII bus, MI and MIII are shut off, Only Arithmetic Block II can be tested independently.

[Effects of the Invention] The circuit for facilitating the test of the logic circuit according to the present invention has been described above. However, in the present invention, the test can be performed at high speed with a small number of pins.

In addition, when a test is performed on a plurality of operation blocks, a specific operation block can be selected and performed independently, so that it is convenient and wasteful.

[Brief description of the drawings]

FIG. 1 is an embodiment of a circuit for facilitating test of a logic circuit according to the present invention, FIG. 2 is a detailed view of a configuration example of a timing signal generating circuit for generating each timing signal of FIG. 1, and FIG. 4 is a timing chart for explaining the operation of the test facilitating circuit of FIG. 4, FIG. 4 is a second embodiment of the test facilitating circuit of the present invention, FIG. 5 is a third embodiment of the test facilitating circuit of the present invention, FIG. 6 shows one conventional logic circuit test method.
Are respectively shown. In the figure, 1 is an adder, 2 is an input register A, 3 is an input register B, 4 and 5 are data inverting circuits, 6 is a bus driver, FF _i (i = 1, 2,...) Is a flip-flop, M _i ( i =
1, 2, 3) is a multiplexer, the bus switch 7, B is an internal data _{bus, G i (i = 1,2,3,} ... 5) are AND gates, each pin P ₁ P ₂ P _3, LB Indicates an operation block.

 ──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-61-218963 (JP, A) JP-A-58-154038 (JP, A) JP-A-56-164425 (JP, A) JP-A-61-164425 112248 (JP, A) JP-A-60-239836 (JP, A)

Claims (2)

(57) [Claims] An operation is performed by a control signal from a plurality of control signal lines, input data is received from a data bus, a predetermined operation is performed on the input data according to a control signal on the control signal line, and the result is sent to the data bus. A bus switch provided between an external pin for data input / output and a data bus, the circuit for facilitating a test of a logic circuit to be output;
A plurality of flip-flops provided corresponding to each of the plurality of control signal lines and connected in series with each other to form a shift register; and the control corresponding to each output of the flip-flop. A control signal for normal operation is put on the control signal line when the logic circuit performs a normal operation, and the flip-flop is used when a test of the logic circuit is performed. A plurality of multiplexers for respectively putting the signals held in the control signal on the control signal, and controlling the operation timing of the bus switch and the timing of supplying the signal held in the flip-flop to the logic circuit Means for inputting data from the data bus, performing the predetermined operation according to the control signal, and outputting the result to the data bus. Test circuit of a logic circuit formed. 2. The means for controlling timing comprises: an output provided to the bus switch and the multiplexer;
A signal indicating a test operation and an output of the flip-flop are provided to one of the inputs, and a timing signal necessary for the operation of the logic circuit is provided to the other of the plurality of ANs.
2. The test facilitation circuit according to claim 1, comprising a D gate.