KR101419335B1 - Apparatus and method for page unit clustering of multi level cell flash memory - Google Patents

Abstract

Two bits per cell are stored. The most significant bit of the two bits constitutes the MSB (Most Significant Bit) page, and the lower bit is the page of the multilevel cell flash memory constituting the LSB (Least Significant Bit) page. Clustering apparatus for clustering is disclosed. The clustering unit forms a first clustering page by grouping the first MSB page and the first LSB page together in the first channel. The ECC unit applies a different ECC (Error Correction Code) to the first MSB page and the first LSB page. The control unit may include a first spare area excluding the first data area of the first MSB page among the first parity bits generated after the data is encoded in the first MSB page in the first clustering page The excess second parity bit is stored in the second spare area excluding the second data area of the first LSB page in the first clustering page. According to the present invention, by changing the structure of the clustered page, the error imbalance phenomenon existing between the MSB page and the LSB page is solved and the lifetime of the MSB page is extended, thereby improving the reliability of the entire solid state device You can.

Description

[0001] Apparatus and method for page level clustering of multi-level cell flash memory [

The present invention relates to an apparatus and method for clustering pages in a multi-level cell flash memory, and more particularly, to a method and apparatus for page level clustering in a multi-level cell flash memory, in which, in consideration of the difference in error rates between MSB pages and LSB pages, To an apparatus and method for page-by-page clustering of a multi-level cell flash memory.

NAND flash memory is attracting attention as a substitute resource for replacing existing magnetic disk storage media because of advantages such as low power and miniaturization. In particular, instead of a single level cell (SLC) storing one bit per cell, the use of a multi level cell (MLC) storing more than two bits per cell is increasing, .

The MLC NAND flash stores two bits per cell, and the two bits are divided into upper and lower bits. The upper bit consists of the MSB page and the lower bit consists of the LSB page. In MLC NAND flash, MSB page and LSB page data have different sensing process of bit and MSB page sensing process is more complicated than LSB page sensing process. However, the controller of the currently used MLC NAND flash corrects the error by using the same performance error correction code (ECC) in both the MSB page and the LSB page. This causes a life imbalance phenomenon in which an MSB page having a large number of errors becomes shorter than an LSB page. In addition, in the case of the LSB page, a high performance error correction code (ECC) is used rather than an error occurrence frequency, thereby causing overhead in terms of latency and spare area for a read operation.

In addition, a solid state drive (SSD) composed of MLC NAND arrays has a clustered page structure, MSB pages are clustered between MSB pages, LSB pages are clustered between LSB pages, MSB pages are clustered page ) Is significantly shorter than the clustered page clustered LSB pages. This is also a phenomenon that occurs when a stronger error correcting code (ECC) can not be used due to a shortage of a spare area.

Specifically, Korean Patent Laid-Open Publication No. 2009-0022435 (a system including a multi-bit flash memory device and a data processing method thereof) is provided with a memory for storing a plurality of pages And a data management method that can reduce the influence of the data. This is achieved by programming a plurality of memory cells into any one of the pages reconstructed according to the error detection coding scheme. In this case, when an error occurs in the program stage, the validity of any one page is determined by using an error detection code read from a plurality of memory cells .

In addition, in Korean Laid-Open Publication No. 2006-0023428 (entitled " NAND flash memory device and its copy back program method "), an error occurs during copy backup program operation (operation of moving data stored in the first page to the second page) And terminating the copy-back program when it is detected. This reads data stored in a cell array to detect an error, programs the data in accordance with an error detection result, and terminates the copy back program operation when an error is detected.

An object of the present invention is to provide an apparatus and method for clustering pages of a multi-level cell flash memory in which the speed of read / write operations is increased through clustering and the size of metadata to be managed can be reduced. In addition, since the clustered page is recognized as one page in the SSD (Solid State Device) operation, the clustered pages configured over the multiple channels can operate in parallel as many as the number of channels, Level cell flash memory, and a page level clustering apparatus and method for a multi-level cell flash memory.

According to another aspect of the present invention, there is provided a page level clustering method for a multi-level cell flash memory in which a speed of a read / write operation is improved through clustering and a size of metadata to be managed can be reduced, And an object of the present invention is to provide a computer-readable recording medium having recorded thereon a computer program. In addition, since the clustered page is recognized as one page in the SSD (Solid State Device) operation, the clustered pages configured over the multiple channels can operate in parallel as many as the number of channels, Readable recording medium on which a program for causing a computer to execute a page-by-page clustering method of a multi-level cell flash memory is provided.

According to an aspect of the present invention, there is provided a page level clustering apparatus for a multi-level cell flash memory, which stores two bits per cell, and the most significant bit of the two bits is a most significant bit ) Page and the lower bits are clustered in page units in a multi-level cell flash memory constituting a LSB (Least Significant Bit) page, wherein the first clustering unit groups the first MSB page and the first LSB page together in the first channel, A clustering unit that constitutes a clustering page; An ECC unit applying different ECC (Error Correction Code) to the first MSB page and the first LSB page; And a first spare area excluding a first data area of the first MSB page among first parity bits generated after data is encoded in the first MSB page in the first clustering page, ) In a second spare area excluding a second data area of the first LSB page in the first clustering page (step < RTI ID = 0.0 > .

According to another aspect of the present invention, there is provided a page-level clustering apparatus for a multi-level cell flash memory, comprising: a first clustering unit configured to group a first MSB page and a first LSB page in a first channel, And a second clustering page is formed by grouping the second MSB page and the second LSB page in a second channel different from the first channel so that the first clustering page and the second clustering page are grouped together to constitute a third clustering page A clustering unit; An ECC unit applying different ECC (Error Correction Codes) to the first MSB page and the first LSB page, the second MSB page, and the second LSB page; And a first spare area excluding a first data area of the first MSB page among first parity bits generated after data is encoded in the first MSB page in the first clustering page, ) In a fourth spare area excluding a fourth data area of the second LSB page in the second clustering page is included in the second clustering page .

According to another aspect of the present invention, there is provided a page-level clustering method of a multi-level cell flash memory, which stores two bits per cell, and the most significant bit of the two bits is an MSB Bit cell in a multi-level cell flash memory, the low-order bits being LSB (Least Significant Bit) pages, the method comprising the steps of: (a) And a first LSB page to form a first clustering page; (b) applying a different ECC (Error Correction Code) to the first MSB page and the first LSB page; And (c) a first spare area, excluding a first data area of the first MSB page, among first parity bits generated after data is encoded in the first MSB page in the first clustering page, storing a second parity bit exceeding a spare area in a second spare area excluding a second data area of the first LSB page in the first clustering page; .

According to another aspect of the present invention, there is provided a page level clustering method for a multi-level cell flash memory, the method comprising: (a) clustering a first MSB page and a first LSB page in a first channel, ), Constituting a second clustering page by grouping a second MSB page and a second LSB page in a second channel different from the first channel, and combining the first clustering page and the second clustering page together, Constituting a page; (b) applying a different ECC (Error Correction Code) to the first MSB page and the first LSB page, the second MSB page, and the second LSB page; And (c) a first spare area, excluding a first data area of the first MSB page, among first parity bits generated after data is encoded in the first MSB page in the first clustering page, storing a fourth parity bit exceeding a spare area in a fourth spare area excluding a fourth data area of the second LSB page in the second clustering page; .

According to an apparatus and method for page unit clustering of a multi-level cell flash memory according to the present invention, clustering improves the speed of read / write operations and reduces the size of metadata to be managed. In addition, since the clustered page is recognized as one page in the SSD (Solid State Device) operation, the clustered pages configured over the multiple channels can operate in parallel as many as the number of channels, have. That is, an apparatus and method for clustering per page of a multi-level cell flash memory according to the present invention can solve the error imbalance phenomenon existing between the MSB and LSB pages by changing the structure of the clustered page and extend the lifetime of the MSB page The reliability of the entire solid state device (SSD) can be improved.

1 is a diagram showing a clustering page structure of a conventional solid state device (SSD)
FIG. 2 is a block diagram showing the configuration of a page-by-unit clustering apparatus of a multi-level cell flash memory according to the present invention;
3 is a diagram showing a page configuration clustered by a page unit clustering method of a multi-level cell flash memory according to the present invention,
4 is a diagram illustrating a method of storing parity bits in a clustered page by a page unit clustering method of a multi-level cell flash memory according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout.

A solid state device (SSD) uses a clustering page, which is a cluster of pages of a conventional NAND flash memory, as a unit of basic read / write operation when processing data. Therefore, as shown in FIG. 1, by using the pages located at the same offset for each channel, the size of the meta data increases and manages the speed of operation through parallelization using a plurality of channels, thereby reducing the size of the DRAM and the NAND flash memory It is possible to save the capacity of the battery. In order to ensure reliability, an error correction code (ECC) is used. A parity bit is generated after data is encoded in a spare area separately from a data area where data is stored. And the like. The stored parity bit is used to read and decode the error in the read operation.

That is, conventionally, as shown in FIG. 1, pages having block numbers of the same offset in the NAND flash memory connected to each channel are clustered one by one. Such a clustered page is recognized as one page in the SSD operation and is recognized as a page in the software level such as FTL (Flash Translation Layer) and the information in the mapping table. Clustering pages constructed over several channels can operate in parallel as many as the number of channels, thereby improving the operation speed of processing large data. In addition, if you do not cluster, you must keep the address and state of all pages in the mapping table, whereas clustering will reduce the number of addresses that are kept in inverse proportion to the number of clustering pages. Therefore, clustering improves the speed of read / write operations and reduces the size of the metadata to be managed.

In the ECC encoding process, parity bits are generated in addition to the existing data. Which increases in proportion to the error correction capability. This parity bit is stored in the spare area of the NAND flash memory page in the order of the sector of the page or the ECC block. In case of decoding, the data area and the parity bit of the spare area are simultaneously read to find the error. If an error is detected, the original data is recovered and transmitted to the host. If necessary, the corrected data is stored again in the NAND flash memory .

However, in the MLC NAND flash, the data of the MSB page and the LSB page are different in the sensing process of reading the bits, and the sensing process of the MSB page is more complicated than the sensing process of the LSB page. Therefore, in order to guarantee the life of the LSB page level, the MSB page requires more powerful ECC than the LSB page, and more space is needed to store the parity bits. The parity bit is stored in the spare area of each page, and the limitation of the spare area has a decisive influence on the life of the NAND flash memory.

Therefore, in the present invention, as shown in FIG. 1, instead of clustering MSB pages between MSB pages and LSB pages by LSB pages, MSB pages and LSB pages are clustered together so that different ECCs And stores the parity bits of the MSB page in the spare area of the LSB page to improve the reliability of the MSB page by using a better performance ECC on the MSB page.

2 is a block diagram showing the configuration of an apparatus 200 for page-by-page clustering of a multi-level cell flash memory according to the present invention. The page-level clustering apparatus 200 of the multi-level cell flash memory according to the present invention may include a clustering unit 210, an ECC unit 220, and a control unit 230.

The MLC NAND flash memory consists of an LSB page and an MSB page in one block. Therefore, if two adjacent pages are clustered, the MSB page and the LSB page can be included in one clustering page at the same time, and the characteristics of the NAND flash memory in which the write operation must be performed sequentially in the page number can be maintained.

More specifically, referring to FIG. 3, the clustering unit 210 forms a first clustering page by grouping the first MSB page and the first LSB page together in the first channel. Furthermore, a third clustering page may be formed by grouping the second clustering page and the first clustering page, which are generated by grouping the second MSB page and the second LSB page together in a second channel different from the first channel.

The ECC unit 220 applies a different ECC (Error Correction Code) to the first MSB page and the first LSB page. As described above, the MSB page is much more error-prone due to the physical characteristics of the NAND flash memory than the LSB page. Therefore, even within one clustering page, it is desirable that the MSB page use better ECC than the LSB page. Therefore, the MSB page uses a better performance ECC than the LSB page, so that the lifetime of the MSB page can be guaranteed by the LSB page. That is, the ECC unit 220 applies ECC having better error correction performance to the first MSB page and the second MSB page than the first LSB page and the second LSB page, respectively.

However, since the size of the spare area is determined for each page, there is not enough space to store the parity bits generated in the MSB page. Therefore, if a portion of the parity bits of the MSB page in one clustering page that can not be stored in the spare area of the MSB page is stored in the spare area of the LSB page as shown in FIG. 4, the better performance ECC is used for the MSB page It becomes possible. In addition, when the overhead of reading and writing the page in the same block twice during the read operation and the write operation is taken, the reliability of the entire SSD is improved and the service life is prolonged.

More specifically, referring to FIG. 4A, the control unit 230 determines whether or not the first MSB page of the first MSB page among the first parity bits generated after the data is encoded in the first MSB page in the first clustering page The second parity bit exceeding the first spare area excluding the first data area is a parity bit of the second cluster area excluding the second data area of the first LSB page in the first clustering page. It is stored in the spare area.

4B, a first data area of the first MSB page among the first parity bits generated after data is encoded in the first MSB page in the first clustering page, The fourth parity bit exceeding the first spare area is stored in the fourth spare area excluding the fourth data area of the second LSB page in the second clustering page do. In addition, a third spare area excluding the third data area of the second MSB page among the third parity bits generated after the data is encoded in the second MSB page in the second clustering page is referred to as a " spare area " The exceeding third parity bit is stored in the second spare area excluding the second data area of the first LSB page in the first clustering page.

That is, FIG. 4A illustrates a method of storing parity bits of an MSB page using a spare area of an LSB page in the same channel, and FIG. 4B illustrates a method of storing spare bits of LSB pages of different channels Lt; RTI ID = 0.0 > MSB < / RTI >

4A, a parity bit having a size exceeding a spare area among parity bits of the same MSB page is stored in a spare area of an LSB page belonging to the same clustering page in the same channel. That is, parity information of five sectors among eight sectors belonging to the MSB page is stored in the spare area of the MSB page, and parity bit information corresponding to the remaining three sectors is stored in the LSB of the same channel And stored in the spare area of the page.

4B, in order to ensure parallelism when reading the MSB page, the parity bit of the MSB page is set to the spare area of the LSB page of the channel other than the LSB page of the same channel, . In this case, when the MSB page of the first channel is accessed in the case of storing in the spare area of the LSB page of another channel, the method of (a) is such that the LSB page and the MSB page are once read in one channel, ) Operation occurs. Therefore, the speed of read operation is doubled. However, in the case of the (b) method, when the MSB page is read, one page at a time is simultaneously read to the first channel and the second channel, and the speed at which the page is read is the same as when reading one page.

An embodiment in which a page unit clustering method of a multi-level cell flash memory according to the present invention is actually implemented will be described. Table 1 below is based on 4 Gbyte MLC and its specification is as follows.

1 page size 8 Kbytes spare size 640 byte page / block 256 chip / block 2048

The specification of the BCH code, which is a type of ECC that performs error correction in 2 Kbyte units, is shown in Table 2 below.

(n, k, t) BCH Codes Latency (㎲) parity bits (bits per 2K) One (16459, 16384, 5) 20.7 75 2 (17914, 16384, 102) 40.2 1530

That is, assuming that four 4-Gbyte MLC NANDs in Table 1 are used to form a 4-channel 1-way SSD, one NAND is formed per one channel. Pages with the same offset in each channel constitute one clustering page. Therefore, in this case, a clustering page is constructed as shown in FIG. 1, and one clustering page has a size of 34 KB.

However, as shown in FIG. 3, in the page level clustering method of the multi-level cell flash memory according to the present invention, unlike the conventional method, one MSB page and one LSB page are clustered in one channel, Unlike clustering four pages one by one, clustering one MSB page and one LSB page per channel in two channels makes four pages into one clustering page.

In this case, we apply the 1st BCH in Table 1 to the LSB page and apply the 2nd BCH to the MSB page. When applied to an LSB page, the number of parity bits generated is 300 bits, which is large enough to be stored in the spare area. However, the MSB page generates 875 Bytes of parity bits, which is insufficient even using the entire spare area. Therefore, as shown in FIG. 4, a part of the parity bit is stored in the remaining part of the spare area of the LSB page.

Accordingly, the page-by-page clustering method of the multi-level cell flash memory according to the present invention can solve the error imbalance phenomenon existing between the MSB and LSB pages by changing the structure of the clustering page, The reliability of the entire SSD can be improved.

In the above description, terms such as 'first', 'second', and the like are used to describe various components, but each component should not be limited by these terms. That is, the terms 'first', 'second', and the like are used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a 'first component' may be referred to as a 'second component', and similarly, a 'second component' may also be referred to as a 'first component' . Also, the term " and / or " is used in the sense of including any combination of a plurality of related listed items or any of the plurality of related listed items.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and a carrier wave (transmission via the Internet). In addition, the computer-readable recording medium may be distributed to a computer system connected to a wired / wireless communication network, and a computer-readable code may be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation in the embodiment in which said invention is directed. It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the appended claims.

200: Per-page clustering device of multi-level cell flash memory
210: clustering unit
220: ECC Department
230:

Claims (12)

And the lower bit of the multi-level cell flash memory constitutes a least significant bit (LSB) page. In the multi-level cell flash memory, CLAIMS 1. A clustering apparatus for clustering a plurality of clusters
A clustering unit for grouping a first MSB page and a first LSB page in a first channel to form a first clustering page;
An ECC unit applying different ECC (Error Correction Code) to the first MSB page and the first LSB page; And
A first spare area excluding a first data area of the first MSB page among first parity bits generated after data is encoded in the first MSB page in the first clustering page, And a second parity bit that is greater than the first parity bit in the second clustering page is stored in a second spare area excluding a second data area of the first LSB page in the first clustering page Wherein said page level clustering device is a multi-level cell flash memory. The method according to claim 1,
Wherein the clustering unit forms a third clustering page by grouping the second clustering page generated by grouping the second MSB page and the second LSB page together in the second channel different from the first channel together with the first clustering page A page - level clustering device for multi - level cell flash memory. 3. The method according to claim 1 or 2,
Wherein the ECC unit applies an ECC having better error correction performance to the first MSB page and the second MSB page than the first LSB page and the second LSB page, respectively. 3. The method of claim 2,
Wherein the control unit includes a first data area of the first MSB page excluding a first data area of the first MSB page among first parity bits generated after data is encoded in the first MSB page in the first clustering page and a fourth parity bit exceeding a spare area is stored in a fourth spare area excluding a fourth data area of the second LSB page in the second clustering page A page-level clustering device of a multi-level cell flash memory. 5. The method of claim 4,
The controller may further include a third spare area (spare) excluding a third data area of the second MSB page among a third parity bit generated after the data is encoded in the second MSB page in the second clustering page. area in the first clustering page is stored in a second spare area excluding a second data area of the first LSB page in the first clustering page A page - level clustering device for multi - level cell flash memory. And the lower bit of the multi-level cell flash memory constitutes a least significant bit (LSB) page. In the multi-level cell flash memory, CLAIMS 1. A method for clustering,
(a) grouping a first MSB page and a first LSB page together in a first channel to form a first clustering page;
(b) applying a different ECC (Error Correction Code) to the first MSB page and the first LSB page; And
(c) a first spare area, excluding a first data area of the first MSB page, among first parity bits generated after data is encoded in the first MSB page in the first clustering page storing a second parity bit exceeding a spare area in a second spare area excluding a second data area of the first LSB page in the first clustering page; Level cell flash memory in a page-by-page clustering manner. The method according to claim 6,
In the step (a), a second clustering page generated by grouping a second MSB page and a second LSB page in a second channel different from the first channel and the first clustering page are grouped together to form a third clustering page A method for clustering pages in a multi-level cell flash memory. 8. The method of claim 7,
Wherein the step (b) applies an ECC having a better error correction performance to the second MSB page than the second LSB page. The method according to claim 6,
And the step (b) applies an ECC having a better error correction performance to the first MSB page than the first LSB page. 8. The method of claim 7,
A first spare area excluding a first data area of the first MSB page among first parity bits generated after data is encoded in the first MSB page in the first clustering page, And a fourth parity bit exceeding the first data area is stored in a fourth spare area excluding the fourth data area of the second LSB page in the second clustering page. A method for page - by - page clustering of cell flash memory. 11. The method of claim 10,
A third spare area excluding a third data area of the second MSB page among a third parity bit generated after data is encoded in the second MSB page in the second clustering page, And a third parity bit that is greater than the first parity bit is stored in a second spare area excluding a second data area of the first LSB page in the first clustering page. A method for page - by - page clustering of cell flash memory. A computer-readable recording medium having recorded thereon a program for causing a computer to execute a page unit clustering method of the multi-level cell flash memory according to any one of claims 6 to 11.

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