KR101417827B1 - Apparatus and method for controlling flash memory for storing error correction code - Google Patents

Abstract

A flash memory control apparatus and method for storing an error correction code are disclosed. The host interface unit transmits and receives control signals and data to and from the host, and the memory interface unit receives the write control signals from the host together with the write control signals And the error correction code generated in correspondence with the write target data and the write target data is stored in a page of the flash memory, and a region corresponding to a predetermined number of sectors among the plurality of sectors corresponding to the data region in which the write target data is stored To the storage area of the error correction code. According to the present invention, by using a part of the memory area for data storage for storing the error correction code, compared with the conventional error correction code storage techniques such as a method using a RAID-5 structure or a method using an external expansion block Since the data and the error correction code for the same page can be stored in the same page, the delay time for reading and writing the external page can be reduced.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to an apparatus and a method for controlling a flash memory for storing an error correction code,

The present invention relates to a flash memory control apparatus and method for storing an error correction code, and more particularly, to an apparatus and a method for controlling a process of storing an error correction code used for error correction of data stored in a flash memory .

NAND flash memory has excellent random read / write performance compared to hard drives and is used to build storage on server systems that process many user requests concurrently. Recently, NAND flash memories have been widely used as solid state drives (SSD) and storage devices for portable devices due to their low power consumption and large capacity.

Meanwhile, the manufacturing cost of the NAND flash memory has been reduced due to the miniaturization of the production technology of the NAND flash memory and the introduction of multi level cell (MLC) technology which stores a plurality of bits in one storage cell. However, The reliability and durability are degraded, and error detection and correction techniques are used accordingly.

The controller of the NAND flash memory uses an error correction code (ECC) for error correction. The error correction code is generated during the data transfer time and stored in the spare area with the data page during the page program time do. Since the large capacity NAND flash memory device performs a write operation in both the data area and the spare area using the program command, no additional overhead for storing the error correction code occurs. The stored error correction code is decoded when the data is read during the page read time, and the error corrected data is returned to the host by the error correction code. The information stored in the data area and the spare area can be read by a single read operation as in the case of performing the write operation.

The controller of the NAND flash memory generally uses the BCH code algorithm as the error correction code. The BCH code algorithm requires a 13-bit error correction code to correct a 1-bit error in a sector of 512 bytes in size. In addition, flash memory based on 3-bit multi-level cells (MLC) and 20-nanometer memory fabrication processes, which are recently produced, have a significant increase in error rate per sector, and an error correcting code of 24 bits or 40 bits per 1024 bytes is recommended.

RAID-5 is a technique commonly used in high-reliability storage systems. FIG. 1 is a diagram for explaining a conventional RAID-5 technique. In FIG. 1, five storage devices are connected in parallel and four storage devices are used for general data storage. Four storage devices are connected to one storage device A parity bit for error correction of stored data is stored.

As described above, according to RAID-5, 1/5 of the storage area is used for error correction. Therefore, it is possible to implement a highly reliable storage medium. However, since it is inefficient in terms of storage efficiency, a storage device based on NAND flash memory In this paper, we propose a technique to improve the RAID structure and store the error correction code in the area where the parity bits are stored. However, there is a problem that a delay occurs due to an operation of reading and writing a specific page for processing an error correction code in a data read / write operation.

In order to secure the storage area of the error correction code necessary for applying the BCH code algorithm, a technique of using an external expansion block is proposed. 2 is a diagram for explaining a technique using an external expansion block. 2, an error correction code of a low-performance BCH code algorithm such as a 4-bit error correction is first stored in a spare area of a corresponding page, and an error correction code of a high-performance BCH code algorithm such as 24- And the second block is stored in the expansion block. When this method is used, generally an error correction code stored firstarily is used to correct the error. However, if an error that can not be corrected firstly occurs, the error correction code stored in the second order is used to correct the error, .

However, when the technique using the external expansion block is used, there is an overhead to generate and store two error correction codes for one piece of data. In the case where the number of times of deletion of the corresponding block increases due to the life of the storage device There is a disadvantage that two pages must be read and restored each time for error correction.

Korean Unexamined Patent Publication No. 1998-0038438 discloses a method of encoding sector information of a sector by separately encoding an overhead area and correcting an error occurring in a sector in a sector by an error correction code . However, this method also has a problem in that the problem of securing an additional area for storing an increased size of error correction code can not be solved.

SUMMARY OF THE INVENTION The present invention is directed to a flash memory controller for storing an error correction code for storing a large number of error correction codes in a page where data of a flash memory is to be stored, Method.

According to an aspect of the present invention, there is provided an apparatus for controlling flash memory for storing an error correction code, the apparatus comprising: a flash memory for storing data in units of pages; A host interface unit for transmitting / receiving control signals and data to / from the host; And an error correcting code generated corresponding to the write target data and the write target data received together with the write control signal from the host, in a page of the flash memory, wherein a plurality And a memory interface unit for additionally allocating an area corresponding to a predetermined number of sectors among the sectors of the page to the storage area of the error correction code, The sectors corresponding to the predetermined number of sectors are divided into the remaining sectors except for the number of sectors and allocated to the storage area of an additional error correction code.

According to another aspect of the present invention, there is provided a method of controlling a flash memory for storing an error correction code, the method comprising: storing data in units of pages; controlling the flash memory to include a predetermined number of sectors; (A) receiving data to be written together with a write control signal from a host; (b) generating an error correction code corresponding to the data to be written; And (c) storing the write target data and the error correction code in a page of the flash memory, wherein an area corresponding to a predetermined number of sectors among a plurality of sectors corresponding to a data area in which the write target data is stored is Further comprising the steps of: (a) allocating a predetermined number of sectors of the plurality of sectors constituting the page to a sector of the error correction code; The sector corresponding to the sector is divided and allocated to a storage area for an additional error correction code.

According to an apparatus and method for controlling a flash memory for storing an error correction code according to the present invention, by using a part of a memory area for storing data for storing an error correction code, a method using a RAID- It is possible to store the data and the error correction code thereon in the same page as compared with the conventional error correction code storing schemes such as the method of using it, so that the delay time for reading and writing the external page can be reduced.

FIG. 1 is a diagram for explaining a conventional RAID-5 technique,
2 is a diagram for explaining a technique using an external expansion block,
3 is a block diagram showing a configuration of a preferred embodiment of a flash memory control apparatus for storing an error correction code according to the present invention;
4 is a diagram showing an existing method in which data and error correction codes are stored in one page,
5 is a diagram illustrating a method of storing data and an error correction code in one page in the present invention.
6 is a graph showing the number of error correctable bits according to the number of sectors used as a spare area in one page of the flash memory,
7 is a diagram illustrating an example of a clustering page used in an SSD using a multi-chip;
FIG. 8 is a graph showing a relationship between a correctable block error rate (CBER) and a raw bit error rate (RBER) according to the number of error correctable bits,
FIG. 9 is a graph illustrating a normalized error delay time, which is obtained by applying the conventional error correction code storing technique and the present invention,
10 is a flowchart illustrating a method of controlling a flash memory control method for storing an error correction code according to an exemplary embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of a flash memory control apparatus and method for storing an error correction code according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram showing a configuration of a preferred embodiment of a flash memory control apparatus for storing an error correction code according to the present invention.

3, a flash memory control apparatus 100 according to the present invention operates between a host 200 and a flash memory 300, and includes a host interface unit 110 and a memory interface unit 120. The flash memory control apparatus 100 may further include a buffer unit (not shown) in which data transferred between the host 200 and the flash memory 300 is stored.

The host interface unit 110 transmits and receives control signals and data to and from the host 200 in the flash memory control apparatus 100. The memory interface unit 120 receives the write target data And the error correction code generated corresponding to the write target data in the page of the flash memory 300. [

The flash memory 300 is constituted by a plurality of blocks, which are basic units of data erase operations, and the blocks are composed of a plurality of pages which are basic units of read and write operations. The page is composed of a plurality of sectors, and each sector is composed of a data area for storing actual data and a spare area for storing information such as an error correction code for managing the data area .

4 is a diagram showing an existing method in which data and error correction codes are stored in one page. Referring to FIG. 4, a page of (16K + 512) bytes consists of 32 sectors, and each sector is (512 + 16) bytes in size. Each sector is composed of a data area of 512 bytes size and a spare area of 16 bytes size, and data and an error correction code are respectively stored.

As described above, the page size grows linearly while the error occurrence probability increases exponentially, and the spare area in which the error correction code is stored becomes insufficient. Accordingly, the memory interface unit 120 of the flash memory control apparatus 100 according to the present invention further allocates the ECC storage area in which the error correction code is stored by adjusting the number of sectors constituting the page, The same effect as that of the increase in the number of pixels is obtained.

5 is a diagram illustrating a method of storing data and an error correction code in one page in the present invention. The page size of FIG. 5 is (16K + 512) bytes. It can be seen that the page size of FIG. 4 and the flash memory 300 are the same, but the number of sectors is reduced to 31 by one. In the page of the flash memory 300 shown in FIG. 5, each sector is composed of a data area of 512 bytes and an ECC storage area of (32 +?) Bytes, where? = (The size of the reduced sector / )to be.

The number of sectors to be used as the ECC storage area can be adjusted by setting, and preferably, an area corresponding to one sector can be used as the ECC storage area. Also, as a part of a sector is used as an ECC storage area, a host can read / write requests by allocating another page to data that is outside the reduced data area size.

In this way, by using a part of the sector of the flash memory 300 as the ECC storage area, the memory interface unit 120 stores the error correction code for the write target data in the same page as the write target data, Since the error correction code is stored in succession to the data, it is possible to perform error correction without delay in accordance with the sector unit operation of the host.

Then, when the read control signal of the data stored in the flash memory 300 is received from the host 200, the memory interface unit 120 reads the read target data corresponding to the read control signal and the error correction code corresponding to the read target data Reads data from the same page of the memory 300, performs error correction on the data to be read, and outputs the data to the host 200 through the host interface unit 110.

6 is a graph showing the number of error correctable bits according to the number of sectors used as an ECC storage area in one page of the flash memory 300. As shown in FIG. Referring to FIG. 6, the number of sectors for data storage is adjusted to secure a storage area for an error correction code, thereby storing an error correction code of an increased bit for high performance error correction in an error correction method such as a BCH code algorithm .

However, since the flash memory control apparatus 100 according to the present invention reduces the size of the data area and increases the size of the ECC storage area, the read / write request of the host is allocated in units equal to the page size of the flash memory 300 The performance degradation may be expected to occur. However, the size of the flash memory 300 included in the SSD product, which is currently widely used, is expanded to 16 KB or more, and furthermore, 8 or 16 pages are clustered and used as one clustering page. In practice, the page clustering technique is indispensable in order to easily manage the SSD equipped with dozens of NAND flash memories or to reduce the size of the map table of the FTL.

FIG. 7 is a diagram illustrating an example of a clustering page used in an SSD using a multi-chip. In the four flash memory chips, pages at the same position are clustered and used as one page. Therefore, the effect of increasing the size of the page substantially occurs.

FIG. 8 is a graph showing a relationship between a correctable block error rate (CBER) and a raw bit error rate (RBER) according to the number of error correctable bits. The graph of FIG. 8 shows a CBER in which the RBER of a flash memory product currently being produced has a 24-bit or 40-bit error correction scheme. Here, CBER is a value calculated by the following equation (1).

Where N is the number of bits in the block, E is the number of errors in the block, and p is the bit error rate.

9 is a graph illustrating normalization of the operation delay time according to the conventional error correction code storing technique and the present invention. Referring to FIG. 9, when the page size is small, the delay time increases sharply as the number of sectors used for storing the error correction code increases. However, when the page size increases, some sectors are used for storing the error correction code It can be confirmed that there is no difference in the delay time.

On the other hand, like the hard disk drive, a volatile memory buffer can be used for the performance enhancement of the NAND flash memory based storage device. In this system, the memory controller temporarily stores data to be written in the buffer in response to an I / O access command of the host, or outputs data to be read from the buffer to be output to the host. By using the buffer memory in this way, it is possible to reduce the delay time which occurs during the processing of the I / O access, and to combine instructions for the same block or page.

One of the buffer management algorithms, CFLRU (Clean-first LRU), is an LRU-based buffer management algorithm for a storage system with NAND flash memory. When a buffer is empty, Use pages or blocks.

The CRLRU buffer management scheme may be applied to the flash memory management apparatus 100 according to the present invention. Hereinafter, the CFLRU scheme applied to the present invention will be referred to as an O-CFLRU scheme. Specifically, in the O-CFLRU technique, the allocation or flush of a buffer is performed page by page by grouping the instructions of the sector for the same page regardless of the timing and type. In the O-CFLRU, the received command is classified according to the size of the command, that is, the size of the sector. If the size of the sector is larger than a preset reference value (for example, 32), the command is directly transmitted to the NAND flash memory , Instructions smaller in size than the reference value are stored in the buffer and are merged or 'in-place' updated.

In the case of applying the O-CFLRU scheme as the buffer management algorithm described above to the present invention, as shown in FIG. 9, when the buffer is used for temporary data storage, the delay time decreases as the size of the buffer increases. The width becomes smaller.

10 is a flowchart illustrating a method of controlling a flash memory control method for storing an error correction code according to an exemplary embodiment of the present invention.

10, when the host interface unit 110 of the flash memory control apparatus 100 according to the present invention receives a data write control signal from the host 200 (S1010) A corresponding error correction code is generated (S1020). The error correction code may be generated by an error correction unit (not shown) separately provided in the memory interface unit 120 or the flash memory control device 100. [

The memory interface unit 120 stores the write target data and the corresponding error correcting code in the flash memory 300. As described above, the memory interface unit 120 stores the write target data in some sectors of the page, for example, one or two sectors To the ECC storage area for storing the error correction code (S1030).

Thereafter, when the read control signal for the stored data is received from the host 200 (S1040), the memory interface unit 120 reads the error correction code stored in the same page as the read target data and the read target data corresponding to the read control signal Reads the data from the flash memory 300 (S1050), corrects the error of the data to be read using the error correction code, and outputs the error to the host 200 (S1060). The error correction process may also be performed by an error correction unit (not shown) separately provided in the flash memory control device 100.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored. Examples of the computer-readable recording medium include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like, and may be implemented in the form of a carrier wave (for example, transmission via the Internet) . The computer-readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation in the embodiment in which said invention is directed. It will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the scope of the appended claims.

100 - Flash memory control device
110 - Host interface unit
120 - memory interface unit
200 - host
300 - Flash memory

Claims (8)

A flash memory control apparatus for controlling a flash memory in which data is stored in units of pages and the page has a preset number of sectors,
A host interface unit for transmitting and receiving control signals and data to / from the host; And
And a write control unit for storing the write target data received together with the write control signal from the host and an error correction code generated corresponding to the write target data in a page of the flash memory, And a memory interface unit for allocating, as a storage area of the error correction code, an area corresponding to a predetermined number of sectors of the sector,
The memory interface unit divides the sector corresponding to the predetermined number of sectors into the remaining sectors excluding the predetermined number of sectors among the plurality of sectors constituting the page and allocates the divided sector as a storage area for an additional error correction code Wherein the flash memory is a flash memory. The method according to claim 1,
Wherein the memory interface unit reads the read target data corresponding to the read control signal received from the host and the error correction code stored in the same page as the read target data from the flash memory. 3. The method according to claim 1 or 2,
Wherein the memory interface sequentially stores an error correction code corresponding to data stored in each sector in a page in an additional allocated sector as a storage area of the error correction code in the same page where the data is stored, . 3. The method according to claim 1 or 2,
Wherein the page is a clustering page in which pages in different flash memories are clustered and processed in a single operation in a storage device having a plurality of flash memories. A flash memory control method for controlling a flash memory in which data is stored in units of pages and the page is composed of a predetermined number of sectors,
(a) receiving data to be written together with a write control signal from a host;
(b) generating an error correction code corresponding to the data to be written; And
(c) storing the write target data and the error correction code in a page of the flash memory, wherein an area corresponding to a predetermined number of sectors among a plurality of sectors corresponding to a data area in which the write target data is stored, Further comprising the step of:
In the step (c), an area corresponding to the predetermined number of sectors is divided into the remaining sectors excluding the predetermined number of sectors among the plurality of sectors constituting the page, To the flash memory. 6. The method of claim 5,
(d) reading the read target data corresponding to the read control signal received from the host and the error correction code stored in the same page as the read target data from the flash memory; And
(e) correcting an error of the data to be read by the error correction code read from the flash memory and outputting the corrected data to the host. The method according to claim 5 or 6,
Wherein in the step (c), an error correction code corresponding to data stored in each sector in the page is successively stored in a sector allocated additionally as a storage area of the error correction code in the same page where the data is stored Memory control method. The method according to claim 5 or 6,
Wherein the page is a clustering page in which pages in different flash memories are clustered and processed in a single operation in a storage device having a plurality of flash memories.

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