CN109872764B - ECC multi-code rate coding and decoding system and method for multi-level storage unit flash memory - Google Patents
ECC multi-code rate coding and decoding system and method for multi-level storage unit flash memory Download PDFInfo
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- CN109872764B CN109872764B CN201910047413.8A CN201910047413A CN109872764B CN 109872764 B CN109872764 B CN 109872764B CN 201910047413 A CN201910047413 A CN 201910047413A CN 109872764 B CN109872764 B CN 109872764B
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Abstract
The invention discloses an ECC multi-code rate coding and decoding system and method of a multi-level storage unit flash memory, which mainly adopt multi-code rate ECC to decode different pages on one physical cell in the multi-level storage unit flash memory so as to achieve the aims of reducing iteration times and prolonging the service life of a flash memory device. Aiming at an ECC part in a main control chip of a multi-level storage unit flash memory, the invention adopts a multi-rate coding and decoding scheme different from the traditional error correcting code, for a lower page with a smaller RBER, an LDPC code/BCH code with a high rate is adopted, for a middle page and an upper page with a larger RBER, an LDPC code/BCH code with a lower rate is adopted, and partial fixed check cells are distributed to the page with the larger RBER from the page with the smaller RBER, so that the decoding rate of the latter is reduced, the decoding performance is improved, the decoding is correctly realized, the iteration times are reduced, the decoding passing rate is increased, and the service life of a flash memory device is prolonged.
Description
Technical Field
The invention belongs to data storage, and particularly relates to an ECC multi-code rate coding and decoding system and method of a multi-level storage unit flash memory.
Background
With the rapid development of the internet big data age, the data volume is larger and larger no matter whether the shooting, the movie, the television play or the game is carried out. In such a large environment, the capacity for the hard disk capacity would be an unprecedented huge challenge. Even though the conventional mechanical hard disk can solve the capacity problem, the conventional mechanical hard disk is slow in speed, large in size and inconvenient to carry, so that the conventional mechanical hard disk is not an optimal choice.
Flash memory has penetrated into every corner of daily life as a storage device which is more stable and faster and more convenient to read and write data than the traditional mechanical hard disk storage mode. In order to meet the increasing memory demand, flash memory manufacturers are continuously reducing the process size and proposing three-dimensional NAND memory technology, increasing the number of information bits in a single flash memory cell, including MLC, TLC, QLC. With the increasing error probability of flash memory, the conventional BCH error correction code is not enough to ensure the data security.
The low density parity check code LDPC is gradually replacing BCH as an error correction mode with error correction capability approaching the shannon limit, and becomes an error correction coding mode in a new generation of flash memory controller.
Each page of the Flash memory corresponds to a region called spare area/redundant area (redundant area), which is originally based on the hardware characteristics of Nand Flash: data is relatively easy to be wrong during reading and writing, so that a corresponding detection and error correction mechanism is required to ensure the correctness of the data, and redundant storage space is designed for placing check bits of the data.
The number of information bits existing in a single flash memory unit of multi-level storage is 2 or more, the information bits are mapped to pages corresponding to the multi-level storage, RBERs (Raw Bit Error rates) of the multiple pages are different, if an Error correction code with the same code Rate is adopted, the iteration times in the decoding process of codes corresponding to the pages with higher RBERs are too many, the speed is reduced, even the codes cannot be correctly decoded, and therefore the service life of the flash memory is reduced, and the stability is reduced.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, and a first aim of the invention is to provide an ECC multi-code rate coding and decoding system of a multi-level storage unit flash memory.
The technical scheme is as follows: an ECC multi-code rate decoding system of a multi-level storage unit flash memory comprises a check unit dynamic allocation module, a multi-code rate error correction code encoding module and a multi-code rate error correction code decoding module, wherein different numbers of check units are allocated according to original error rates of different pages through the check unit dynamic allocation module according to user information, and the ECC multi-code rate decoding system comprises the steps of allocating fixed check units of pages with low error rates to pages with high error rates so as to perform multi-code rate encoding; when the multi-code-rate error correction code decoding module decodes, the multi-code-rate error correction code is decoded according to different code rates used by the multi-code-rate error correction code encoding module.
Furthermore, the multi-code-rate error correction code encoding module selects a code rate from high to low according to the allocation condition of the check cell of each page of the flash memory processed by the check unit dynamic allocation module, and encodes the information bit of each page corresponding to each code rate.
Further, the multi-code-rate error correction code decoding module performs decoding by using a decoding method of an error correction code corresponding to a code rate corresponding to each page according to the allocation condition of the check cell of each page of the flash memory processed by the check unit dynamic allocation module.
An ECC multi-rate decoding method of a multi-level memory cell flash memory, based on ECC decoding, comprises the following steps:
(1) the verification unit dynamic allocation module allocates the fixed verification units of the lower-layer page to the upper-layer page, so that the verification units of the upper-layer page are added;
(2) selecting a code rate from high to low to encode the information bits of each page;
(3) reading data and integrating the check value of each layer into a code word with multiple code rates;
(4) and performing ECC decoding by using the check matrix corresponding to the code rate.
Furthermore, in the step (1), the dynamic allocation module for checking units allocates the fixed checking units of the lowerpage to the midle page and the upperpage, increases the checking bits of the midle page and the uppage, and reduces the code rate, so as to reduce the code rate of decoding the upper page, improve the decoding performance, enable the decoding to be correct, reduce the iteration times and increase the decoding passing rate.
And (3) in the step (2), according to the distribution relation of the verification cells in each page of the flash memory unit, corresponding to each code rate, and respectively coding the information bits of each page from high to low by selecting the code rate.
Reading the data and check value of each page in the step (3), and integrating the data and check value into a code word with multiple code rates according to different code rates; the process of integrating the upper page and the middle page also needs to integrate the check bits of the lower page.
The error correction coding used by the decoding module in step (4) includes LDPC and BCH codes.
Has the advantages that: compared with the prior art, the invention has the remarkable advantages that the first error correction decoding part uses an LDPC/BCH decoding module with one code rate compared with the traditional error correction decoding part, and multi-code rate decoding is added, so that the decoding performance under different pages is obviously improved; secondly, the invention uses lower code rate aiming at the page under low signal-to-noise ratio, so that the iteration times are reduced, and the service life of the flash memory is effectively prolonged; thirdly, the decoding module of the invention supports decoding of various error correcting codes, and has better applicability.
Drawings
FIG. 1 is a decoding flow diagram according to the present invention;
FIG. 2 is a diagram of a calibration unit distribution according to the present invention;
FIG. 3 is a diagram illustrating the check unit dynamic allocation module allocating a fixed check unit of a page with a larger RBER to a page with a smaller RBER;
FIG. 4 is a decoding performance effect diagram of a multi-rate LDPC code used in the present invention;
FIG. 5 is a diagram illustrating the change of the P/E times of the extended flash memory after the multi-rate decoding is performed.
Detailed Description
In order to explain the technical scheme disclosed by the invention in detail, the following is further explained by combining a specific embodiment and a drawing of the specification.
The invention adopts a multi-code-rate decoding scheme different from the traditional error correcting code for an ECC (data error correction) part in a main control chip of a flash memory, adopts an LDPC/BCH code with a higher code rate for a lower layer page with a smaller RBER, reduces the code rate for an upper layer page with a larger RBER by taking the check bits of part of the lower layer page, and adopts the LDPC/BCH code with a lower code rate for coding and decoding.
Take decoding using multi-rate LDPC codes in the TLC flash error correction portion as an example:
each page of the TLC Flash memory corresponds to a region called spare area/redundant area (redundant area), which is originally based on the hardware characteristics of NAND Flash: data is relatively easy to be wrong during reading and writing, so that a corresponding detection and error correction mechanism is required to ensure the correctness of the data, and an redundant area is designed for placing check bits of the data.
The information Bit number in a single flash memory unit of TLC is 3Bit, and the information Bit number is mapped to three different pages, RBER (Raw Bit Error Rate) of the three pages is different, and the LDPC/BCH code with the same code Rate causes that the iteration times of the upper page are too many, the speed is reduced, and the upper page cannot be decoded correctly. Thereby reducing the lifetime and stability of the flash memory.
The life of TLC flash memory is related to the rise of RBER caused by the increase of the number of times of erasing and the RBER threshold value of correct error correction algorithm, as shown in fig. 1, three pages of TCL: the RBER magnitude of upper page, middle page and lower page is 1 × 10 when the P/E times reach about 2000 times-2、1×10-3、1×10-4Left and right. The RBER of the decoding device rises along with the increase of the P/E (erasing) times, at the moment, the acceptable RBER (T-RBER) of the common decoding is reached, the normal decoding of the upperpage can not be met, and the service life of the decoding device almost reaches the end.
Then, the multi-rate decoding in the present invention is used to solve this problem, and the decoding steps are shown in fig. 2:
(1) the check unit dynamic allocation module allocates the fixed check unit of the page with the larger RBER to the page with the smaller RBER, thereby increasing the check bits of the latter, reducing the code rate thereof and obtaining higher decoding throughput rate. As shown in fig. 3.
(2) And respectively coding the information bits of each page from high to low according to the distribution relation of check cells in each page of the flash memory unit and corresponding to each code rate.
(3) Reading data and check values of each page, and integrating the data and check values into a code word with multiple code rates according to different code rates; the process of integrating the upper page and the middle page also needs to integrate the check bits of the lower page.
(4) And performing LDPC decoding by using the check matrix corresponding to the code rate.
Wherein, the decoding performance of the multi-rate LDPC code used by the invention is shown in FIG. 4, and the RBER rises to 1 x 10 after P/E times for an upper page-2After the code rate is reduced to 0.887, the T-RBER of the decoding performance is 1 multiplied by 10-2Above, it can support the RBER to reach 1 × 10-2And above, the correct decoding can still be ensured, thereby prolonging the service life of the flash memory.
After multi-rate decoding, the P/E times of the flash memory are extended to about 2500 times, as shown in FIG. 5.
Aiming at an ECC (data error correction) part in a main control chip of the flash memory, the invention adopts a multi-code-rate decoding scheme different from the traditional error correction code, for a lower page with a smaller RBER, an LDPC/BCH code with a higher code rate is adopted, for an upper page with a larger RBER, the code rate is reduced by taking part of check bits of the lower page, and the LDPC/BCH code with a lower code rate is adopted, so that the decoding performance is improved, the decoding is correctly realized, the iteration times are reduced, the decoding passing rate is increased, and the service life of a flash memory device is prolonged. Has great theoretical significance and application value.
Claims (8)
1. An ECC multi-code rate coding and decoding system of a multi-level memory cell flash memory is characterized in that: the method comprises a check unit dynamic allocation module, a multi-code-rate error correction code encoding module and a multi-code-rate error correction code decoding module, wherein different numbers of check units are allocated through the check unit dynamic allocation module according to original error rates of different pages according to user information, and a fixed check unit of a page with a low error rate is allocated to a page with a high error rate so as to carry out multi-code-rate encoding; when the multi-code-rate error correction code decoding module decodes, the multi-code-rate error correction code is decoded according to different code rates used by the multi-code-rate error correction code encoding module.
2. The ECC multi-rate coding and decoding system of the multi-level cell flash memory according to claim 1, wherein: and the multi-code-rate error correction code encoding module is used for respectively encoding the code rate of the information bit of each page from high to low according to the distribution condition of the check cell of each page of the flash memory processed by the check unit dynamic distribution module and corresponding to each code rate.
3. The ECC multi-rate coding and decoding system of the multi-level cell flash memory according to claim 1, wherein: and the multi-code-rate error correcting code decoding module is used for decoding corresponding to each page according to the distribution condition of the check cell of each page of the flash memory processed by the check unit dynamic distribution module by using a decoding method of the error correcting code corresponding to the code rate.
4. An ECC multi-code rate coding and decoding method of a multi-level memory cell flash memory is characterized in that: the method is based on ECC decoding and comprises the following steps:
(1) the verification unit dynamic allocation module allocates the fixed verification units of the lower-layer page to the upper-layer page, so that the verification units of the upper-layer page are added;
(2) selecting a code rate from high to low to encode the information bits of each page;
(3) reading data and integrating the check value of each layer into a code word with multiple code rates;
(4) and performing ECC decoding by using the check matrix corresponding to the code rate.
5. The ECC multi-rate coding and decoding method of the multi-level cell flash memory according to claim 4, wherein: in the step (1), the check unit dynamic allocation module allocates the fixed check unit of the lowerpage to the midlet page and the upperpage, increases the check bits of the midlet page and the upperpage, and reduces the code rate of the midlet page and the upperpage, so that the code rate of the decoding of the upper layer of the page is reduced, the decoding performance is improved, the decoding is correct, the iteration times are reduced, and the decoding passing rate is increased.
6. The ECC multi-rate coding and decoding method of the multi-level cell flash memory according to claim 4, wherein: and (3) in the step (2), according to the distribution relation of the verification cells in each page of the flash memory unit, corresponding to each code rate, and respectively coding the information bits of each page from high to low by selecting the code rate.
7. The ECC multi-rate coding and decoding method of the multi-level cell flash memory according to claim 4, wherein: reading the data and check value of each page in the step (3), and integrating the data and check value into a code word with multiple code rates according to different code rates; the process of integrating the upper page and the middle page also needs to integrate the check bits of the lower page.
8. The ECC multi-rate coding and decoding method of the multi-level cell flash memory according to claim 4, wherein: the error correction coding used by the decoding module in step (4) includes LDPC and BCH codes.
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