KR101161795B1 - Method for fabricating the same of semiconductor with recess gate - Google Patents

Method for fabricating the same of semiconductor with recess gate Download PDF

Info

Publication number
KR101161795B1
KR101161795B1 KR1020060012977A KR20060012977A KR101161795B1 KR 101161795 B1 KR101161795 B1 KR 101161795B1 KR 1020060012977 A KR1020060012977 A KR 1020060012977A KR 20060012977 A KR20060012977 A KR 20060012977A KR 101161795 B1 KR101161795 B1 KR 101161795B1
Authority
KR
South Korea
Prior art keywords
gate
recess
pattern
sacrificial layer
forming
Prior art date
Application number
KR1020060012977A
Other languages
Korean (ko)
Other versions
KR20070081213A (en
Inventor
김형수
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020060012977A priority Critical patent/KR101161795B1/en
Publication of KR20070081213A publication Critical patent/KR20070081213A/en
Application granted granted Critical
Publication of KR101161795B1 publication Critical patent/KR101161795B1/en

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28211—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 리세스패턴과 게이트패턴간의 오정렬문제를 해결하기 위한 리세스 게이트를 갖는 반도체 소자의 제조방법을 제공하기 위한 것으로, 본 발명은 반도체 기판 상에 게이트 예정지역을 오픈시키는 희생막패턴을 형성하는 단계, 상기 희생막패턴을 하드마스크로 하여 상기 반도체 기판을 식각하여 리세스를 형성하는 단계, 상기 리세스 표면에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 상기 희생막패턴과 리세스의 측벽에 스페이서를 형성하는 단계, 상기 희생막패턴 상에 상기 리세스를 매립하는 게이트전극물질을 형성하는 단계, 상기 희생막패턴의 표면이 드러날때까지 상기 게이트전극물질을 평탄화하는 단계, 상기 희생막패턴과 스페이서를 선택적으로 제거하는 단계, 상기 희생막패턴과 스페이서 제거 후에 발생되는 상기 게이트전극물질과 리세스측벽 사이를 채우는 게이트절연막을 추가로 성장시키는 단계를 포함하고, 상기한 본 발명은 리세스 패턴과 게이트패턴간의 오정렬(misalign)문제를 해결하여 소자 특성을 향상시키고, 공정 단순화 및 턴어라운드타임(Turn Around Time) 단축이 가능한 효과가 있다.The present invention is to provide a method for manufacturing a semiconductor device having a recess gate for solving the misalignment problem between the recess pattern and the gate pattern, the present invention is to form a sacrificial layer pattern for opening a gate predetermined region on the semiconductor substrate Forming a recess by etching the semiconductor substrate using the sacrificial layer pattern as a hard mask, forming a gate insulating layer on a surface of the recess, and forming a recess on the gate insulating layer. Forming a spacer on the sidewalls, forming a gate electrode material filling the recess on the sacrificial layer pattern, planarizing the gate electrode material until the surface of the sacrificial layer pattern is exposed, and Selectively removing the pattern and the spacer; And further growing a gate insulating film that fills between the bit electrode material and the recess side wall, wherein the present invention solves a misalignment problem between the recess pattern and the gate pattern to improve device characteristics and simplify the process. And it is possible to reduce the turn around time (Turn Around Time).

게이트전극, 오정렬, 질화막, 산화공정 Gate electrode, misalignment, nitride film, oxidation process

Description

리세스 게이트를 갖는 반도체 소자의 제조방법{METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR WITH RECESS GATE}Method for manufacturing a semiconductor device having a recess gate {METHOD FOR FABRICATING THE SAME OF SEMICONDUCTOR WITH RECESS GATE}

도 1은 종래 기술에 따른 리세스 게이트를 갖는 반도체 소자를 설명하기 위한 TEM사진,1 is a TEM photograph for explaining a semiconductor device having a recess gate according to the prior art;

도 2a 내지 도 2h는 본 발명의 바람직한 실시예에 따른 리세스 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate in accordance with a preferred embodiment of the present invention.

본 발명은 반도체 소자의 제조방법에 관한 것으로, 특히 리세스게이트를 갖는 반도체 소자의 제조방법에 관한 것이다.The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device having a recess gate.

반도체 소자가 초고집적화 됨에 따라 게이트를 평탄한 활성영역 위에 형성하는 기존의 플라나 게이트(Planar Gate)배선 형성 방법은 게이트 채널길이(Gate channel Length)가 점점 작아지고 이온주입도핑(Implant Dopping)농도가 증가하에 따라 전계(Electric Filed) 증가에 의해 접합 누설전류(Junction Leakage)가 생겨 소자의 리프레시특성을 확보하기가 어렵다.As the semiconductor device becomes very integrated, the conventional planar gate wiring forming method for forming a gate over a flat active region becomes smaller with a gate channel length and an implant doping concentration increased. As a result, an increase in electric filed causes junction leakage, which makes it difficult to secure refresh characteristics of the device.

이를 개선하기 위해 게이트 배선 형성방법으로 활성영역 기판을 리세스패턴으로 식각 후 게이트를 형성하는 리세스 게이트 공정이 실시되고 있다. 상기 리세스 게이트 공정을 적용하면 채널길이 증가 및 이온주입 도핑 농도의 감소가 가능하여 소자의 리프레시 특성이 개선된다.In order to improve this, a recess gate process is performed in which a gate is formed after the active region substrate is etched into the recess pattern using a gate wiring method. Applying the recess gate process can increase the channel length and decrease the ion implantation doping concentration, thereby improving the refresh characteristics of the device.

상기 리세스 게이트 공정은 후속 공정인 게이트패턴과의 정렬도 확보가 매우 중요한 특성이다. 현재 리세스 게이트 공정은 활성(active)영역에 미세한 스페이스(space)를 갖는 리세스 게이트패턴을 형성하고, 게이트물질을 증착한 다음 감광제를 이용한 패터닝공정을 실시하는 단계로 실시된다.The recess gate process is very important in ensuring alignment with the gate pattern, which is a subsequent process. Currently, the recess gate process is performed by forming a recess gate pattern having a fine space in an active region, depositing a gate material, and then performing a patterning process using a photoresist.

도 1은 종래 기술에 따른 리세스 게이트를 갖는 반도체 소자를 설명하기 위한 TEM사진이다.1 is a TEM photograph for explaining a semiconductor device having a recess gate according to the prior art.

도 1을 참조하면, 리세스패턴(10)과 게이트패턴(20)간의 정렬도가 심하게 틀어져 오정렬(100) 된 것을 알 수 있다. Referring to FIG. 1, it can be seen that the alignment between the recess pattern 10 and the gate pattern 20 is severely misaligned and misaligned 100.

상기 정렬도는 노광장비 자체의 문제, 공정 문제로 15nm이상 벗어나게 되는데, 소자의 집적도가 증가되면서 정밀도는 종래보다 더 높은 정렬특성을 요구하고 있다.The degree of alignment is more than 15nm due to the problem of the exposure equipment itself, the process problem, the accuracy of the device as the degree of integration is higher than the conventional requires a higher alignment characteristics.

본 발명은 상기한 종래 기술의 문제점을 해결하기 위해 제안된 것으로, 리세스패턴과 게이트패턴간의 오정렬문제를 해결하기 위한 리세스 게이트를 갖는 반도 체 소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been proposed to solve the above problems of the prior art, and an object thereof is to provide a method of manufacturing a semiconductor device having a recess gate for solving the misalignment problem between the recess pattern and the gate pattern.

상기 목적을 달성하기 위한 본 발명은 반도체 기판 상에 게이트 예정지역을 오픈시키는 희생막패턴을 형성하는 단계, 상기 희생막패턴을 하드마스크로 하여 상기 반도체 기판을 식각하여 리세스를 형성하는 단계, 상기 리세스 표면에 게이트절연막을 형성하는 단계, 상기 게이트절연막 상에 상기 희생막패턴과 리세스의 측벽에 스페이서를 형성하는 단계, 상기 희생막패턴 상에 상기 리세스를 매립하는 게이트전극물질을 형성하는 단계, 상기 희생막패턴의 표면이 드러날때까지 상기 게이트전극물질을 평탄화하는 단계, 상기 희생막패턴과 스페이서를 선택적으로 제거하는 단계, 상기 희생막패턴과 스페이서 제거 후에 발생되는 상기 게이트전극물질과 리세스측벽 사이를 채우는 게이트절연막을 추가로 성장시키는 단계를 포함한다.According to an aspect of the present invention, a sacrificial layer pattern for opening a gate predetermined region on a semiconductor substrate is formed, and the recess is formed by etching the semiconductor substrate using the sacrificial layer pattern as a hard mask. Forming a gate insulating film on a recess surface, forming a spacer on the sidewalls of the sacrificial film pattern and the recess on the gate insulating film, and forming a gate electrode material filling the recess on the sacrificial film pattern In the step of planarizing the gate electrode material until the surface of the sacrificial layer pattern is exposed, selectively removing the sacrificial layer pattern and the spacer, and removing the gate electrode material and the spacer formed after removing the sacrificial layer pattern and the spacer. And growing a gate insulating film that fills between the recess side walls.

이하, 본 발명이 속하는 기술 분야에서 통상의 지식을 가진 자가 본 발명의 기술적 사상을 용이하게 실시할 수 있을 정도로 상세히 설명하기 위하여, 본 발명의 가장 바람직한 실시예를 첨부된 도면을 참조하여 설명하기로 한다.DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings, in order to facilitate a person skilled in the art to easily carry out the technical idea of the present invention. do.

도 2a 내지 도 2h는 본 발명의 바람직한 실시예에 따른 리세스 게이트를 갖는 반도체 소자의 제조방법을 설명하기 위한 공정 단면도이다.2A to 2H are cross-sectional views illustrating a method of manufacturing a semiconductor device having a recess gate according to an exemplary embodiment of the present invention.

도 2a에 도시된 바와 같이, 반도체 기판(31)에 소자분리막(32)을 형성한다. 여기서, 소자분리막(32)은 활성영역을 정의하기 위한 것으로, 적어도 3000Å의 두께로 형성한다.As shown in FIG. 2A, an isolation layer 32 is formed on the semiconductor substrate 31. In this case, the device isolation layer 32 is for defining an active region and is formed to have a thickness of at least 3000 GPa.

이어서, 활성영역이 정의된 반도체 기판(31) 상에 희생막(33)을 형성한다. 여기서, 희생막(33)은 질화막으로 형성한다.Subsequently, a sacrificial layer 33 is formed on the semiconductor substrate 31 in which the active region is defined. Here, the sacrificial film 33 is formed of a nitride film.

이어서, 희생막(33) 상에 감광막을 형성하고, 노광 및 현상으로 게이트 예정지역을 오픈시키는 감광막패턴(34)을 형성한다.Subsequently, a photoresist film is formed on the sacrificial film 33, and a photoresist pattern 34 is formed to open the gate predetermined region by exposure and development.

도 2b에 도시된 바와 같이, 감광막패턴(34)을 식각마스크로 희생막(33)을 식각하여 희생막패턴(33)을 형성한다.As shown in FIG. 2B, the sacrificial layer 33 is etched using the photoresist layer 34 as an etch mask to form the sacrificial layer pattern 33.

이하, 게이트 예정지역을 오픈시키는 희생막패턴(33)을 '희생막패턴(33a)'이라고 한다.Hereinafter, the sacrificial film pattern 33 for opening the gate scheduled area is referred to as the 'sacrificial film pattern 33a'.

이어서, 희생막패턴(33a)을 하드마스크로 반도체 기판(31)을 소정깊이 식각하여 리세스(35)를 형성한다.Subsequently, the recess 35 is formed by etching the semiconductor substrate 31 by a predetermined depth using the sacrificial layer pattern 33a as a hard mask.

도 2c에 도시된 바와 같이, 리세스(35)의 표면에 게이트절연막(36)을 형성한다. 여기서, 게이트절연막(36)은 게이트와 반도체 기판(31) 사이의 절연을 위한 것으로, 산화막으로 형성한다.As shown in FIG. 2C, a gate insulating film 36 is formed on the surface of the recess 35. Here, the gate insulating film 36 is for insulating between the gate and the semiconductor substrate 31 and is formed of an oxide film.

이어서, 게이트절연막(36) 상에 희생막패턴(33a)과 리세스(35)의 측벽에 스페이서(37)를 형성한다. 여기서, 스페이서(37)는 상기 희생막패턴(33)과 같은 물질로 형성하되, 질화막으로 형성한다.Subsequently, spacers 37 are formed on sidewalls of the sacrificial layer pattern 33a and the recess 35 on the gate insulating layer 36. Here, the spacer 37 is formed of the same material as the sacrificial film pattern 33, but is formed of a nitride film.

도 2d에 도시된 바와 같이, 희생막패턴(33a) 상에 리세스(35)를 매립하는 폴리실리콘(38)을 형성한다.As shown in FIG. 2D, the polysilicon 38 filling the recess 35 is formed on the sacrificial layer pattern 33a.

도 2e에 도시된 바와 같이, 희생막패턴(33a) 표면이 드러날때까지 폴리실리콘(38)을 평탄화한다.As shown in FIG. 2E, the polysilicon 38 is planarized until the surface of the sacrificial film pattern 33a is exposed.

이하, 평탄화된 폴리실리콘(38)을 '폴리실리콘전극(38a)'이라고 한다.Hereinafter, the planarized polysilicon 38 is referred to as a 'polysilicon electrode 38a'.

도 2f에 도시된 바와 같이, 희생막패턴(33a)과 스페이서(37)를 제거한다. 여기서, 희생막패턴(33a)과 스페이서(37)는 습식식각으로 제거하되, 인산(H3PO4)으로 실시할 수 있다.As shown in FIG. 2F, the sacrificial layer pattern 33a and the spacer 37 are removed. Here, the sacrificial film pattern 33a and the spacer 37 may be removed by wet etching, but may be performed by phosphoric acid (H 3 PO 4 ).

상기와 같이, 희생막패턴(33a)과 스페이서(37)를 제거하면 폴리실리콘전극(38a)과 리세스(35) 측벽사이에 공간이 생기게된다. As described above, when the sacrificial layer pattern 33a and the spacer 37 are removed, a space is formed between the polysilicon electrode 38a and the sidewall of the recess 35.

도 2g에 도시된 바와 같이, 희생막패턴(33a)과 스페이서(37) 제거 후에 발생되는 상기 폴리실리콘전극(38a)과 리세스(35)측벽 사이를 채우는 게이트절연막(36)의 추가 성장을 실시한다.As shown in FIG. 2G, further growth of the gate insulating film 36 filling the sidewalls of the recess 35 and the polysilicon electrode 38a generated after removing the sacrificial film pattern 33a and the spacer 37 is performed. do.

여기서, 게이트절연막(36)의 추가 성장은 산화공정을 실시하되, 폴리실리콘전극(38a)과 리세스(35)의 측벽 사이가 채워질때까지 실시한다.Here, the further growth of the gate insulating film 36 is performed by an oxidation process until the gap between the polysilicon electrode 38a and the sidewall of the recess 35 is filled.

이하, 추가 성장된 게이트절연막(36)을 '게이트절연막(36a)'이라고 한다.Hereinafter, the additionally grown gate insulating film 36 is referred to as a 'gate insulating film 36a'.

따라서, 폴리실리콘전극(38a)이 리세스(35)에 매립되는 부분과 반도체 기판(31) 상에 돌출되는 부분을 동시에 형성함으로써 공정 단순화 및 턴어라운드타임(Turn Around Time;TAT) 단축을 가져올 뿐 아니라, 리세스 패턴과 게이트패턴간의 오정렬(misalign)문제를 해결할 수 있다.Therefore, the polysilicon electrode 38a simultaneously forms a portion buried in the recess 35 and a portion protruding on the semiconductor substrate 31, thereby simplifying the process and shortening the turn around time (TAT). Therefore, the misalignment between the recess pattern and the gate pattern can be solved.

도 2h에 도시된 바와 같이, 폴리실리콘전극(38a) 상에 저저항금속전극(39)과 게이트하드마스크(40)를 순차로 적층하여 게이트패턴을 형성한다. 여기서, 저저항금속전극(39)은 하부 폴리실리콘전극(38a)과 함께 게이트전극으로 사용하기 위한 것이다.As shown in FIG. 2H, the low resistance metal electrode 39 and the gate hard mask 40 are sequentially stacked on the polysilicon electrode 38a to form a gate pattern. Here, the low resistance metal electrode 39 is used as the gate electrode together with the lower polysilicon electrode 38a.

게이트패턴을 형성하기 위해, 폴리실리콘전극(38a)을 포함한 반도체 기판(31) 상에 저저항금속전극(39)과 게이트하드마스크(40)를 순차로 적층한다. 이어서, 도시되지는 않았지만 게이트하드마스크(40) 상에 감광막을 형성하고 노광 및 현상으로 게이트 예정지역을 정의하는 감광막패턴을 형성한다. 이어서, 감광막패턴을 식각마스크로 하여 게이트하드마스크(40)와 저저항금속물질(39)을 식각하여 게이트패턴을 형성한다.In order to form the gate pattern, the low resistance metal electrode 39 and the gate hard mask 40 are sequentially stacked on the semiconductor substrate 31 including the polysilicon electrode 38a. Subsequently, although not shown, a photoresist film is formed on the gate hard mask 40, and a photoresist pattern defining a gate predetermined area is formed by exposure and development. Subsequently, the gate hard mask 40 and the low resistance metal material 39 are etched using the photoresist pattern as an etch mask to form a gate pattern.

이때, 하부 폴리실리콘전극(38a)의 측벽과 저저항금속전극(39) 및 게이트하드마스크(40)의 측벽이 서로 정렬되도록 식각한다.At this time, the sidewalls of the lower polysilicon electrode 38a and the sidewalls of the low resistance metal electrode 39 and the gate hard mask 40 are etched to be aligned with each other.

상기한 본 발명은, 리세스 패턴과 게이트패턴에 형성되는 폴리실리콘전극을 동시에 형성하여 서로간의 오정렬문제를 해결하면서, 공정 단순화 및 턴어라운드타임을 단축시키는 장점이 있다.The present invention has the advantage of reducing the process simplification and turnaround time while solving the misalignment problem by forming the polysilicon electrodes formed on the recess pattern and the gate pattern at the same time.

본 발명의 기술 사상은 상기 바람직한 실시예에 따라 구체적으로 기술되었으나, 상기한 실시예는 그 설명을 위한 것이며 그 제한을 위한 것이 아님을 주의하여야 한다. 또한, 본 발명의 기술 분야의 통상의 전문가라면 본 발명의 기술 사상의 범위 내에서 다양한 실시예가 가능함을 이해할 수 있을 것이다.While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. In addition, those skilled in the art will understand that various embodiments are possible within the scope of the technical idea of the present invention.

상술한 본 발명에 의한 리세스 게이트를 갖는 반도체 소자의 제조방법은 리세스 패턴과 게이트패턴간의 오정렬(misalign)문제를 해결하여 소자 특성을 향상시 키고, 공정 단순화 및 턴어라운드타임(Turn Around Time) 단축이 가능한 효과가 있다. The above-described method of manufacturing a semiconductor device having a recess gate according to the present invention improves device characteristics by solving a misalignment problem between the recess pattern and the gate pattern, and simplifies the process and shortens the turn around time. This has a possible effect.

Claims (9)

반도체 기판 상에 게이트 예정지역을 오픈시키는 희생막패턴을 형성하는 단계;Forming a sacrificial layer pattern on the semiconductor substrate to open the gate predetermined region; 상기 희생막패턴을 하드마스크로 하여 상기 반도체 기판을 식각하여 리세스를 형성하는 단계;Etching the semiconductor substrate using the sacrificial layer pattern as a hard mask to form a recess; 상기 리세스 표면에 게이트절연막을 형성하는 단계;Forming a gate insulating film on the recess surface; 상기 게이트절연막 상에 상기 희생막패턴과 리세스의 측벽에 스페이서를 형성하는 단계;Forming spacers on sidewalls of the sacrificial layer pattern and the recess on the gate insulating layer; 상기 희생막패턴 상에 상기 리세스를 매립하는 게이트전극물질을 형성하는 단계;Forming a gate electrode material filling the recess on the sacrificial layer pattern; 상기 희생막패턴의 표면이 드러날때까지 상기 게이트전극물질을 평탄화하는 단계;Planarizing the gate electrode material until the surface of the sacrificial layer pattern is exposed; 상기 희생막패턴과 스페이서를 선택적으로 제거하는 단계; 및Selectively removing the sacrificial layer pattern and the spacer; And 상기 희생막패턴과 스페이서 제거 후에 발생되는 상기 게이트전극물질과 리세스측벽 사이를 채우는 게이트절연막을 추가로 성장시키는 단계Further growing a gate insulating layer filling between the gate electrode material and a recess side wall generated after removing the sacrificial layer pattern and the spacer. 를 포함하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device having a recess gate, characterized in that it comprises a. 청구항 2은(는) 설정등록료 납부시 포기되었습니다.Claim 2 has been abandoned due to the setting registration fee. 상기 희생막패턴을 형성하는 단계는,Forming the sacrificial layer pattern, 상기 반도체 기판 상에 희생막을 형성하는 단계;Forming a sacrificial layer on the semiconductor substrate; 상기 희생막 상에 감광막을 형성하는 단계;Forming a photoresist film on the sacrificial film; 상기 감광막을 노광 및 현상으로 게이트 예정지역을 오픈시키는 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern for opening a predetermined gate region by exposing and developing the photoresist; And 상기 감광막패턴을 식각마스크로 하여 상기 희생막을 식각하여 희생막패턴을 형성하는 단계Etching the sacrificial layer by using the photoresist pattern as an etching mask to form a sacrificial layer pattern 를 포함하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.A method of manufacturing a semiconductor device having a recess gate, characterized in that it comprises a. 청구항 3은(는) 설정등록료 납부시 포기되었습니다.Claim 3 has been abandoned due to the setting registration fee. 제1항에 있어서,The method of claim 1, 상기 희생막패턴과 스페이서는 같은 물질로 형성하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The method of claim 1, wherein the sacrificial layer pattern and the spacer are formed of the same material. 청구항 4은(는) 설정등록료 납부시 포기되었습니다.Claim 4 was abandoned when the registration fee was paid. 제3항에 있어서,The method of claim 3, 상기 희생막패턴과 스페이서는 질화막으로 형성하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The method of claim 1, wherein the sacrificial layer pattern and the spacer are formed of a nitride layer. 청구항 5은(는) 설정등록료 납부시 포기되었습니다.Claim 5 was abandoned upon payment of a set-up fee. 제1항에 있어서,The method of claim 1, 상기 게이트전극물질은 폴리실리콘으로 형성하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The gate electrode material is a semiconductor device manufacturing method having a recess gate, characterized in that formed of polysilicon. 청구항 6은(는) 설정등록료 납부시 포기되었습니다.Claim 6 was abandoned when the registration fee was paid. 제1항에 있어서,The method of claim 1, 상기 희생막패턴과 스페이서를 제거하는 단계는 습식식각공정으로 실시하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The removing of the sacrificial layer pattern and the spacer is a method of manufacturing a semiconductor device having a recess gate, characterized in that the wet etching process. 청구항 7은(는) 설정등록료 납부시 포기되었습니다.Claim 7 was abandoned upon payment of a set-up fee. 제6항에 있어서,The method of claim 6, 상기 습식식각공정은 인산(H3PO4)로 실시하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The wet etching process is a method of manufacturing a semiconductor device having a recess gate, characterized in that performed with phosphoric acid (H 3 PO 4 ). 청구항 8은(는) 설정등록료 납부시 포기되었습니다.Claim 8 was abandoned when the registration fee was paid. 제1항에 있어서,The method of claim 1, 상기 게이트절연막을 추가로 성장시키는 단계는 산화공정을 실시하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device having a recess gate, wherein the growing of the gate insulating layer further comprises performing an oxidation process. 청구항 9은(는) 설정등록료 납부시 포기되었습니다.Claim 9 has been abandoned due to the setting registration fee. 제1항에 있어서,The method of claim 1, 상기 게이트절연막을 추가로 성장시키는 단계 후,After further growing the gate insulating film, 상기 게이트전극물질을 포함한 상기 반도체 기판 상에 저저항금속물질과 게이트하드마스크를 형성하는 단계;Forming a low resistance metal material and a gate hard mask on the semiconductor substrate including the gate electrode material; 감광막패턴을 형성하는 단계; 및Forming a photoresist pattern; And 상기 감광막패턴을 식각마스크로 하여 상기 저저항금속물질 및 게이트하드마스크를 식각하여 게이트패턴을 형성하는 단계Etching the low resistance metal material and the gate hard mask using the photoresist pattern as an etching mask to form a gate pattern 를 더 포함하는 것을 특징으로 하는 리세스 게이트를 갖는 반도체 소자의 제조방법.The method of manufacturing a semiconductor device having a recess gate further comprising.
KR1020060012977A 2006-02-10 2006-02-10 Method for fabricating the same of semiconductor with recess gate KR101161795B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020060012977A KR101161795B1 (en) 2006-02-10 2006-02-10 Method for fabricating the same of semiconductor with recess gate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060012977A KR101161795B1 (en) 2006-02-10 2006-02-10 Method for fabricating the same of semiconductor with recess gate

Publications (2)

Publication Number Publication Date
KR20070081213A KR20070081213A (en) 2007-08-16
KR101161795B1 true KR101161795B1 (en) 2012-07-03

Family

ID=38611174

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020060012977A KR101161795B1 (en) 2006-02-10 2006-02-10 Method for fabricating the same of semiconductor with recess gate

Country Status (1)

Country Link
KR (1) KR101161795B1 (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228580A (en) 2003-01-22 2004-08-12 Samsung Electronics Co Ltd Semiconductor device and its manufacturing method

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004228580A (en) 2003-01-22 2004-08-12 Samsung Electronics Co Ltd Semiconductor device and its manufacturing method

Also Published As

Publication number Publication date
KR20070081213A (en) 2007-08-16

Similar Documents

Publication Publication Date Title
KR100610465B1 (en) Method for fabricating semiconductor device
US7253060B2 (en) Gate-all-around type of semiconductor device and method of fabricating the same
KR100673133B1 (en) Method for fabricating semiconductor device
KR100720232B1 (en) Method for forming semiconductor device having fin structure
KR100607351B1 (en) Method for fabricating flash memory device
US20070200178A1 (en) Gate-all-around type of semiconductor device and method of fabricating the same
KR100695498B1 (en) Semiconductor device with vertical channel and method for manufacturing the same
KR100615593B1 (en) Method for manufacturing semiconductor device with recess channel
US6380088B1 (en) Method to form a recessed source drain on a trench side wall with a replacement gate technique
KR101051180B1 (en) Method for forming semiconductor device
JP4634877B2 (en) Manufacturing method of semiconductor device
KR101161795B1 (en) Method for fabricating the same of semiconductor with recess gate
JP2005116952A (en) Trench capacitor and method of manufacturing the same
KR101003489B1 (en) Method of manufacturing Buried channel transistor having recess gate
KR100744088B1 (en) Method for fabricating the same of semiconductor with bulb recess gate
KR100629695B1 (en) Method for manufacturing semiconductor device wiht recess gate
KR20020055147A (en) Method for manufacturing semiconductor device
KR100670748B1 (en) Method for fabricating the same of semiconductor device with recess gate
KR101119739B1 (en) Method for Forming Transistor of Semiconductor Device
KR100611083B1 (en) Mos transistor and method for manufacturing the same
KR100689674B1 (en) Method for fabricating of semiconductor device
KR100271661B1 (en) Method for fabricating semiconductor device
KR101194742B1 (en) Method for forming semiconductor device
KR100612559B1 (en) Method of forming a floating gate in a flash memory cell
KR101079287B1 (en) Transistor and method for fabricating the same

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
LAPS Lapse due to unpaid annual fee