KR20020055147A - Method for manufacturing semiconductor device - Google Patents

Abstract

PURPOSE: A method for fabricating a semiconductor device is provided to guarantee a short channel margin and to control generation of hot carriers in forming a transistor of an ultra-fine line width, by forming a recess region on the lower surface of a gate so that the channel length between a source and a drain can be guaranteed. CONSTITUTION: A semiconductor substrate(10) having an isolation layer(11) is prepared. The first photoresist layer pattern for confining a gate structure formation region is formed on the semiconductor substrate. A predetermined portion of the semiconductor substrate is etched to form the recess region by using the first photoresist layer pattern as an etch barrier. After the first photoresist layer pattern is removed, a gate insulation layer(13), a conductive layer(14) for the gate and a hard mask layer(15) are sequentially deposited on the semiconductor substrate including a trench. The second photoresist layer pattern for confining a gate structure formation region is formed on the hard mask layer. The hard mask layer, the conductive layer for the gate and the gate insulation layer are sequentially etched to form the gate(100) by using the second photoresist layer pattern as an etch barrier. A low density impurity ion implantation process is performed regarding the semiconductor substrate at both sides of the gate. A spacer(17) is formed on both sidewalls of the gate. A high density impurity ion implantation process is performed regarding the semiconductor substrate at both sides of the spacer to form a source/drain region(18a,18b).

Description

Manufacturing method of semiconductor device {METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a transistor manufacturing method capable of securing a channel length.

Recently, due to consumer demand and cost reduction, it is inevitable to develop ultra-fine devices. Accordingly, when the transistor is formed by a conventional DRAM transistor manufacturing method, the short channel effect is large due to a short channel margin, and the hot carrier effect characteristic is deteriorated, thereby deteriorating device characteristics. Brings effect.

Accordingly, an object of the present invention for solving the above problems is to provide a transistor manufacturing method of a semiconductor device capable of securing a channel length.

1A to 1D are manufacturing process diagrams for explaining a method for manufacturing a semiconductor device according to the present invention.

10 semiconductor substrate 11 device isolation film

12: first photosensitive film pattern 13: gate insulating film

14 gate conductive film 15 hard mask film

16 second photosensitive film pattern 17 spacer

18a, 18b: source / drain regions

50: recessed area 100: gate

A semiconductor device manufacturing method according to the present invention for achieving the above object comprises the steps of providing a semiconductor substrate having a device isolation film; Forming a first photoresist pattern defining a gate structure formation region on the semiconductor substrate; Etching a predetermined portion of the semiconductor substrate using the first photoresist pattern as an etch barrier to form a recess region; After removing the first photoresist layer pattern, sequentially depositing a gate insulating layer, a gate conductive layer, and a hard mask layer on the entire surface of the semiconductor substrate on which the trench is formed; Forming; Forming a gate by sequentially etching the hard mask layer, the gate conductive layer, and the gate insulating layer using the second photoresist pattern as an etch barrier; Low concentration impurity ion implantation into the semiconductor substrate on both sides of the gate; Forming spacers on both sidewalls of the gate; And forming a source / drain region by performing high concentration impurity ion implantation into the semiconductor substrate on both sides of the space.

BEST MODE Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1A to 1D are views for explaining a method of manufacturing a semiconductor device of the present invention.

First, as shown in FIG. 1A, an isolation layer 11 is formed on the semiconductor substrate 10 to define an element formation region. Although not shown in the drawing, the process of forming the device isolation film 11 is as follows.

A pad oxide film and an anti-oxidation silicon nitride film (not shown) are sequentially deposited on the semiconductor substrate 10. Next, a photoresist pattern is formed on the silicon nitride layer to define an isolation region. Next, a trench is formed by sequentially etching the silicon nitride film, the pad oxide film, and a predetermined silicon substrate using the photoresist pattern as an etch barrier. Subsequently, a gapfill oxide film is embedded on the front structure including the trench, and the gapfill oxide film is polished until the silicon nitride film is exposed. Next, the device isolation layer 11 is formed by removing the silicon nitride layer and the pad oxide layer.

Next, as shown in FIG. 1B, a first photosensitive layer pattern 12 defining a gate structure forming region is formed on the entire surface of the semiconductor substrate 10 on which the device isolation layer 11 is formed.

Next, a predetermined portion of the semiconductor substrate 10 is etched using the first photoresist pattern 12 as an etch barrier to form a rounded recessed region 50. In this case, the recess region 50 is preferably formed using a wet etching process.

Subsequently, as shown in FIG. 1C, after the first photoresist layer pattern 12 is removed, the gate insulating layer 13, the gate conductive layer 14, and the hard layer are formed on the entire surface of the semiconductor substrate on which the recess region 50 is formed. The mask film 15 is sequentially deposited. At this time, the gate conductive film 14 is preferably formed of a polysilicon film.

Next, a second photoresist pattern 16 defining a gate structure formation region is formed on the hard mask layer 15. Subsequently, the hard mask layer 15, the gate conductive layer 14, and the gate insulating layer 13 are sequentially etched using the second photoresist layer pattern 16 as an etch barrier to form the gate 100. Next, low concentration impurity ions are implanted into the semiconductor substrate 10 on both sides of the gate 100.

Next, as shown in FIG. 1D, the second photoresist layer pattern 16 is removed, and then a silicon nitride layer is deposited on the upper surface of the entire structure where the low concentration impurity ion implantation is performed. Next, the silicon nitride layer is isotropically etched to form spacers 17 on both sidewalls of the gate 100. Then, high concentration impurity ions are implanted into the semiconductor substrate 10 on both sides of the spacer 17 to form source / drain regions 18a and 18b.

The transistor manufacturing method of the semiconductor device according to the present invention as described above has the following effects.

A recess region 50 may be formed on the lower surface of the gate to secure a channel length between the source and drain regions. Therefore, when forming a transistor having an ultra fine line width, short channel margin can be secured, hot carrier generation can be suppressed, and reliability of the semiconductor device can be increased.

In addition, it can change and implement variously in the range which does not deviate from the summary of this invention.

Claims (2)

Providing a semiconductor substrate having a device isolation film; Forming a first photoresist pattern defining a gate structure formation region on the semiconductor substrate; Etching a predetermined portion of the semiconductor substrate using the first photoresist pattern as an etch barrier to form a recess region; After removing the first photoresist pattern, sequentially depositing a gate insulating film, a gate conductive film, and a hard mask film on the entire surface of the semiconductor substrate on which the trench is formed; Forming a second photoresist pattern on the hard mask layer to define a gate structure formation region; Forming a gate by sequentially etching the hard mask layer, the gate conductive layer, and the gate insulating layer using the second photoresist pattern as an etch barrier; Low concentration impurity ion implantation into the semiconductor substrate on both sides of the gate; Forming spacers on both sidewalls of the gate; And And implanting a high concentration of impurity ions into the semiconductor substrate on both sides of the space to form a source / drain region. The method of claim 1, The recess region forming process uses wet etching.