KR100983408B1 - Thin film memory, array, and operation method and manufacture method therefor - Google Patents

Abstract

Memory cells, and memory cell arrays, formed on a fully depleted SOI or other semiconductor thin film and operating at low voltages without the need for conventional large capacitors are provided. The semiconductor thin film is interposed between the first semiconductor region and the second semiconductor region, which face each other over the semiconductor thin film and have the second conductivity type. The third semiconductor region having a reverse conductivity type is provided in the expanded portion of the semiconductor thin film. From the third semiconductor region, carriers of reverse conductivity type are supplied to and accumulated in the semiconductor thin film portion, whereby a first conductivity is formed in the semiconductor thin film between the first semiconductor region and the second semiconductor region by the first conductive gate voltage through the insulating film. The gate threshold voltage of the channel is changed.

Description

Thin film memory, array, operation method and manufacturing method {THIN FILM MEMORY, ARRAY, AND OPERATION METHOD AND MANUFACTURE METHOD THEREFOR}

1 is a cross-sectional view illustrating the principles of the present invention.

2A and 2B are plan and cross-sectional views illustrating embodiments of the present invention.

3 is a plan view showing another embodiment of the present invention in which the first conductive gate and the second conductive gate are continuous;

4A and 4B are a plan view and a sectional view of yet another embodiment of the present invention in which a third conductive gate is installed on a second main surface of the semiconductor thin film;

5A and 5B are plan views and cross-sectional views of a cell portion in which memory cells of the present invention are arranged and connected to form an array structure;

6A-6G are cross-sectional views illustrating examples of processes for fabricating memory cells and arrays of the embodiments shown in FIGS. 5A and 5B.

FIG. 7 is an equivalent circuit diagram of the memory cell array shown in FIGS. 5A and 5B.

8 is a plan view of an array of memory cells and array in which write bit lines and read bit lines are shared;

FIG. 9 is an equivalent circuit diagram of the memory cell array of FIG. 8. FIG.

<Description of the symbols for the main parts of the drawings>                 

100; Semiconductor thin film 101; First plane

102; Second principal plane 10; Substrate

20; Insulating film 110; First semiconductor region

120; Second semiconductor region 130; Third semiconductor region

110s; Silicide layer 220; Second gate insulating film

300; A conductive gate thin film 310; First conductive gate

330; Third conductive gate 51; Photoresist pattern

1000; Memory cell 1001; Word line

1003; Common line

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memories and integrated circuits constructed therefrom, and more particularly to a technique using a semiconductor thin film such as a semiconductor on insulator (SOI) or a semiconductor on nothing (SON) for a channel formation region. The semiconductor thin film is formed on the insulating substrate SOI in some cases, and in other cases, both ends thereof are held by the substrates in the cavity state SON, and in another case, the semiconductor thin film has protrusions having one end connected to the substrate.

H. second. Wan et al. Proposed in 1993 to obtain a dynamic memory without a capacitor by mounting two complementary transistors in a partially depleted SOIMOS transistor structure (see Non-Patent Document 1, for example).

Recently, carrier multiplication phenomena, such as avalanche breakdown in the high field region of the drain of a partially depleted SOIMOS transistor, are used to generate carriers and charge these obtained carriers in a neutral body to A memory for changing the current flowing between the sources has been proposed (see, for example, Non-Patent Document 2).

The term partially depleted SOI, abbreviated as PD SOI, refers to an SOI in which the depletion layer only partially diffuses in the depth direction of the semiconductor thin film to make it a neutral region. "Body" is a term for simply referring to the above-described semiconductor thin film in which a channel is formed.

[Non-Patent Document 1]

International Electron Device Meeting (IEDM) Technical Digest, pp. 635-638. second. city. "DRAM cell without capacitor on SOI substrate",

[Non-Patent Document 2]

In February 2002, in IEEE Electronics Letter, Volume 23, No. 2, pages 85-87, S. "1T-DRAM cells without capacitors" such as oconin.

On the other hand, fully depleted (FD) SOI is used for low power consumption or for advanced miniaturization of SOIMOS transistors, thereby creating a need for SOI memory cells that can be applied to FDSOI. The term FD (Full Depletion) SOI refers to an SOI having a thickness and an impurity concentration that causes the entire depth of the semiconductor thin film to be a depletion layer by the gate bias of a transistor fabricated therein.

Also, the method of using carrier multiplication in the high electric field portion of the drain causes a slight carrier multiplication in an unselected cell connected to the bit line to drive the drain of the cell to which the signal is to be written to the high voltage. This results in a slight, if not written, "write disturb" that makes it difficult to assemble a large array in which multiple cells are connected to each bit line. In addition, the method requires a relatively large current and prevents parallel programming of multiple cells.

SUMMARY OF THE INVENTION The present invention has been made in light of the foregoing, and an object of the present invention is to provide a capacitor-free SOI or other semiconductor thin film memory cell and a memory cell applicable to FDSOI. It is still another object of the present invention to provide an SOI or other semiconductor thin film memory cell and memory cell in which data is written or erased without using carrier multiplication in the high electric field portion of the drain, and an operation method and a manufacturing method for the memory cell and array. To provide.

In order to achieve the above objects, the present invention provides a method of supplying carriers from a third semiconductor region that is not a drain or a source to (1) the body, without (2) using carrier multiplication in the high electric field portion of the drain. Adopt.

Embodiment

The memory cell of the present invention is shown in FIGS. 1 and 2A and 2B. 1 is an example of a cross-sectional view of a semiconductor cell of the present invention. FIG. 2A is an example of the top view and FIG. 2B is a sectional view taken along the line X-X 'of FIG. 2A. As shown in these figures, the memory cell,                     

A semiconductor thin film 100 having a first principal surface 101 and a second principal surface 102 facing the first principal surface;

A first gate insulating film 210 formed on the first main surface of the semiconductor thin film;

A first conductive gate 310 formed on the first gate insulating film;

A first semiconductor region 110 and a second semiconductor region, which are separated from each other over the first conductive gate, are insulated from the first conductive gate, are in contact with the semiconductor thin film 100, and have a first conductivity type. 120); And

And a third semiconductor region 130 having a reverse conductivity type and in contact with the semiconductor thin film.

The semiconductor thin film 100 has a potential of a first conductive gate that causes depletion of carriers between the first and second main surfaces 101 and 102 between the first and second semiconductor regions under the first conductive gate. Has a combination of thickness and impurity concentration relationships present.

In the memory cell provided by the present invention, the semiconductor thin film is interposed between the first semiconductor region 110 and the second semiconductor region 120 and extends from the semiconductor thin film portion designated 103 to the third semiconductor region 130. A second gate insulating film 220 is formed on this extended portion of the semiconductor thin film, denoted by 104, and a second conductive gate 320 is formed on the second gate insulating film 220.

2A and 2B, reference numeral 421 denotes an inter-gate insulating film provided to insulate the first conductive gate and the second conductive gate, which overlap each other, if necessary. Reference numeral 400 is a so-called field insulating film. Reference numerals 413 and 431 denote insulating films formed on the third semiconductor region and insulating films formed on the first conductive gate, respectively. 113, 123, 133, 313, 323, if necessary, are installed to act as contacts to the first, second, third semiconductor regions and to the first and second conductive gates. 1 corresponds to a cross-sectional view taken along the line Y-Y 'of FIG. 2A. Such a cell does not necessarily have the contacts described above. In particular, the contact to the conductive gate can be shared between multiple cells because the conductive gate frequently forms part of the word line.

The first conductivity type channel is caused in a portion of the semiconductor thin film interposed between the first semiconductor region 110 and the second semiconductor region 120 due to the potential exceeding the gate threshold voltage of the first conductive gate. In the present invention, the semiconductor thin film portion 103 is referred to as a first channel forming semiconductor thin film portion.

In the semiconductor thin film extension 104, carriers of reverse conductivity are induced, or channels for the carriers of reverse conductivity are formed by the potential difference between the second conductive gate and the third semiconductor region. The extended portion 104 is referred to as a second channel forming semiconductor thin film portion in the present invention. In order to adjust the gate threshold voltage of the carrier channel which is a reverse conduction type in the second conductive gate, an extension portion 104 may be formed with a portion 105 having a different conductivity type or different impurity concentration from the other expansion portion 104. It may be. In the present invention, the above-mentioned "potential above the gate threshold voltage" means a potential whose absolute value is larger than the gate threshold voltage in the positive direction when the transistor is an n-channel transistor and a gate threshold voltage in the negative direction when the transistor is a p-channel transistor. Rather, it means a potential with a large absolute value.

The distance between the first main surface and the second main surface is referred to as the thickness of the semiconductor thin film in the present invention.                     

According to the first combination of the potential of the second conductive gate and the potential of the third semiconductor region, the gate threshold voltage of the first conductive channel in the first channel forming semiconductor thin film portion viewed from the first conductive gate is changed to the first value Vth _11. In order to change), carriers 2 of the reverse conductivity type are injected into the first channel forming semiconductor thin film portion from the third semiconductor region through the second channel forming semiconductor thin film portion. This operation is referred to as "writing" in the present invention.

According to the potentials of the first combination, a value obtained by subtracting the potential of the third semiconductor region from the potential of the second conductive gate is a channel induced in the second channel forming semiconductor thin film portion to move the carriers of the reverse conductivity from the third semiconductor region. Exceeds the gate threshold voltage of Vth _2r . Vth _2r is the gate threshold voltage seen from the second conductive gate.

As the carriers of the reverse conductivity type are injected into the first channel forming semiconductor thin film portion, the gate voltage required for the first conductive gate to generate the first conductive channel is a level corresponding to the number of carriers or charges injected into the reverse conductivity type. Is reduced. This means that the gate threshold voltage has been shifted to the depletion equivalent. If the gate threshold voltage is changed within the range of the improved type, this means that the absolute value of the gate threshold voltage is reduced.

Multiple level settings are possible with the first potential combination. For example, a value obtained by subtracting the potential of the third semiconductor region from the potential of the second conductive gate is the second conductive gate of the channel induced in the second channel forming semiconductor thin film portion such that the reverse conductive carriers are moved in the third semiconductor region. As seen from the above, on the premise that the gate threshold voltage Vth _2r is sufficiently exceeded, the potential of the third semiconductor region is set to a plurality of levels with respect to the gate potential. Accordingly, it is possible to change the gate threshold voltage of the first conductive channel seen from the first conductive gate into values Vth ₁₁ , Vth ₁₂ , Vth ₁₃ ,..., For writing. In summary, it is possible to store multiple bit information in one cell.

The reverse conductive carriers 2 injected into the first channeling semiconductor thin film gradually decrease due to recombination with the carriers of the first conductivity type or as they exit from the first channeling semiconductor thin film due to their own field. Therefore, it is necessary to read the amount of counter conductive carriers accumulated in the first channel forming semiconductor thin film portion and rewrite it based on the reading. This is called "refresh".

By the second combination of the potential of the second conductive gate and the potential of the third semiconductor region, the gate threshold voltage of the first conductive channel in the first channel forming semiconductor thin film portion viewed from the first conductive gate is changed to the second value Vth _10. To reverse), the carriers 2 of reverse conductivity are drawn from the first channeling semiconductor thin film portion to the third semiconductor region. This operation is referred to as "erasing" in the present invention.

According to the potential relationship of the second combination, the value obtained by subtracting the potential of the reverse conductive type injected into the first channel-forming semiconductor thin film portion from the potential of the second conductive gate is the weight factor in the second channel-forming semiconductor thin film portion viewed from the second conductive gate. Exceeds the typical gate threshold voltage (Vth _2r ).

Alternatively, the erase operation is achieved by applying a potential in the direction of drawing the reverse conductive carriers to the first or second semiconductor region (eg, 0.6 V or more in the negative direction with respect to the holes). In this case, carriers of the first conductivity type are also supplied to the first channeling semiconductor thin film portion to accelerate the reduction of the carriers of the reverse conductivity through recombination. In this erasing operation, data is erased from all the cells in which the second semiconductor region or the first semiconductor region is connected to the common line or the bit line.

The information stored in the memory cell of the present invention is determined by the amount of storage or whether the carriers of the reverse conductivity type are stored in the first channel forming semiconductor thin film of the memory cell. To determine the stored information in this way, the voltage of the first conductive gate with respect to the second semiconductor region is set to a prescribed value exceeding one or both of the first gate threshold voltage and the second gate threshold voltage and the first It is detected whether the current flowing between the semiconductor region and the second semiconductor region is large or small ("small" includes zero). For example, the voltage of the first conductive gate with respect to the second semiconductor region is set at a level within the range of the first gate threshold voltage to the second gate threshold voltage and whether a current flows between the first semiconductor region and the second semiconductor region. To detect the stored information.

When multiple levels of the first threshold voltages are written, the voltage of the first conductive gate is set to a level between any two of these levels to identify stored data. Alternatively, the voltage of the first conductive gate with respect to the second semiconductor region is set to a voltage exceeding both the first gate threshold voltage and the second gate threshold voltage and the stored information is a current flowing between the first semiconductor region and the second semiconductor region. Determined from the quantity

In order to detect the current, a known method such as comparison detection using a reference current and a comparator circuit, or detection by a time constant for charging or discharging a bit line or a bit line having an additional capacity can be adopted. This operation is called 'read'.

Through the read operation, the potential of the valence band and the conduction band in the energy band of the first channel-forming semiconductor thin film portion is shifted in the direction of erasing carriers of the reverse conductivity type. Also, a large amount of first conductive carriers are supplied to the first channeling semiconductor thin film portion to accelerate the recombination of the reverse conductive carriers stored in the first channeling semiconductor thin film portion and in some cases to lose information. In this case, the refresh operation should be performed immediately after reading.

1, the semiconductor thin film 100 is supported by a substrate 10 having an insulating film 20 formed thereon. In most cases, the substrate 10 is made of silicon and the insulating film 20 is a silicon oxide film. A supporting substrate having an insulating layer on its surface is called an insulating substrate. For example, an insulating substrate formed entirely of insulating material, such as a quartz substrate, may also be used as the supporting substrate. An alternative structure is a structure in which at least one end of the semiconductor thin film, or the end of the first semiconductor region, the second semiconductor region, or the third semiconductor region is supported by the substrate.

In the present invention, if the voltage of the first conductive gate and the voltage of the second conductive gate are carefully selected during the write operation, the erase operation, and the read operation, the same voltage can be used for each operation mode. The first and second conductive gates can then be continuously or shared as shown in FIG. 3. In addition, the same material and thickness may be employed as the gate insulating layers. As a result, the number of manufacturing steps and the area occupied by the cell are reduced. In this case, in the description of the write operation and the erase operation of the present invention, it is possible to realize the write operation and the erase operation by replacing the 'second conductive gate' with the 'first conductive gate'.

It is also possible in the present invention to write the first gate threshold voltage value under certain conditions and to write the second gate threshold voltage value under some other conditions. For example, the first gate threshold voltage is a value obtained by subtracting the potential of the third semiconductor region from the potential of the second conductive gate while the potential of the third semiconductor region is forward biased with respect to the potential of the second semiconductor region. This is written when the gate threshold voltage Vth _2r of the channel formed in the second channel forming semiconductor thin film portion is moved so that carriers of the reverse conductivity type are moved from the third semiconductor region seen from the second conductive gate. On the other hand, the second gate threshold voltage is written (equivalent to erasing) when the potential of the third semiconductor region is zeroed or biased in reverse with respect to the second gate voltage.

Another preferred embodiment for effectively carrying out the present invention is the memory cell shown in FIGS. 4A and 4B. Memory cells,

A semiconductor thin film having a first main surface 101 and a second main surface 102 facing the first main surface (divided into portions 103 and 104);

A first gate insulating film 210 formed on the first main surface of the semiconductor thin film;                     

A first conductive gate 310 formed on the first gate insulating layer;

A first semiconductor region 110 and a second semiconductor region 120 that are spaced apart from each other over the first conductive gate, insulated from the first conductive gate, in contact with the semiconductor thin film, and having a first conductivity type ;

A third semiconductor region 130 having an opposite conductivity type and in contact with the semiconductor thin film;

A third gate insulating film 230 formed on the second main surface of the semiconductor thin film portion (first channel forming semiconductor thin film portion) interposed between the first semiconductor region and the second semiconductor region; And

And at least a third conductive gate 330 in contact with the third gate insulating layer 230. In the present invention, the semiconductor thin film portion 104 is also referred to as a second channel forming semiconductor thin film portion.

If the potential of the reverse conductive carriers induced in the first channel forming semiconductor thin film portion exceeds the gate threshold voltage Vth _3r , which is the gate threshold voltage seen from the third conductive gate, the reverse conductive carriers are applied. It is stably stored in the first channel forming semiconductor thin film. However, since the reverse conduction carriers are gradually generated and stored in the first channel forming semiconductor thin film portion due to thermal excitation, slight carrier multiplication in a normal electric field, etc. after the erase operation, a refresh operation is also required in this case.

4A is a plan view of the thin film memory cell of this embodiment, and FIG. 4B is a cross-sectional view taken along the line X-X 'of the plan view of FIG. 4A. 4A and 4B, reference numeral 10 denotes a support substrate, and 20 denotes an insulating film on the surface of the support substrate 10. In FIG. 103 and 104 are portions of the first and second channel forming semiconductor thin films which are portions of the semiconductor thin film 100, respectively. 210 and 220 represent gate insulating layers formed on the semiconductor thin film portions 103 and 104. In the drawing, the gate insulating layers 210 and 220 are continuous. 310 denotes a first conductive gate that is also continuous from the second conductive gate. 110 and 120 are first and second semiconductor regions, respectively. 130 represents a third semiconductor region.

113 and 123 represent wiring contacts leading to the first and second semiconductor regions, respectively. 133 represents a wiring contact leading to the third semiconductor region. 400 is a so-called field insulating film underlying the interconnect film or the like. Reference numeral 431 denotes an insulating film on the first conductive gate and 410 denotes an insulating film disposed between the semiconductor thin film 100 and the insulating film 20. 313 represents a wiring contact leading to the first conductive gate. 333 represents the wiring contact provided to reach the third conductive gate if necessary.

It is not always necessary for each cell to have the contacts described above. In particular, the contact to the conductive gate can be shared among a plurality of cells since the conductive gate frequently forms part of the word line. The impurity region 105 may be formed if the electric field of the third conductive gate affects the semiconductor thin film portion 104 less than the semiconductor thin film portion 103 (that is, the third conductive gate is formed as shown in FIG. 4B). If the third conductive gate overlaps with the semiconductor thin film portion 104 unless otherwise overlapped with the 104 or the insulating film thicker than the third gate insulating film 230 is interposed therebetween, it is not always necessary.

In the above-described embodiments, the first and second conductive gates may be conductive or impurity concentrations of impurities in the second channel forming semiconductor thin film, or the second conductive gate material may be impurity types or impurity concentrations in the first channel forming semiconductor thin film. Or may have different gate threshold voltages if different from the first conductive gate material. In the reverse conductive carriers injected into the second channel forming semiconductor thin film portion, the gate threshold voltage of the second conductive gate in relation to the channel for the carriers of the conductive type opposite to the third semiconductor region is greater than the gate threshold voltage of the first conductive gate. If set to a high level in the improved direction, the reverse flow to the third semiconductor region is prevented.

Example

The memory cell operation is described below with the first conductivity type being n type and the reverse conductivity type being p type. The principles and effects provided in the following description will be reversed in polarity and direction of change, but also apply when the first conductivity type is p-type. 5A is a top view of an embodiment of a memory cell and an array of memory cells of the present invention. FIG. 5B is a cross-sectional view taken along the line X-X 'of the plan view of FIG. 5A.

Reference numeral 10 denotes a support substrate which in this example is a high resistance n-type silicon <100> planar wafer. 20 is a silicon oxide film having a thickness of about 100 nm. 103 shows a semiconductor thin film of about 30 nm thickness serving as the first channel forming semiconductor thin film portion of the thin film memory cell 1000 in this embodiment. 104 denotes a second channel forming semiconductor thin film portion. 105 denotes a high impurity concentration of the second channel forming semiconductor thin film portion. 110 denotes a drain (first semiconductor region). 114 is a drain extension. 120 is a source (second semiconductor region). 124 is a source extension. 130 is a third semiconductor region of reverse conductivity type. 210 is a 2.7 nm thick first gate nitrided oxide film. 220 is a second gate nitride oxide film. 310 and 320 are a first conductive gate and a second conductive gate continuous to the first continuous gate. (300 is a symbol as a conductive gate thin film. 1001 is a functional symbol as a local word line).

210 and 220 are consecutive gates. The first conductive gate is about 100 nm in length in this embodiment and is formed from a silicon thin film to which boron is added. The first, second and third semiconductor regions include a semiconductor film formed by epitaxial growth on a semiconductor thin film. The first and second channel forming semiconductor thin film portions 103 and 104 in one cell are spaced apart from the first and second channel forming semiconductor thin film portions 103 and 104 in the adjacent cell by the spacer insulating film 401. .

113 is a contact leading to the first semiconductor region, and the contact is connected to the read bit line 1005. 113 represents a contact leading to the third semiconductor region, and the contact is connected to the write bit line 1004. The continuous first and second conductive electrodes 310 (320) extend continuously between the cells in the word direction to form a local word line 1001. The second semiconductor region extends between the cells in the word direction to form a local common line 1003. The local word line and the local common line are extended as long as the direct resistance does not affect the array operation, and each is connected through a select transistor or directly to the global word line and the global common line. In a large capacity array, the two types of bit lines described above are connected via select transistors to the bit lines of their respective power.

In the array configuration of FIG. 5A, the cells 1000 are repeatedly arranged in a mirror image relationship in the bit direction. As a result, the contacts 113 and 133 are shared between cells adjacent to each other in the bit direction. The first and third semiconductor regions are contiguous from one cell to its adjacent cell in one direction of the bit direction. This reduces the array area. FIG. 5A shows a total of eight cells (cells 1000 (j, k), ..., cells 1000 (j + 1, k + 3), with two cells in the word direction and four cells in the bit direction. A mirror image arrangement of cells is employed in the embodiment of FIG.

The manufacturing process of this embodiment will be described below with reference to the cross-sectional views of FIGS. 6A-6G and 5B.

(a) Silicon having a silicon oxide film 20 having a thickness of about 100 nm and an n-type impurity concentration of about 2 x 10 ¹⁷ atoms / cc and a thickness of about 35 nm using a high resistance silicon wafer as the support substrate 10. The thin film 100 is stacked on the substrate to prepare an SOI substrate.

(b) On the SOI thus obtained, the oxide film 41 is grown until thermally oxidized to a thickness of about 7 nm, and a silicon nitride film 42 having a thickness of about 50 nm is formed thereon by CVD. Thereafter, the photoresist pattern 51 is formed by known photolithography so as to protect necessary portions of the silicon thin film, such as regions where the memory cells are connected in word and bit directions, select transistor regions and peripheral circuit regions. do.

(c) Using the photoresist pattern 51 as a mask, the silicon nitride film is etched under etching conditions that provide a selectivity with respect to the silicon oxide film so as to leave the silicon oxide film. The photoresist pattern is then removed and the substrate surface is cleaned. The exposed surface of the silicon oxide film exposed by the removal of the silicon nitride film is oxidized by heat oxidation until the silicon oxide film 401 grows to a thickness of about 60 nm. Through this step, the silicon thin film 100 is divided into several parts, leaving the necessary parts given above.

Alternatively, the silicon thin film may be divided using known STI (shallow trench isolation) techniques. An insulating film dividing the silicon thin film in the planar direction is called an insulating separator 401.

The silicon nitride film 42 is removed with a hot phosphoric acid based etchant and the silicon oxide film 41 is removed with a buffered hydrofluoric acid based etchant to expose the surface of the silicon thin film 100.

The silicon oxide film 200 is formed to a thickness of 2.7 nm on the surface of the silicon thin film 100 by thermal oxidation. Subsequently, nitrogen radicals are introduced into the substrate surface from the plasma of nitrogen gas, hydrogen gas, or xenon gas by using a high density plasma apparatus other than Electron Cyclotron Resonance (ECR), Inductively Coupled Plasma (ICP), and the like. By setting it at 400 ° C., the surface is nitrided at a nitriding ratio of 5 to 7%. The substrate is then heat treated at 800 ° C. in nitrogen to transfer the substrate into a high purity nitrogen gas atmosphere and anneal surface defects. The nitrided silicon oxide film is used as the first and second gate oxide films.

(d) Next, the conductive gate thin film 300 is formed by deposition. For the initial 10 nm and the like, pure silicon is deposited to form the pure silicon thin film 301. Subsequently, the silicon thin film 302 to which boron is added is formed by deposition to a thickness of 200 nm. The material gases used are monosilane (SiH ₄ ) and diborane (B ₂ H ₆ ). To this end, a silicon nitride film 43 is formed to a thickness of about 100 nm by deposition. Ion implantation may be employed as an alternative method for the boron addition.

Using a known technique such as ArF lithography or electron beam lithography, a gate-shaped photoresist pattern for a conductive gate / local word line having a gate length of about 100 nm is formed on the silicon nitride film / conductive gate thin film. The silicon nitride film and the conductive gate thin film are etched in this order by the RIE technique using the photolithography pattern as a mask.

The photoresist film formed by photolithography and the silicon nitride film / conductive gate thin film were used as the selection masks, and ion implantation was carried out at a low speed voltage (about 15 KeV for arsenic) to form an n-type drain (first semiconductor region). The extended region 114 and the extended region 124 of the source (second semiconductor region) are selectively formed. In the ion implantation, the implantation amount is set to obtain an impurity concentration of about 1 x 10 ¹⁹ atoms / cc (about 3 x 10 ¹³ atoms / cm ² ).

Similarly, using a photoresist film shaped by photolithography and a silicon nitride film / conductive gate thin film as the selection masks, arsenic is selectively selected in the portion forming the third semiconductor region at an implantation amount of about 8.5 x 10 ¹² atoms / cc. Inject In this way, since the high impurity concentration region 105 is formed in the second channel forming semiconductor thin film portion, it is in contact with the third semiconductor region formed in the subsequent step. This shifts the gate threshold voltage Vth _2r of the channel for holes from the third semiconductor region seen from the second conductive gate to the improvement side.

(e) Using known gate sidewall insulating film processes, insulating film sidewalls 403 each having a thickness of about 30 nm are formed on the sides of the first and second conductive gates. The sidewalls are a two-layer stack consisting of a silicon nitride film 404 having a thickness of about 7 nm and a silicon oxide film 405 having a thickness of about 23 nm. In this step, the silicon nitride film 404 is left on the semiconductor thin film.

Using lithography, a photoresist pattern having openings is formed in the portion where the third semiconductor region is to be formed. Subsequently, after removing the photoresist and wet etching the silicon oxide film remaining in the opening, hydrogen termination is performed.

The boron-doped silicon crystal film 135 is selectively grown in the opening until it becomes about 100 nm thick. The boron concentration is about 4 x 10 ¹⁹ atoms / cc. Through thermal oxidation at 850 ° C., an oxide film 406 about 30 nm thick is grown on the top and side surfaces of the p-type silicon crystal film. In this case, boron diffuses from the silicon crystal film 135 to the semiconductor thin film 100 so that a portion of the semiconductor thin film below 135 becomes a p-type conductivity. In Fig. 6E, this portion is distinguished from the selectively grown silicon crystal film.

(f) The silicon nitride film 404 left on the memory cell portions of the semiconductor thin film 100 is etched by RIE. The silicon oxide film remaining on the etching surface is wet etched and then hydrogen terminated. When etching the silicon nitride film, the portion of the silicon nitride film under the oxide film 406 on the side of the crystal thin film selectively grown to form the semiconductor region 130 is excluded.

Arsenic-doped silicon crystal films 115 and 125 are selectively grown in the openings to a thickness of about 100 nm, respectively. Arsenic concentration is about 5 x 10 ²⁰ atoms / cc. The oxide film 406 on the side separates the p-type high impurity concentration silicon crystal film 135 from the n-type high impurity concentration silicon crystal films 115 and 125.

Instead of the above-described selective crystal growth, selective ion implantation using photoresist patterns and conductive gate thin films as the masks and a silicon nitride film thereon may be employed to form the first, second and third semiconductor regions.

During the crystal growth and subsequent heating steps, impurities of these silicon crystal films obtained through selective crystal growth diffuse into the semiconductor thin film 100 starting from the points where the crystal films and the semiconductor thin film meet. As a result, the third semiconductor region 130, the first semiconductor region 110, and the second semiconductor region 120 are formed at the same time, and the silicon crystal thin films are formed by selective crystal growth.

(h) Wet etching is performed on the silicon nitride film 43 on the conductive gate thin film 300 by high temperature phosphoric acid or the like. The surface is then rinsed, nickel is deposited to a thickness of about 20 nm by evaporation and then sintered. Nickel on the unreacted insulating film is etched with acid to leave a nickel silicide layer. Through high temperature sintering, the silicide layer 110s is formed on the first semiconductor region (drain), the silicide layer 120c is formed on the second semiconductor region (source), and the silicide layer 300s is formed on the gate thin film. Is formed.

A silicon oxide film is formed as the interlayer insulating film 440 for interconnection on the surface by CVD. Contact holes are opened in the required film to form contact plugs 133 and 113 from titanium nitride, tungsten or the like. Subsequently, a TiN film and a tungsten thin film are formed by evaporation. In order to obtain the local wiring bit line 1004 and the local read bit line 1005, wiring patterns are formed by photolithography and RIE (reactive ion etching) (at this time, the state of FIG. 5B is reached). Thereafter, necessary additional interlayer insulating films and a multilayer interconnection composed of Al films, copper films and the like are formed, and finally a passivation film is formed.

The characteristics of this embodiment are that (1) the third semiconductor region and the first semiconductor region are insulated by an insulating film 406 formed on the side of the crystal thin film obtained by selective epitaxial growth, and (2) the third semiconductor region. The gate threshold voltage for causing the reverse conductive carrier is different between the reverse conductive carrier channel from the first channel forming semiconductor thin film portion to the first channel forming semiconductor thin film portion.

Since the reverse conductive carrier channel from the third semiconductor region to the first channel forming semiconductor thin film portion crosses the high impurity concentration region 105 in contact with the third semiconductor region, the impurity concentration of the second channel forming thin film portion is equal to the first. It is different from the impurity concentration in the channel forming thin film portion. Accordingly, the gate threshold voltages for inducing the reverse conductive carriers are different from each other in the reverse conductive carrier channel extending from the third semiconductor region to the first channel forming semiconductor thin film portion.

If a barrier to the reverse conductive carriers is formed between the first channel forming semiconductor thin film portion and the third semiconductor region as described above, a voltage in the direction of inducing the carriers of the first conductive type is applied to the first conductive gate. In this case, the amount of carriers of the reverse conduction type that are re-introduced into the third semiconductor region during readout is reduced. Therefore, reading can be performed without fear of erasing the stored information.

In the embodiment shown in FIGS. 5A and 5B, the first semiconductor regions of the cells arranged in the column direction are connected to the read bit line 1005 and the third semiconductor regions of these cells are connected to the wiring bit line 1004. . The first and second common conductive gates of the cells arranged in the row direction are connected to the word line 1001. Second semiconductor regions of the cells arranged in the row direction are connected to the common line 1003. The read bit line and the write bit line extend in the column direction while the word line and the common line extend in the row direction. The alignment of the cells and the vertical and horizontal relationship of the bitline and wordline can be exchanged without causing any problems.

The operation of a single cell manufactured according to the above embodiment is described below. The potential of the second conductive gate relative to the potential of the third semiconductor region is written into this cell by setting the potential of the second conductive gate to a level exceeding the threshold voltage Vth _r2 of the reverse conductivity carrier channel under the second conductive gate.

In the cell manufactured by the above-described manufacturing process, Vth _r2 is about -0.5V when the potential of the second semiconductor region is 0V, so the potential of the third semiconductor region is set to 0.2 to 0.3V and the second conductive gate is -0.3. It is preferable to set to -0.4V. In order to retain the data, it is preferable to set the second conductive gate to 0 to 0.2V and the first semiconductor region to the same potential as the second semiconductor region.

In order to erase data, the second semiconductor region is set to -0.6V or less (when the potential of the first semiconductor region is 0V and the first conductive gate is 0V), or the potential of the third semiconductor region is 0 to -0.4. It is set to V and the potential of the second conductive gate is set to -0.55V or less. Accordingly, the reverse conductive carriers (holes) stored in the first channel forming semiconductor thin film portion go to the second semiconductor region or the third semiconductor region.

In order to read the data, whether the current flowing between the first semiconductor region and the second semiconductor region is large or small is determined by about the first conductivity type carrier gate threshold voltage Vth ₁₀ (at most 0.2) of the first conductive gate in the cell from which data is erased. V is applied) to the first conductive gate. In the case of storing a plurality of values, a voltage between Vth ₁₀ and Vth ₁₁ , a voltage between Vth ₁₁ and Vth ₁₂ , a voltage between Vth ₁₂ and Vth ₁₃ , ... is applied to the first conductive gate to detect stored information. . The voltage applied between the first semiconductor region and the second semiconductor region is 0.2V to 0.9V. An intermediate current between the current of the cell to which data is written and the current of the cell to which data is erased is taken as a reference value. When a voltage between one stored threshold voltage and another stored threshold voltage is applied to the first conductive gate, information is determined from the presence or absence of cell current.

In order to prevent writing errors (also erase and read errors) caused by carriers of opposite polarities occurring in the high electric field region of the first channel information semiconductor thin film portion, a voltage (thin film) is formed between the first semiconductor region and the second semiconductor region. In the case of silicon, it is safer to avoid applying a voltage higher than the energy gap value of the semiconductor thin film converted to 1.1V).

In Embodiment 1, the cells of the present invention in FIGS. 5A and 5B are connected as shown in the equivalent circuit diagram of FIG. 7 to obtain a memory array. The memory array is operated by the combination of voltages shown in Table 1 below. This array is suitable as a memory for a particular use because data can be written to cells of a word while data is read from cells of another word. The array is also suitable for fast refresh operations. Table 1 shows the voltage relationships between word lines, write bit lines, read bit lines, and common lines when the array is operated with a 1.2V single polarity power supply. Operation with respect to a single pole power supply is made possible by biasing a common line to a positive potential, usually 0.5V.

TABLE 1

Example of the operating voltage of a memory array according to Embodiment 1 of the present invention.

 Selected Cell Voltage (V)  Unselected Cell Voltage (V) entry  elimination Reading Retention  entry  elimination  Reading  maintain CW CB CW CB CW CB Word line 0.1 0 1.2 0.5 0.1 0.5 0 0.5 1.2 0.5 0.5 Write bitline 0.7 0 0.5 0.5 0.5 0.7 0 0 0.5 0.5 0.5 Read bitline 0.5 0.5 0.8 0.5 0.5 0.5 0.5 0.5 0.5 0.8 0.5 Common line 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5

CW (Common Word): Cells that share a wordline

CB (Common Bit): Cells that share a bitline

In the operation shown in Table 1, data is erased from all cells connected to the same word line upon erasing. Acceptable variations in voltage on one line are within ± 0.1V when the voltage on another line has a standard value. If the voltage on every line changes in the same direction, the acceptable potential variation is greater.

It is sufficient if the difference between the potential of each line and the potential of the common line satisfies the relationship shown in Table 1. Therefore, it may be shown as Table 2.

TABLE 2

Relative representation of an operating voltage example of a memory array according to Embodiment 1 of the present invention

 Selected Cell Voltage (V) entry  elimination Reading maintain Word line Common line potential
-0.4 Common line potential
-0.5 Common line potential +0.7 Common line potential Write bitline Common line potential
+0.2 Common line potential Common line potential Common line potential Read bitline Common line potential Common line potential Common line potential
+0.3 Common line potential

According to the array structure for the memory cells of the present invention, the third semiconductor region and the first semiconductor region are connected to the same bit line (one bit line is different from the case in the memory arrays of FIGS. 5A and 5B). Also serves as a read bitline).

This array structure makes it possible to reduce the array area. 8 is a plan view of memory cells used in this array connection and its cell area is between 6F ² and 4F ² . In order to achieve a cell area of 4F ² , a long-term alignment contact technique is required.

The cell arrangement in the array of FIG. 8 is similar to that of FIGS. 5A and 5B, wherein the conductive gates in one cell are above the first, second and third semiconductor regions, and this positional relationship is reversed in all other cells in the longitudinal direction. While the first, second, and third semiconductor regions in a cell are contiguous with those in its adjacent cells in the column direction. For example, the first and third semiconductor regions of the kth cell in the column direction are contiguous with those in the k + 1th cell. The second semiconductor region of the j th cell is continuous to that of the j + 1 cell. The first semiconductor region in one cell and the first semiconductor region in a cell adjacent to this cell in the word direction are electrically isolated from each other when biased with a reverse bias and some forward voltage by the third semiconductor region of their adjacent cells. do.

The semiconductor thin film 100 extending in the word direction including the first semiconductor region and the third semiconductor region is physically continuous. Meanwhile, in the example shown in FIGS. 5A and 5B, the first semiconductor regions in the cells adjacent in the word direction are spaced apart by the insulating film. However, if the distance between the write bit line and the read bit line is narrowed, for example by forming two bit lines from different interconnect layers, FIGS. 5A and 5B show that the semiconductor thin film is continuous and adjacent to the first semiconductor region side as well. The first semiconductor regions may have a structure that is electrically insulated by the third semiconductor region.

In either case, the first channel forming semiconductor thin film portion or the second channel forming semiconductor thin film portion of one cell is spaced apart from that of the cell adjacent to this one cell in the word direction.

Also in the top view of FIG. 8, the first conductive gate and the second conductive gate are continuous and more continuous to the first or second conductive gate of the adjacent cell in the row direction. Since the gate has a series resistance component, the operation speed is limited. To improve this, use a metal wire as the main wordline and use this metal wire as the conductive gates of a group of cells (e.g., one group consists of 32 to 512 cells) before the series resistance reaches a limit value. Is connected to.

In Embodiment 2, the cells of the present invention of FIG. 8 are connected as shown in the equivalent circuit diagram of FIG. 9 to obtain a memory array. The memory array of Embodiment 2 is operated by the combination of voltages shown in Table 3 below.

Table 3 shows an example of the voltage relationship between word lines, bit lines, and common lines when the array is operated by a 1V single-pole power supply. Operation with respect to a single pole power supply is made possible by biasing a common line with a positive potential, normally 0.3V.

TABLE 3

Example of the operating voltage of a memory array according to Embodiment 2 of the present invention.

 Selected Cell Voltage (V)  Unselected Cell Voltage (V)  entry Reading
maintain  Entry (CW)  Entry (CB)  Reading  maintain "One" "0" "One" "0" CW CB "One" "0"  Word line 0 0 1.0 (in advance) 0.3 0 0 0.3 0.3 1.0 0.3 0.3  Bitline 0.6 0 0.5 0.3 0.3 0.3 0.6 0 0.3 0.5 0.3  Common line 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3

CW (Common Word): Cells that share a wordline

CB (Common Bit): Cells that share a bitline

On read, the wordline is supplied before the bitline voltage.

Acceptable variations in voltage on one line are in the range of ± 0.1V when the voltage on another line has a standard value. If the voltages of all the lines fluctuate in the same direction, the acceptable potential fluctuations are greater.

If the difference between the potential of each line and the potential of the common line satisfies the relationship shown in Table 3, it is sufficient. Therefore, it may be shown as Table 4.

Table 4

Relative Representation of an Operating Voltage Example of a Memory Array According to Embodiment 2 of the Present Invention

 Selected Cell Voltage (V) entry Reading maintain  "One"  "0"  Word line Common line potential
-0.3 Common line potential
-0.3 Common line potential
+0.7 (front) Common line potential  Bitline Common line potential
+0.3 Common line potential
-0.3 Common line potential
+0.2 Common line potential

In the present invention, the semiconductor thin film may be a silicon germanium single crystal thin film or a strained silicon / silicon germanium stack other than the silicon single crystal thin film. In addition to the silicon oxide film, the gate insulating film may be a silicon oxynitride film, a silicon nitride film, an aluminum film, a hafnium oxide film, a silicon-hafnium oxide mixed film, a zirconium oxide film, or a silicon-zirconium oxide mixed film. The conductive gates may be a tungsten film, a titanium nitride film, or a titanium / titanium nitride stack, in addition to the polysilicon film or the silicon germanium film. The first, second, and third semiconductor regions may be formed not only on the semiconductor thin film but also on the semiconductor thin film, and a metal silicide film or a metal thin film may be added thereon to form a stack. Accordingly, the present invention can be practiced within the scope of modification that will be readily apparent to those skilled in the art.

The first, second, and third semiconductor regions have been described herein as "contacting" the semiconductor thin film. This contact state is caused by introducing impurity atoms into the semiconductor thin film to form first, second and third semiconductor regions in the film, or by forming first, second and third semiconductor regions on the semiconductor thin film by deposition. Obtained.

The present invention may employ a structure in which the second main surface or the side surface is capacitively coupled to the first channel forming semiconductor thin film portion so that the stored data is retained for a longer period of time and the amount of stored reverse conductive type is increased.

The present invention can be applied to both PDSOI and FDSOI, and when applied to FDSOI, the present invention can provide an effect that was difficult to obtain in the prior art.                     

The present invention can provide not only a PDSOIMIS structure but also a memory cell having an FDSOIMOS structure and an FDSONMIS structure, and a memory array using the memory cell. Memory cells do not require large capacitors.

The memory may be mounted with FDSOI logic capable of operating at low power, and the operating voltage of the memory is within the range of the low power logic.

Even if the cell has a so-called double gate MIS structure, the carriers of the reverse conduction type are reliably stored in the memory cell by the potential applied to the third conductive gate of the cell.

Claims (61)

In a thin film memory cell, A semiconductor thin film having a first principal surface and a second principal surface facing the first principal surface; A first gate insulating film formed on the first main surface of the semiconductor thin film; A first conductive gate formed on the first gate insulating film; A first semiconductor region and a second semiconductor region, spaced apart from each other over the first conductive gate, insulated from the first conductive gate, in contact with the semiconductor thin film, and having a first conductivity type; And A third semiconductor region having a reverse conductivity type opposite to the first conductivity type and in contact with the semiconductor thin film, The semiconductor thin film is a combination of a thickness and an impurity concentration relationship such that a depletion layer covers the entire depth of the semiconductor thin film between the second main surface and the first main surface under the first conductive gate with a bias to the first conductive gate. To have, A portion of the semiconductor thin film interposed between the first semiconductor region and the second semiconductor region forms a first channel forming semiconductor thin film portion, The semiconductor thin film extends between the first channel forming semiconductor thin film portion and the third semiconductor region of the reverse conductivity type to form a second channel forming semiconductor thin film portion, And a second gate insulating film is formed on the extended portion of the semiconductor thin film, and a second conductive gate is formed on the second gate insulating film. The thin film memory cell of claim 1, wherein the first conductive gate and the second conductive gate are continuous. The thin film memory cell of claim 1, wherein the second gate insulating layer is continuous to the first gate insulating layer, and the second conductive gate is continuous to the first conductive gate. The semiconductor device of claim 1, wherein the extended portion of the semiconductor thin film includes a portion having an impurity concentration different from an impurity concentration of the semiconductor thin film portion interposed between the first semiconductor region and the second semiconductor region. Thin film memory cell. The semiconductor device of claim 1, wherein the extended portion of the semiconductor thin film includes an impurity portion having a conductivity type different from that of the semiconductor thin film portion interposed between the first semiconductor region and the second semiconductor region. Thin film memory cells characterized by. In a thin film memory cell, A semiconductor thin film having a first main surface and a second main surface facing the first main surface; A first gate insulating film formed on the first main surface of the semiconductor thin film; A first conductive gate formed on the first gate insulating film; A first semiconductor region and a second semiconductor region, spaced apart from each other over the first conductive gate, insulated from the first conductive gate, in contact with the semiconductor thin film, and having a first conductivity type; And A third semiconductor region having a reverse conductivity type opposite to the first conductivity type and in contact with the semiconductor thin film in a portion of the region under the first conductive gate, The semiconductor thin film is a combination of a thickness and an impurity concentration relationship such that a depletion layer covers the entire depth of the semiconductor thin film between the second main surface and the first main surface under the first conductive gate with a bias to the first conductive gate. To have, A portion of the semiconductor thin film interposed between the first semiconductor region and the second semiconductor region forms a first channel forming semiconductor thin film portion, And the semiconductor thin film extends between the first channel forming semiconductor thin film portion and the third conductive region of the reverse conductivity type to form a second channel forming semiconductor thin film portion. The thin film memory cell of claim 6, wherein the second channel forming semiconductor thin film portion includes a portion having an impurity concentration different from that of the first channel forming semiconductor thin film portion. The thin film memory cell of claim 6, wherein the second channel forming semiconductor thin film portion includes an impurity portion having a conductivity type different from that of the first channel forming semiconductor thin film portion. The thin film memory cell of claim 1, wherein the semiconductor thin film is formed on an insulating substrate. The thin film memory cell of claim 1, wherein at least one end of the semiconductor thin film is supported by a substrate. The semiconductor device of claim 1, further comprising: a third gate insulating layer formed on the second main surface at a portion where the semiconductor thin film is interposed between the first semiconductor region and the second semiconductor region; And And a third conductive gate in contact with the third gate insulating film. The thin film memory cell of claim 11, wherein a surface portion of the substrate supporting the semiconductor thin film acts as a third conductive gate. In a thin film memory array, A plurality of word lines; A plurality of write bit lines insulated from and intersecting the word lines; A plurality of read bitlines next to the write bitlines; A plurality of common lines; And A plurality of memory cells of claim 1, A first and a second of one of the plurality of memory cells in a portion where one of the plurality of word lines intersects one of the plurality of write bit lines and a read bit line that follows one of the write bit lines Two conductive gates are connected to one word line of the plurality of word lines, The first semiconductor region of one of the memory cells is connected to one read bit line of the plurality of read bit lines, The second semiconductor region of one of the memory cells is connected to one common line of the plurality of common lines, And the third semiconductor region of one of the memory cells is connected to one write bit line of the plurality of write bit lines. In a thin film memory array, A plurality of word lines; A plurality of write bit lines insulated from and intersecting the word lines; A plurality of read bitlines next to the write bitlines; A plurality of common lines; And A plurality of memory cells of claim 6, A first conductive gate of one of the plurality of memory cells at a portion where one of the plurality of word lines intersects one of the plurality of write bit lines and a read bit line that follows one of the write bit lines Is connected to one word line of the plurality of word lines, The first semiconductor region of one of the memory cells is connected to one read bit line of the plurality of read bit lines, The second semiconductor region of one of the memory cells is connected to one common line of the plurality of common lines, And the third semiconductor region of one of the memory cells is connected to one write bit line of the plurality of write bit lines. In a thin film memory array, A plurality of word lines; A plurality of bit lines insulated from and intersecting the word lines; A plurality of common lines; And A plurality of memory cells of claim 1, In a portion where one of the plurality of word lines and one of the plurality of bit lines cross each other, the first and second conductive gates of one of the plurality of memory cells are one of the plurality of word lines. Connected to a word line, The first semiconductor region and the third semiconductor region of the one memory cell are connected to one bit line of the plurality of bit lines, And the second semiconductor region of the one memory cell is connected to one common line of the plurality of common lines. In a thin film memory array, A plurality of word lines; A plurality of bit lines insulated from and intersecting the word lines; A plurality of common lines; And A plurality of memory cells of claim 6, At a portion where one of the plurality of word lines and one of the plurality of bit lines cross each other, a first conductive gate of one of the plurality of memory cells is connected to one word line of the plurality of word lines. Become, The first semiconductor region and the third semiconductor region of the one memory cell are connected to one bit line of the plurality of bit lines, And the second semiconductor region of the one memory cell is connected to one common line of the plurality of common lines. The method of claim 15, wherein the first conductive gate and the second conductive gate are continuous through one cell and extend between adjacent cells in a word direction to form part of a word line. And one of the first channel forming semiconductor thin film portion and the second channel forming semiconductor thin film portion in one cell is spaced apart from that of its adjacent cell. 17. The device of claim 16, wherein the first conductive gate extends continuously between adjacent cells in the word direction and forms part of a word line; And one of the first channel forming semiconductor thin film portion and the second channel forming semiconductor thin film portion in one cell is spaced apart from that of its adjacent cell. 17. The thin film memory array of claim 16, wherein some of the common lines are formed from consecutive second semiconductor regions extending over adjacent cells. 19. The method of claim 18, wherein the cells are arranged such that the first semiconductor regions and the second semiconductor regions of adjacent cells form a mirror image relationship to form an array, And the first and third semiconductor regions are contiguous from one cell to their adjacent cell in one direction and the second semiconductor region is contiguous from one cell to its adjacent cell in another direction. The method of claim 16, The semiconductor thin film is continuous in the word line direction, And the first semiconductor region of one cell is electrically insulated by the third semiconductor region from the first semiconductor region of its adjacent cell. A writing method applied to the thin film memory cell of claim 1, The value obtained by subtracting the potential of the third semiconductor region from the potential of the second conductive gate is transferred to the second channel forming semiconductor thin film portion such that carriers of reverse conductivity type are moved from the third semiconductor region seen from the second conductive gate. It is set to a level exceeding the gate threshold voltage Vth _2r of the channel to be induced, By setting the potential difference between the second conductive gate and the third semiconductor region as described above, the carriers of the reverse conduction type are transferred from the third semiconductor region to the first channel forming semiconductor thin film portion through the second channel forming semiconductor thin film portion. And a gate threshold voltage of a first conductive channel in the first channel forming semiconductor thin film portion viewed from the first conductive gate is changed to a first value. A writing method applied to the thin film memory cell of claim 6, The value obtained by subtracting the potential of the third semiconductor region from the potential of the first conductive gate is applied to the second channel forming semiconductor thin film portion such that carriers of reverse conductivity type are moved from the third semiconductor region seen from the first conductive gate. It is set to a level exceeding the gate threshold voltage Vth _2r of the channel to be induced, By setting the potential difference between the first conductive gate and the third semiconductor region as described above, the carriers of reverse conductivity type are transferred from the third semiconductor region to the first channel forming semiconductor thin film portion through the second channel forming semiconductor thin film portion. And a gate threshold voltage of a first conductive channel in the first channel forming semiconductor thin film portion viewed from the first conductive gate is changed to a first value. A writing method applied to the thin film memory cell of claim 1, The value obtained by subtracting the potential of the third semiconductor region from the potential of the second conductive gate is transferred to the second channel forming semiconductor thin film portion such that carriers of reverse conductivity type are moved from the third semiconductor region seen from the second conductive gate. Is set to a level that exceeds the gate threshold voltage of the triggered channel, The potential of the third semiconductor region is set to a plurality of levels with respect to the same second conductive gate potential, so that the first value of the gate threshold voltage has a plurality of levels. In the erase method applied to the thin film memory cell of claim 1, The value obtained by subtracting the potential of the reverse conductive carriers injected into the first channel forming semiconductor thin film portion from the potential of the second conductive gate is the reverse conductive channel in the second channel forming semiconductor thin film portion viewed from the second conductive gate. It is set to a level exceeding the gate threshold voltage of By setting the potential difference as described above, the carriers of the reverse conduction type are introduced into the third semiconductor region from the first channel forming semiconductor thin film portion, and thus in the first channel forming semiconductor thin film portion seen from the first conductive gate. The gate threshold voltage of the first conductive channel is changed to a second value. In the erase method applied to the thin film memory cell of claim 6, The value obtained by subtracting the potentials of the reverse conductive carriers injected into the first channel forming semiconductor thin film portion from the potential of the first conductive gate is the reverse conductive channel in the second channel forming semiconductor thin film portion viewed from the first conductive gate. It is set to a level exceeding the gate threshold voltage of By setting the potential difference as described above, the carriers of the reverse conduction type are introduced into the third semiconductor region from the first channel forming semiconductor thin film portion, and thus in the first channel forming semiconductor thin film portion seen from the first conductive gate. The gate threshold voltage of the first conductive channel is changed to a second value. In the erase method applied to the thin film memory cell of claim 1, And a potential is applied to the first semiconductor region in a direction in which carriers of a reverse conductivity type are drawn out to the first semiconductor region. In the erase method applied to the thin film memory cell of claim 1, And a potential is applied to the second semiconductor region in a direction in which carriers of reverse conductivity are drawn out to the second semiconductor region. In the operating method applied to the thin film memory cell of claim 1, The value obtained by subtracting the potential of the third semiconductor region from the potential of the second conductive gate is transferred to the second channel forming semiconductor thin film portion such that reverse conductive carriers are moved from the third semiconductor region seen from the second conductive gate. Is set to a level that exceeds the gate threshold voltage of the triggered channel, A first gate threshold voltage is written when the potential of the third semiconductor region is forward biased with respect to the potential of the second semiconductor region, And the second gate threshold voltage is written when the potential of the third semiconductor region is biased to zero or inversely with respect to the same second gate voltage. In the method of operation applied to the thin film memory cell of claim 6, The value obtained by subtracting the potential of the third semiconductor region from the potential of the first conductive gate is transferred to the second channel forming semiconductor thin film portion such that reverse conductive carriers are moved from the third semiconductor region seen from the first conductive gate. Is set to a level that exceeds the gate threshold voltage of the triggered channel, A first gate threshold voltage is written when the potential of the third semiconductor region is forward biased with respect to the potential of the second semiconductor region, And a second gate threshold voltage is written when the potential of the third semiconductor region is biased to zero or reverse direction with respect to the same first gate voltage. In the reading method applied to the thin film memory cell of claim 1, The voltage of the first conductive gate with respect to the second semiconductor region is set to a prescribed value exceeding one or both of a first gate threshold voltage and a second gate threshold voltage, and the first semiconductor region and the second A thin film memory cell reading method, characterized in that it is detected to determine stored information whether a current flowing between semiconductor regions is large or small. 23. The method of claim 22, wherein the voltage applied between the first semiconductor region and the second semiconductor region does not exceed a value greater than or equal to an energy gap of the semiconductor thin film to be converted into a voltage. In the method of operation applied to the thin film memory array of claim 14, When writing, the word line potential is obtained by subtracting 0.4V (± 0.1V) from the common line potential, the write bitline potential is obtained by adding 0.2V (± 0.1V) to the common potential, and the read bitline potential Is a common potential, When erasing, the word line potential is obtained by subtracting 0.5 V (± 0.1 V) from the common line potential, the write bit line potential is the common potential, the read bit line potential is the common potential, When reading, the word line potential is obtained by adding 0.7 V (± 0.1 V) to the common line potential, the write bit line potential is the common potential, and the read bit line potential is 0.3 V (± 0.1 V) to the common potential. A method of operating a thin film memory array, which is obtained by adding. In the method of operation applied to the thin film memory array of claim 16, When writing, the word line potential is obtained by subtracting 0.3V (± 0.1V) from the common line potential, and the "1" write bitline potential is obtained by adding 0.3V (± 0.1V) to the common potential, The 0 "write bit line potential is obtained by subtracting 0.3V (± 0.1V) from the common potential, In reading, the word line potential is obtained by adding 0.7 V (± 0.1 V) to the common line potential, and the bit line potential is obtained by adding 0.2 V (± 0.1 V) to the common potential. How Arrays Work The method of manufacturing the thin film memory array of claim 16, Forming a third semiconductor region through selective crystal growth; Oxidizing at least a side of the third semiconductor region formed by selective crystal growth; And Forming a first semiconductor region through selective epitaxial growth. The thin film memory cell of claim 6, wherein the semiconductor thin film is formed on an insulating substrate. The thin film memory cell of claim 6, wherein at least one end of the semiconductor thin film is supported by a substrate. The semiconductor device of claim 6, further comprising: a third gate insulating layer formed on the second main surface at a portion where the semiconductor thin film is interposed between the first semiconductor region and the second semiconductor region; And And a third conductive gate in contact with the third gate insulating film. 39. The thin film memory cell of claim 38 wherein a surface portion of the substrate supporting the semiconductor thin film acts as a third conductive gate. The method of claim 13, wherein the first conductive gate and the second conductive gate are continuous through one cell and extend between adjacent cells in a word direction to form part of a word line. And one of the first channel forming semiconductor thin film portion and the second channel forming semiconductor thin film portion in one cell is spaced apart from that of its adjacent cell. 15. The device of claim 14, wherein the first conductive gate extends continuously between adjacent cells in a word direction and forms part of a word line, And one of the first channel forming semiconductor thin film portion and the second channel forming semiconductor thin film portion in one cell is spaced apart from that of its adjacent cell. The thin film memory array of claim 13, wherein the portion of the common lines is formed from a second continuous semiconductor region extending over adjacent cells. 15. The thin film memory array of claim 14, wherein the portion of the common lines is formed from a contiguous second semiconductor region extending over adjacent cells. The thin film memory array of claim 15, wherein the portion of the common lines is formed from a continuous second semiconductor region extending over adjacent cells. 18. The method of claim 17, wherein the cells are arranged such that the first semiconductor regions and the second semiconductor regions of adjacent cells form a mirror image relationship to form an array, And the first and third semiconductor regions are contiguous from one cell to their adjacent cell in one direction and the second semiconductor region is contiguous from one cell to its adjacent cell in another direction. 41. The method of claim 40, wherein the cells are arranged such that the first semiconductor regions and the second semiconductor regions of adjacent cells form a mirror image relationship to form an array, And the first and third semiconductor regions are contiguous from one cell to their adjacent cell in one direction and the second semiconductor region is contiguous from one cell to its adjacent cell in another direction. 42. The method of claim 41, wherein the cells are arranged such that the first semiconductor regions and the second semiconductor regions of adjacent cells form a mirror image relationship to form an array, And the first and third semiconductor regions are contiguous from one cell to their adjacent cell in one direction and the second semiconductor region is contiguous from one cell to its adjacent cell in another direction. The method of claim 13, The semiconductor thin film is continuous in the word line direction, And the first semiconductor region of one cell is electrically insulated by the third semiconductor region from the first semiconductor region of its adjacent cell. The method of claim 14, The semiconductor thin film is continuous in the word line direction, And the first semiconductor region of one cell is electrically insulated by the third semiconductor region from the first semiconductor region of its adjacent cell. The method of claim 15, The semiconductor thin film is continuous in the word line direction, And the first semiconductor region of one cell is electrically insulated by the third semiconductor region from the first semiconductor region of its adjacent cell. In the erase method applied to the thin film memory cell of claim 6, And a potential is applied to the first semiconductor region in a direction in which carriers of a reverse conductivity type are drawn out to the first semiconductor region. In the erase method applied to the thin film memory cell of claim 6, And a potential is applied to the second semiconductor region in a direction in which carriers of reverse conductivity are drawn out to the second semiconductor region. In the reading method applied to the thin film memory cell of claim 6, The voltage of the first conductive gate with respect to the second semiconductor region is set to a prescribed value exceeding one or both of a first gate threshold voltage and a second gate threshold voltage, and the first semiconductor region and the second A thin film memory cell reading method, characterized in that it is detected to determine stored information whether a current flowing between semiconductor regions is large or small. 24. The method of claim 23, wherein the voltage applied between the first semiconductor region and the second semiconductor region does not exceed a value greater than or equal to an energy gap of the semiconductor thin film which is converted into a voltage. In the method of operation applied to the thin film memory cell of claim 13, When writing, the word line potential is obtained by subtracting 0.4V (± 0.1V) from the common line potential, the write bitline potential is obtained by adding 0.2V (± 0.1V) to the common potential, and the read bitline potential Is a common potential, When erasing, the word line potential is obtained by subtracting 0.5 V (± 0.1 V) from the common line potential, the write bit line potential is the common potential, the read bit line potential is the common potential, When reading, the word line potential is obtained by adding 0.7 V (± 0.1 V) to the common line potential, the write bit line potential is the common potential, and the read bit line potential is 0.3 V (± 0.1 V) to the common potential. A thin film memory cell operating method, which is obtained by adding. An operating method applied to the thin film memory array of claim 15, When writing, the word line potential is obtained by subtracting 0.3V (± 0.1V) from the common line potential, and the "1" write bitline potential is obtained by adding 0.3V (± 0.1V) to the common potential, The 0 "write bit line potential is obtained by subtracting 0.3V (± 0.1V) from the common potential, In reading, the word line potential is obtained by adding 0.7 V (± 0.1 V) to the common line potential, and the bit line potential is obtained by adding 0.2 V (± 0.1 V) to the common potential. How Arrays Work The method of manufacturing the thin film memory array of claim 13, Forming a third semiconductor region through selective crystal growth; Oxidizing at least a side of the third semiconductor region formed by selective crystal growth; And Forming a first semiconductor region through selective epitaxial growth. The method of manufacturing the thin film memory array of claim 14, Forming a third semiconductor region through selective crystal growth; Oxidizing at least a side of the third semiconductor region formed by selective crystal growth; And Forming a first semiconductor region through selective epitaxial growth. The method of manufacturing the thin film memory array of claim 15, Forming a third semiconductor region through selective crystal growth; Oxidizing at least a side of the third semiconductor region formed by selective crystal growth; And Forming a first semiconductor region through selective epitaxial growth. In the method of manufacturing the thin film memory cell of claim 1, Forming a third semiconductor region through selective crystal growth; Oxidizing at least a side of the third semiconductor region formed by selective crystal growth; And Forming a first semiconductor region through selective epitaxial growth. In the method of manufacturing a thin film memory cell of claim 6, Forming a third semiconductor region through selective crystal growth; Oxidizing at least a side of the third semiconductor region formed by selective crystal growth; And Forming a first semiconductor region through selective epitaxial growth.

Images