JP2003303901A - Integrated semiconductor circuit device and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To precise a integrated semiconductor circuit device, such a DRAM, and to improve the performance level of the device. <P>SOLUTION: A horizontal n-channel MISFET is formed in the peripheral circuit region, a silicon oxide film 23 is formed above, then in the memory cell area MA that locates above the film 23, there are formed vertical data transfer MISFETQs having semiconductor poles comprising n-type polycrystalline silicon films 41, undoped polycrystalline silicon films 43, and n-type polycrystalline silicon films 47, where silicon nitride films 46, 42 are formed on the upper and lower sides of the undoped polycrystalline silicon films 43 respectively, silicon oxide films 53 formed on sidewalls of the semiconductor poles are gate insulating films, and n-type polycrystalline silicon films 55, 57 are gate electrodes, and data storage capacitance elements C are formed at the upper part of the n-type polycrystalline silicon films 47. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and its manufacturing technology, and more particularly to a DRAM (Dynami
c Random Access Memory) and other information transfer M
ISFET (Metal Insulator Semiconductor Field Ef
The present invention relates to a technique effectively applied to a semiconductor integrated circuit device having a memory cell in which an effect transistor) and an information storage capacitive element are connected in series.

[0002]

2. Description of the Related Art As described above, a memory cell such as a DRAM has a structure in which an information transfer MISFET and an information storage capacitive element are connected in series.

Semiconductor integrated circuit devices having such memory cells are required to be miniaturized and have improved characteristics, and various studies have been made on these.

For example, Japanese Unexamined Patent Publication (Kokai) No. 5-110019 discloses a semiconductor device in which a MOS structure transistor is a vertical type in order to make each memory cell constituting a DRAM as small as possible.

Further, Japanese Laid-Open Patent Publication No. 11-87541 discloses that leakage current from a memory node can be reduced without deteriorating the read / write time of the memory.
A semiconductor device using a transistor having a charge barrier structure is disclosed.

[0006]

DISCLOSURE OF THE INVENTION The present inventors
He is engaged in research and development of semiconductor integrated circuit devices such as M, and is studying miniaturization and improvement of characteristics.

Although these contents are various and difficult to explain in general, for example, 1) the structure of the MISFET for information transfer which constitutes a memory cell such as DRAM,
It is necessary to study various points such as 2) the structure of the information storage capacitive element, 3) the materials used for them, and 4) the configuration of the circuit (MISFET) necessary for driving the memory cell.

Further, since these elements are involved in a complicated manner, it is necessary to examine the optimum device structure and its manufacturing method while mutually judging each element.

An object of the present invention is to miniaturize or highly integrate a semiconductor integrated circuit device.

Another object of the present invention is to improve the performance of a semiconductor integrated circuit device.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

(1) A semiconductor integrated circuit device of the present invention is a semiconductor integrated circuit device having a memory cell composed of an MISFET for information transfer and a capacitive element, and is an MIS for information transfer.
The FET is a vertical type, and a capacitive element is formed on the vertical MISFET. This vertical MISFET is
A semiconductor pillar having a first semiconductor layer, a second semiconductor layer and a third semiconductor layer formed from below, a boundary between the first semiconductor layer and the second semiconductor layer, and the second semiconductor layer and the third semiconductor layer. A thin insulating film is formed at the boundary between and. Further, this thin insulating film may be formed in the central portion of the second semiconductor layer.

(2) Further, according to the method of manufacturing a semiconductor integrated circuit device of the present invention, a memory cell including a vertical MISFET for information transfer and a capacitive element is formed in a memory cell region of a semiconductor substrate, and a peripheral circuit is formed in the peripheral circuit region. Type horizontal MISF
A method of manufacturing a semiconductor integrated circuit device for forming an ET, comprising: forming a lateral MISFET forming a peripheral circuit in a peripheral circuit region of a semiconductor substrate; forming an insulating film on the semiconductor substrate including an upper portion of the MISFET; A vertical MISFET for information transfer is formed on the top.

(3) Further, in the method for manufacturing a semiconductor integrated circuit device of the present invention, the semiconductor pillar constituting the vertical MISFET for information transfer, wherein the first semiconductor layer, the second semiconductor layer and the third semiconductor layer are After forming a gate insulating film on a sidewall of a semiconductor pillar formed from below, a conductive film covering the gate insulating film is formed to expose a surface of a wiring extending to a lower portion of the semiconductor pillar, and an upper portion thereof is formed. Further, a conductive film is formed.

(4) Further, in the method of manufacturing a semiconductor integrated circuit device of the present invention, a vertical MISFET for information transfer is constituted,
A semiconductor pillar on which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are formed from below is etched in a first direction of a laminated film of these semiconductor layers, and then a second pillar orthogonal to the first direction is formed.
It is formed by etching in the direction. Before the etching in the second direction, if there is a step between the memory cell region where the vertical MISFET for information transfer is formed and the peripheral circuit region, after reducing the step, the second direction Can be etched.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted.

(Embodiment 1) A method of manufacturing a DRAM according to Embodiment 1 of the present invention will be described in the order of steps with reference to FIGS. 1 to 29 are cross-sectional views or plan views of relevant parts of a substrate showing a method for manufacturing a semiconductor integrated circuit device (DRAM) according to an embodiment of the present invention, in which a memory cell of a DRAM is formed. The state of the cell area MA or the peripheral circuit area PA in which MISFETs forming the peripheral circuit are formed is shown.

First, the peripheral circuit area PA of the semiconductor substrate 1
First, the MISFET that forms the peripheral circuit is formed. The process will be described in detail below.

As shown in FIG. 1, a silicon oxide film 2a of about 10 nm, for example, is formed as an insulating film on the semiconductor substrate 1 by thermal oxidation. Next, a silicon nitride film 2b having a thickness of, for example, about 140 nm is further formed on the silicon oxide film 2a as an insulating film by CVD (Chemical Vapor Depositio).
n) Formed by the method.

Then, as shown in FIG. 2, the silicon oxide film 2a and the silicon nitride film 2b in the element isolation region of the peripheral circuit area PA are masked with a photoresist film (not shown) (hereinafter simply referred to as "resist film") as a mask. Remove. That is, the silicon nitride film 2b and the like are left only in the element formation region of the peripheral circuit area PA.

Next, after removing the resist film by ashing, the semiconductor substrate 1 is etched using the silicon nitride film 2b or the like as a mask to form the groove 3. Next, a silicon oxide film having a thickness of about 10 nm is formed on the surface of the groove 3 by thermal oxidation, and the silicon oxide film is removed to remove defects generated during etching. Next, on the silicon nitride film 2b including the inside of the groove 3, a silicon oxide film 5 of, eg, 500 nm is deposited as an insulating film by the CVD method. Then, the silicon oxide film 5 is densified (baked) by annealing (heat treatment) at, for example, 1100 ° C., and then the silicon oxide film 5 outside the groove 3 is subjected to, for example, CMP (Chemical Mechanical Polish).
The silicon oxide film 5 is embedded in the groove 3 by removing the silicon oxide film 5 by the ing) method.

Then, as shown in FIG. 3, after removing the silicon oxide film 2a and the silicon nitride film 2b, a silicon oxide film 2c of, eg, about 5 nm is formed on the surface of the peripheral circuit region PA by thermal oxidation. Then, after p-type impurities such as B (boron) are ion-implanted into the semiconductor substrate 1 in the peripheral circuit area PA, heat treatment is performed to diffuse the impurities to form the p-type well 7. Although not shown, an n-type well may be formed by implanting n-type impurities into the semiconductor substrate 1 in the peripheral circuit area PA (see FIG. 33).

Subsequently, as shown in FIG. 4, the semiconductor substrate 1
After cleaning the surface of the (p-type well 7) with a cleaning solution such as HF (hydrofluoric acid), the semiconductor substrate 1 is thermally oxidized (RTO: rapid th).
The gate insulating film 9 having a thickness of, for example, about 2.5 nm is formed on the surface of the p-type well 7 by ermal oxidation. Next, the gate insulating film 9 is oxynitrided by performing heat treatment at 1050 ° C. in a dinitrogen monoxide (N ₂ O) atmosphere, for example. As described above, by forming the gate insulating film 9 with an oxynitride film, the hot carrier resistance of the gate insulating film can be improved, and the insulation resistance can be improved.

Then, an n-type polycrystalline silicon film (about 70 nm thick) 11 doped with phosphorus (P) or the like as a conductive film on the gate insulating film 9, a WN film (a tungsten nitride film, about 5 nm thick), (Not shown) and a W film (tungsten film, film thickness of about 80 nm) 13 are sequentially deposited, and then, for example, a silicon nitride film (film thickness of about 150 nm) 15 is deposited thereon as an insulating film. Then, the silicon nitride film 15 is etched using a resist film (not shown) as a mask to leave the silicon nitride film 15 in the region where the gate electrode is to be formed. Then, the resist film is removed by ashing, and the n-type polycrystalline silicon film 11, the WN film, and the W film 13 are masked with the silicon nitride film 15.
The gate electrode G1 is formed by etching.

Next, after implanting an n-type impurity such as phosphorus (P) into the p-type well 7 on both sides of the gate electrode G1, the impurity is diffused by heat treatment to form an n ^-- type semiconductor region 17.

Next, a side wall film 19 is formed on the side wall of the gate electrode G1 by depositing, for example, a silicon nitride film as an insulating film on the semiconductor substrate 1 by the CVD method and anisotropically etching it.

Next, using the side wall film 19 and the like as a mask, n-type impurities are implanted into the p-type wells 7 on both sides of the gate electrode G1 and then heat-treated (for example, at 950 ° C. to 1000 ° C.,
For 10 seconds) to diffuse the impurities,
^{A +} type semiconductor region 21 (source / drain region) is formed.

Through the steps so far, the peripheral circuit area PA is
For example, an n-channel type MISFET Qn forming a logic circuit or the like (hereinafter referred to as “peripheral circuit”) necessary for driving a memory cell or the like is formed. This n-channel type M
The ISFET Qn has a so-called lateral transistor structure. In the present embodiment, the n-channel type M
Although the ISFET formation process has been described, an n-type well may be formed in the peripheral circuit region PA and a p-channel type MISFET may be formed on the main surface thereof (see FIG. 33).

Next, a silicon oxide film 23, for example, is deposited as an insulating film on the semiconductor substrate 1 including the n-channel type MISFET Qn by the CVD method, and the upper portion thereof is polished by the CMP method to planarize it.

Then, as shown in FIG. 5, the contact hole C1 is formed by removing the silicon oxide film 23 on the n ⁺ type semiconductor region 21 by etching. Then, for example, a W film is deposited as a conductive film on the silicon oxide film 23 including the inside of the contact hole C1 by a CVD method, and the W film outside the contact hole C1 is removed by, for example, a CMP method to form the plug P1. To do.

Then, the DRA is formed on the memory cell area MA.
The M memory cells are formed, and the steps thereof will be described in detail below.

First, the word line WL connected to the gate electrode of the information transfer MISFET Qs constituting the DRAM memory cell and the bit line BL connected to the source / drain regions are formed. In this embodiment, these lines are embedded wiring. The forming process will be described.

As shown in FIG. 5, a silicon nitride film 25 is formed on the silicon oxide film 23 as an insulating film.

Next, as shown in FIGS. 6 to 8, after depositing, for example, a silicon oxide film 27 as an insulating film on the silicon nitride film 25 by the CVD method, the silicon oxide film 27 is formed.
The wiring groove 29 is formed by selectively removing the silicon nitride film 25 and the silicon nitride film 25. The silicon nitride film 25
Serves as an etching stopper when forming the wiring groove 29.

FIG. 8 is a plan view of an essential part of the substrate in the memory cell area MA. As shown in FIG. 8, a plurality of wiring trenches 29 extend in the X direction and are formed at regular intervals. In the peripheral circuit area PA, it is formed above the plug P1 (see the right part of FIG. 6).

Next, a laminated film (not shown) of a thin Ti (titanium) film and a TiN (titanium nitride) film as a barrier film is formed on the silicon oxide film 27 including the inside of the wiring groove 29.
After depositing, a W film 31 is deposited on top of it as a conductive film. Next, the W film 31 and the like outside the wiring groove 29 are removed by, for example, the CMP method to form the word line WL and the first layer wiring M1 made of the W film 31 and the like.

Therefore, as shown in FIG. 8, a plurality of word lines WL extend in the X direction and are formed at regular intervals. The width WW of the word line WL is, for example, 90 nm,
The width SW between the word lines is 90 nm, for example. In addition,
The left part of FIG. 6 and FIG. 7 are cross-sectional views of the essential part of the substrate in the memory cell area MA. The left part of FIG. 6 is the AA cross section of FIG. 8 and FIG. Corresponds to the B section.

As described above, according to this embodiment, since the word line WL is formed by using the so-called damascene technique, the flatness of the surface of the word line WL and the silicon oxide film 27 can be secured. As a result, the word line WL
Bit line BL formed above and MISFET for information transfer
Photolithography and etching when forming Qs can be performed with high precision. What is photolithography?
This is the process of exposing and developing the resist film.

Then, the silicon oxide film 27 and the word line W are formed.
After depositing, for example, a silicon nitride film 33 as an insulating film on the L and the first layer wiring M1 by the CVD method, a silicon oxide film 35, for example, as an insulating film is deposited on the upper portion thereof by the CVD method.

Then, the silicon oxide film 35 is selectively removed using a resist film (not shown) as a mask to form a wiring groove 37 (FIGS. 9 to 11). The silicon nitride film 33 serves as an etching stopper when the wiring groove 37 is formed. In addition, the silicon nitride film 3
3 functions as an interlayer insulating film between the word line WL and the bit line BL.

FIG. 11 is a plan view of an essential part of the substrate in the memory cell area MA. As shown in FIG.
A plurality are formed extending in the Y direction (direction orthogonal to the X direction) and having a certain interval.

Then, a laminated film (not shown) of a thin Ti (titanium) film and a TiN (titanium nitride) film is formed as a barrier film on the silicon oxide film 35 including the inside of the wiring groove 37.
After depositing, a W film 39 is deposited on the upper part as a conductive film. Next, the W film 39 and the like outside the wiring groove 37 are removed by, for example, the CMP method to form the bit line BL made of the W film 39 and the like.

Therefore, a plurality of bit lines BL extend in the Y direction and are formed at regular intervals (FIG. 11). The width WB of the bit line BL is, for example, 50 nm, and the width SB between the bit lines is, for example, 130 nm.

The left part of FIG. 9 and FIG. 10 are cross-sectional views of the essential part of the substrate of the memory cell area MA. The left part of FIG. 9 is taken along the line AA of FIG. 11 and the left part of FIG. The part is shown in FIG.
10 corresponds to the BB cross section of FIG. 10, and the right part of FIG. 10 corresponds to the CC cross section of FIG. 11 (this relationship is shown in FIG. 12 to FIG. 14, FIG. 15 to FIG. 17, FIG. The same applies to FIGS. 20, 21 and 22, and FIGS. 23 to 25).

As described above, according to the present embodiment, since the bit line BL is formed by using the so-called damascene technique, the flatness of the surface of the bit line BL and the silicon oxide film 35 can be secured. As a result, the bit line BL
It is possible to accurately perform photolithography and etching when forming the information transfer MISFET Qs formed above. Especially, the first pattern PT1 and the second pattern
At the time of forming the pattern PT2, it is necessary to etch a thick film in which a plurality of films are stacked, so that the accuracy of photolithography and etching is important.

Next, on the bit line BL, the information transfer MISFET Qs forming the DRAM memory cell is formed. In this embodiment, this information transfer MISF is used.
ETQs have a vertical transistor structure. Hereinafter, the forming process will be described.

First, as shown in FIGS. 12 to 14, an n-type polycrystalline silicon film (about 200 nm thick) 41 doped with an n-type impurity such as phosphorus (P) is deposited by the CVD method, and then the An extremely thin silicon nitride film 42 of about 1 nm is formed as an insulating film on the upper portion. The silicon nitride film 42 is formed, for example, by nitriding the surface of the n-type polycrystalline silicon film 41.
Heat treatment is performed at 800 ° C. for about 2 minutes in an ammonia (NH ₃ ) atmosphere. Then, on the silicon nitride film 42,
For example, non-doped polycrystalline silicon film (film thickness 400 nm
Degree) 43 by the CVD method, and then, for example, 600 ° C.
Then, heat treatment is performed for about 12 hours. The non-doped polycrystalline silicon film is a polycrystalline silicon film that does not contain impurities or has a lower n-type impurity concentration than the n-type polycrystalline silicon films (41, 47).

Then, on the upper portion of the polycrystalline silicon film 43,
A silicon nitride film 46 of about 1 nm is formed as an insulating film. This silicon nitride film 46 can be formed similarly to the silicon nitride film 42. Then, on the silicon nitride film 46,
For example, an n-type polycrystalline silicon film (film thickness of about 200 nm) 47 doped with an n-type impurity such as phosphorus (P) is deposited by the CVD method.

Then, on the n-type polycrystalline silicon film 47,
After depositing, for example, a silicon oxide film 49 as an insulating film by a CVD method, a silicon nitride film 51, for example, as an insulating film is deposited on the upper portion thereof by a CVD method.

Then, the silicon nitride film 51 and the silicon oxide film 49 are selectively removed using a resist film (not shown) as a mask, and then the n-type polycrystalline silicon film 41, the silicon nitride film 42, and the like are used as masks. The non-doped polycrystalline silicon film 43, the silicon nitride film 46 and the n-type polycrystalline silicon film 47 are etched. As a result, the first pattern PT1 made of these films is formed.

Here, according to the present embodiment, the word line WL and the bit line B below the n-type polycrystalline silicon film 41 are formed.
Since L is formed by using the so-called damascene technique, and the flatness of the upper part thereof is secured, the first pattern P
Photolithography and etching for forming T1 can be performed with high accuracy.

FIG. 14 is a plan view of the main part of the substrate in the memory cell area MA. As shown in FIG.
T1 extends in the Y direction, and a plurality of T1s are formed at regular intervals. The width WP1 of the first pattern PT1 is, for example, 1
00 nm, and the distance SP1 is 80 nm, for example.

Then, the silicon oxide film 35 exposed between the first patterns PT1 is removed by etching (FIG. 1).
2, FIG. 13).

Here, according to the present embodiment, since the width WP1 of the first pattern PT1 is made larger than the width WB of the bit line BL, when the silicon oxide film 35 is etched,
It is possible to prevent the bit line BL from being exposed.
Further, thereafter, the gate electrodes (55, 57) formed between the first patterns PT1 and the bit lines BL can be electrically isolated.

After the etching of the silicon oxide film 35, the silicon nitride film 33 is exposed in the peripheral circuit area PA.

Next, as shown in FIGS. 15 to 17, an insulating film such as 10 to 2 is formed on the side wall of the first pattern PT1.
A silicon oxide film 53 of about 0 nm is formed by thermal oxidation at 800 ° C. The silicon oxide film 53 becomes a gate insulating film of the information transfer MISFET Qs.

Therefore, the silicon oxide film 53 may be formed at least on the side wall of the non-doped polycrystalline silicon film 43 in which the channel is formed.

When the silicon oxide film 53 is formed on the side wall of the first pattern PT1, the n-type polycrystalline silicon film 4 is formed.
The silicon oxide film 53 formed on the sidewalls 1 and 47 is thicker than the silicon oxide film 53 formed on the sidewalls of the non-doped polycrystalline silicon film 43. As described above, by using the non-doped polycrystalline silicon film 43, the silicon oxide film 53 formed on the side wall of the polycrystalline silicon film 43 can be thinly formed, and the channel current (drain current) can be increased. Further, the operating speed of the DRAM can be increased.

Further, since the silicon oxide film 53 on the sidewalls of the n-type polycrystalline silicon films 41 and 47 can be formed thick, the electric field applied from the gate electrode to the drain end can be relaxed, and GIDL ( Gate Induced Drain L
eakage) can be reduced. Therefore, the on / off ratio can be improved and a margin for circuit operation can be secured. In addition, the product yield can be improved. In addition, the refresh characteristic of the memory cell can be improved. Further, since the off-current can be reduced while the on-current of the transistor is secured, it is possible to achieve both high-speed circuit operation and low current consumption.

Here, the word line WL including the W film 31 and the like
Is covered with the silicon nitride film 33 (see the left part of FIG. 13), the silicon oxide film (gate insulating film) 53 is
It is possible to prevent contamination with a metal such as W.

Then, an n-type polycrystalline silicon film 55 doped with, for example, phosphorus (P) is deposited as a conductive film on the first pattern PT1 and the silicon nitride film 33 by the CVD method to a thickness of about 50 nm, and then this film is deposited. By anisotropically etching, the n-type polycrystalline silicon film 55 is left on the side wall of the first pattern PT1. Therefore, the silicon oxide film (gate insulating film) 53 is covered with the n-type polycrystalline silicon film 55.

Next, the surface of the word line WL is exposed by etching the silicon nitride film 33 using the n-type polycrystalline silicon film 55 as a mask (see the left part of FIG. 16). At this time, the silicon oxide film (gate insulating film) 53
Since it is covered with the n-type polycrystalline silicon film 55, it is possible to prevent the silicon oxide film (gate insulating film) 53 from being contaminated by the metal such as W forming the word line WL.

Next, as shown in FIGS. 18 to 20, on the first pattern PT1, the n-type polycrystalline silicon film 55 and the word line WL, an n-type polycrystalline film doped with, for example, phosphorus (P) as a conductive film is formed. The crystalline silicon film 57 is formed by CVD method 1
After depositing about 00 nm, this film is formed into a silicon nitride film 51.
Etch back or polish by CMP method until exposed. As a result, the n-type polycrystalline silicon film 57 is embedded between the first patterns PT1. The n-type polycrystalline silicon films 57 and 55 will be the gate electrodes of the information transfer MISFET Qs. The n-type polycrystalline silicon film 57 has a first
By embedding an n-type polycrystalline silicon film between the patterns PT1, it can be formed in a self-aligned manner.

Here, in the peripheral circuit area PA, the silicon nitride film 33 is exposed, and the memory cell area MA is formed.
First pattern PT1 and n-type polycrystalline silicon film 57 of
There is a step ST between the surface of the silicon nitride film 33 and the surface of the silicon nitride film 33 in the peripheral circuit area PA (see FIG. 18).

Next, as shown in FIGS. 21 and 22, in the memory cell area MA and the peripheral circuit area PA of the semiconductor substrate 1, for example, SOG (Spin On Glas) is used as an insulating film.
s) A film is applied and heat-treated to form a silicon oxide film 59. The SOG film has high fluidity, and the step ST between the memory cell area MA and the peripheral circuit area PA can be filled with high accuracy. Note that the surface of the silicon oxide film 59 may be planarized if necessary. For example, the silicon oxide film 59 is etched back until the surface of the silicon nitride film 51 is exposed. Since the plan view of the main part of the memory cell area MA of the substrate at this time is the same as FIG. 20, its illustration is omitted.

As described above, according to the present embodiment, the step ST between the memory cell region MA and the peripheral circuit region PA is reduced by the silicon oxide film 59, so that the second pattern PT2 described later is formed. Photolithography and etching at that time can be performed accurately.

Next, as shown in FIGS. 23 to 25, the first pattern PT1,
The second pattern PT2 is formed by etching the n-type polycrystalline silicon films 55 and 57 in the X direction. At this time, the n-type polycrystalline silicon films 55 and 57 existing between the bit lines BL are also removed (see the left part of FIG. 23). In the formation of the second pattern PT2, the word line WL
You may use the same mask as the mask used when forming.

Here, since the step ST is reduced by the silicon oxide film 59 and the flatness of the upper portion of the word line WL and the bit line BL is ensured, the photo when the second pattern PT2 is formed. Lithography and etching can be performed accurately.

FIG. 25 is a plan view of an essential part of the substrate in the memory cell area MA. As shown in FIG.
A plurality of T2 extends in the X direction and is formed at regular intervals. The width WP2 of the second pattern PT2 is, for example, 1
00 nm, and the distance SP2 is 80 nm, for example.

The second pattern PT2 has an n-type polycrystalline silicon film 41, a silicon nitride film 42, a non-doped polycrystalline silicon film 43, a silicon nitride film 46 and n.
The silicon pillar 60 is formed of the type polycrystalline silicon film 47. On the side surface of the silicon pillar 60 extending in the Y direction,
The gate insulating film (silicon oxide film 53) is located,
The gate electrode (n-type polycrystalline silicon film 5
5, 57) is located. Also, the silicon pillar 60 is
It is located on the intersection of the word line WL and the bit line BL in the layout (see FIG. 25).

As described above, since the silicon pillar 60 and the gate electrode (n-type polycrystalline silicon films 55 and 57) are formed by one patterning, it is not necessary to consider the misalignment between the silicon pillar 60 and the gate electrode. The memory cell can be miniaturized.

Further, the gate insulating film (silicon oxide film 5
3) is formed only on the two side surfaces extending in the Y direction out of the four side surfaces of the silicon pillar 60. For example, after the silicon pillar 60 is formed, the gate insulating film is formed on the four side surfaces. However, as compared with the case where the gate electrode (word line) is formed, the alignment with the gate electrode can be facilitated. As a result, the manufacturing yield can be improved.

Further, according to the present embodiment, the n-type polycrystalline silicon film 41 and the non-doped polycrystalline silicon film 43.
A silicon nitride film 42 was formed at the boundary between the n-type polycrystalline silicon film 47 and the non-doped polycrystalline silicon film 43 (see FIG. 24).

These films are called diffusion barrier films, and the effective channel length is not shortened by this film, so punch-through can be suppressed and the function of reducing the leak current between the source and drain of the MISFET is provided. ing. A PLED (Phase-state) provided with such an insulating film
Low Electron Number Drive) type transistor,
Leakage current between the source and the drain can be reduced as compared with a normal vertical transistor in which these insulating films are not provided. Therefore, the on / off ratio can be improved. In addition, the refresh characteristics of the DRAM memory cell can be improved. Further, the operation speed of the DRAM can be improved. Further, the characteristics of the semiconductor device can be improved, such as reduction in power consumption.

In addition to the silicon nitride film, for example, a silicon oxide film can be used as the diffusion barrier film. However, in adjusting the band gap, the barrier is smaller in the silicon nitride film and the on-current is increased. Therefore, the silicon nitride film is preferable.

It is also possible to form the silicon pillar 60 by one etching using the mask 60M shown in FIG. However, in this case, the resolution is poor and the resist film cannot be formed accurately. Therefore, in this case, it is necessary to enlarge the pattern corresponding to the silicon pillar in advance, and the occupied area of the memory cell becomes large.

On the other hand, according to the present embodiment, the silicon pillar is formed by etching twice using a line-shaped (PT1, PT2) mask, so that the resist film can be formed accurately. The fine silicon pillar 60 can be formed. Further, a photo margin and a process margin can be secured.

Next, the memory cell region M of the semiconductor substrate 1
A silicon oxide film 61, for example, is deposited as an insulating film on A and the peripheral circuit area PA by a CVD method. The film thickness of the silicon oxide film 61 is set so that the space between the second patterns PT2 can be sufficiently filled. Then, the surface of the silicon oxide film 61 is planarized by polishing by using, for example, the CMP method.

Next, the information storage capacitive element C is formed on the information transfer MISFET Qs.

First, as shown in FIGS. 26 to 28, the second
A silicon oxide film 61 and a silicon nitride film 51 on the n-type polycrystalline silicon film 47 of the pattern PT2 (silicon pillar 60).
The through hole 63 is formed by removing the silicon oxide film 49 and the silicon oxide film 49 (FIG. 27). The n-type polycrystalline silicon film 47, which is the source and drain regions of the information transfer MISFET Qs, is exposed at the bottom of the through hole 63.

Next, a silicon nitride film 65, for example, is deposited as an insulating film on the silicon oxide film 61 including the inside of the through hole 63 by a CVD method.

Then, as shown in FIG. 29, a thick (eg, about 1.5 μm thick) silicon oxide film 67 is deposited on the silicon nitride film 65. The reason why the thickness of the silicon oxide film 67 is increased is to increase the capacitance by increasing the surface area of the hole 69 described later.

Then, the silicon oxide film 67 and the silicon nitride film 65 are etched using a hard mask (not shown) as a mask to form deep holes (recesses) 69. The n-type polycrystalline silicon film 47 is formed on the bottom surface of the deep hole 69.
Is exposed. The silicon nitride film 65 functions as an etching stopper when forming the deep hole 69.

Next, after removing the hard mask, holes 69 are formed.
A WN film (not shown), for example, is deposited as an adhesive layer on the silicon oxide film 67 including the inside by a sputtering method.

Then, a Ru (ruthenium) film 71 is deposited as a conductive film on the WN film by the CVD method. Then, after heat treatment is performed to densify (densify) the Ru film 71, Ru on the surface of the silicon oxide film 67 is removed.
The film 71 is removed. For example, a resist film (not shown) is applied on the Ru film 71, the entire surface is exposed, and then developed to leave the resist film in the holes 69. Then, dry etching is performed using this resist film as a mask, so that the Ru film 7 is formed only on the side wall and the bottom surface of the hole 69.
1 is left.

Then, for example, a thin tantalum oxide (Ta ₂ O ₅ ) film 73 is deposited as a capacitance insulating film by the CVD method inside the hole 69 in which the Ru film 71 is formed and on the silicon oxide film 67. Then, heat treatment (annealing) is performed to crystallize the tantalum oxide.

As described above, according to the present embodiment, the MISF which constitutes the peripheral circuit in the layer lower than the information storage capacitive element C is formed.
Since ET (Qn) is formed (see FIG. 26 and the like), the tantalum oxide film 73 can be used as the capacitive insulating film.

That is, in order to miniaturize the device, it is possible to adopt a so-called trench capacitor structure. However, in this case, after forming the capacitor (capacitance), the MISFET (Qn which forms the peripheral circuit is formed. ) Will be formed. The MISFET formation process includes various heat treatment processes such as a heat treatment for diffusing the impurities forming the source and drain regions (n ⁺ type semiconductor regions 21). When such heat treatment is performed after the tantalum oxide film 73 is formed, the tantalum oxide film 73 is formed.
Film quality is deteriorated, and the Ru film 71, WN film (not shown) and the like under the film are oxidized, resulting in defective insulation characteristics.

Therefore, in the case of the trench capacitor structure, it becomes difficult to use the tantalum oxide film as the capacitance insulating film.

On the other hand, according to the present embodiment, the tantalum oxide film which is a high dielectric film can be used as the capacitance insulating film, and the characteristics of the information storage capacitive element C can be improved.

As the high-dielectric film, aluminum oxide (Al ₂ O ₃ ) film, BST (Ba _X Sr _1-X T) are also used.
There are an iO ₃ ) film, an STO (SrTiO ₃ ) film, and the like, and these films can also be used as a capacitive insulating film.

Needless to say, another insulating film, such as a silicon nitride film, can be used as the capacitive insulating film.

However, as will be described later, in the DRAM memory cell of the present embodiment, when the minimum processing dimension is F, the occupied area can be reduced to 4F ² . In this way, in miniaturized memory cells,
It is necessary to secure a predetermined capacity in a fine area.

In order to secure a predetermined capacitance in such a fine region, it is preferable to use a metal for the lower or upper electrode and a high dielectric film as the capacitance insulating film.

Then, a laminated film 75 of, for example, a Ru film and a W film is formed as a conductive film on the tantalum oxide film 73 by CV.
Deposit by the D method. Then, the laminated film 7 is formed into a desired shape.
5 (Ru film, W film) and the like are etched.

As a result, the lower electrode made of the Ru film 71,
A capacitive insulating film made of tantalum oxide film 73, a W film, and an R film
The information storage capacitive element C constituted by the upper electrode composed of the laminated film 75 with the u film is completed, and the information transfer MISF is completed.
A DRAM memory cell including ETQs and an information storage capacitive element C connected in series with the ETQs is substantially completed.

As described above, in the present embodiment, the information transfer MISFET Qs has the vertical transistor structure, and the information storage capacitive element C is formed on the vertical transistor structure.
The area occupied by the memory cells can be reduced. In addition, high integration of memory cells can be achieved.

For example, the first pattern PT shown in FIG.
The widths of the first and second patterns PT2 are the minimum processing dimensions F, respectively.
Then, a single memory cell can be formed in the 4F ² region. In this case, the width of the bit line BL is
It is necessary to make it equal to or smaller than the minimum processing dimension F. For example, after forming the wiring groove 37 in which the bit line BL is embedded, a side wall made of an insulating film is formed on the side wall thereof.
The width of the bit line BL can be set to F or less.

After that, an interlayer insulating film 77 made of a silicon oxide film or the like is formed on the information storage capacitive element C, and about two layers of wiring are formed on the interlayer insulating film 77, and the uppermost wiring is formed. Although a protective film is formed on the upper part of these, these are not shown.

Although the process of forming the n-channel type MISFET Qn in the peripheral circuit region PA has been described in detail in the present embodiment, it is possible to form the n-channel type MISFET Qn in the peripheral circuit region PA.
Type well is formed, and a p-channel MISF is formed on the main surface.
ET may be formed.

In the step of forming this p-channel type MISFET, the conductivity type of the impurities used is the n-channel type MISFET.
Since it can be formed in the same process as the n-channel type MISFET except that the case is reversed, detailed description thereof will be omitted here. FIG. 33 shows the peripheral circuit area PA.
FIG. 9 shows a cross-sectional view of a main part of the substrate when a p-channel type MISFET Qp is formed in addition to the n-channel type MISFET Qn (the plug in the silicon oxide film 23 and the film above it are omitted).

As shown in FIG. 33, p-channel type MIS
The n-type well 7n in which the FET Qp is formed is isolated from the p-type well 7 through element isolation (silicon oxide film 5).

On the other hand, in the memory cell area MA, element isolation (silicon oxide film 5) is formed on almost the entire surface of the area (see, eg, FIG. 29).

Therefore, it is possible to form a fine memory cell without having to consider a mask shift and a so-called recess phenomenon (a step between the surface of the element isolation and the surface of the semiconductor substrate) when forming the element isolation.

Further, when the information transfer MISFET Qs is of a lateral type and is highly integrated, it is necessary to form element isolations at fine intervals, which causes a problem such as deterioration of the filling characteristics of the isolation trench.

On the other hand, according to the present embodiment, it is possible to accurately form a fine memory cell.

Further, between the word line WL and the semiconductor substrate 1, there is the silicon oxide film 23 as well as the silicon oxide film 5 embedded in the isolation trench 3. The parasitic capacitance generated between the word lines WL can be reduced, and the operation of the memory cell can be speeded up (see FIG. 29).

Further, according to the present embodiment, since the MISFET (Qn) forming the peripheral circuit is formed and then the MISFET Qs for information transfer is formed, the semiconductor integrated circuit device can be formed with high accuracy.

As described above, in this embodiment, since the information transfer MISFET Qs has the vertical transistor structure, a plurality of films (41, 42, 43, 46, 4) are formed.
7) must be laminated (see, for example, FIG. 18). Therefore, after forming the information transfer MISFET Qs having these films, the MISFET (Q
Forming n) causes a step difference between the memory cell area MA and the peripheral circuit area PA. As a result, the accuracy of photolithography and etching when forming the MISFET (Qn) forming the peripheral circuit deteriorates.

Therefore, as in this embodiment, the horizontal M
After forming the ISFET (MISFETQn forming the peripheral circuit), the vertical MISFET (MISF for information transfer)
If ETQs) are formed, photolithography and etching can be performed with high accuracy.

Further, according to the present embodiment, since the information transfer MISFET Qs forming the memory cell is a vertical transistor and the MISFET (Qn) forming the peripheral circuit is a horizontal transistor, a semiconductor integrated circuit device is provided. The characteristics of can be improved.

For example, a MISFET forming a peripheral circuit
(Qn, Qp), like the MISFET for information transfer,
A vertical transistor can be considered, but in this case,
n-channel type MISFET Qn and p-channel type MISF
The process of making different ETQp becomes complicated.

That is, in this case, the semiconductor layer (non-doped polycrystalline silicon film 43) in which the channel is formed is n
In the case of a type, it is sandwiched between semiconductor layers containing n-type impurities,
Further, in the case of p-type, since the structure is sandwiched between semiconductor layers containing p-type impurities, the forming process becomes complicated.

Further, an n-channel type M which constitutes a peripheral circuit
The ISFET Qn and the p-channel type MISFET Qp are required to have various characteristics according to the function of the circuit that constitutes them.
For example, MISFETs having different threshold potentials and different gate insulating film thicknesses are required. For example, the threshold potential can be controlled by the impurity concentration in the region where the channel is formed, but it is difficult to control it in the vertical transistor structure.

When the vertical transistor has a fully depleted type transistor structure, it becomes more difficult to form MISFETs for peripheral circuits having different characteristics. The complete depletion type means a structure in which the semiconductor layer serving as a channel is entirely depleted by the depletion layer extending from the gate electrode.

In the case of such a fully depleted type transistor, in a memory cell which is required to have uniform characteristics, a fully depleted type effect such as good subthreshold characteristic can be obtained. , In the case of MISFET which constitutes a peripheral circuit which requires various characteristics,
Problems such as junction breakdown voltage deterioration due to the parasitic bipolar effect may occur.

Therefore, the characteristics of the semiconductor integrated circuit device can be improved by forming the memory cells with vertical transistors and the peripheral circuits with horizontal transistors.

(Embodiment 2) In Embodiment 1, the silicon nitride films 42 and 46 are formed above and below the non-doped polycrystalline silicon film 43, but silicon nitride is formed in the middle portion of the non-doped polycrystalline silicon film. A film may be formed.

A method of manufacturing the semiconductor integrated circuit device of this embodiment will be described with reference to FIG. The steps other than the step of forming the non-doped polycrystalline silicon film are the same as those in the first embodiment.
Since the process is the same as the process described above, detailed description thereof will be omitted.

As shown in FIG. 30, on the bit line BL,
For example, after depositing an n-type polycrystalline silicon film (having a film thickness of about 200 nm) 41 doped with an n-type impurity such as phosphorus (P) by a CVD method, a non-doped polycrystalline silicon film (having a film thickness of about 200 nm) is formed thereon. ) 43a is deposited by the CVD method and heat treatment (600 ° C., 12 hours) is performed. Then, the surface of the polycrystalline silicon film 43a is nitrided to form a silicon nitride film 45 of about 2 to 3 nm.
This nitriding treatment is performed by, for example, a heat treatment at 800 ° C. for about 5 minutes in an ammonia (NH ₃ ) atmosphere. Further, a non-doped polycrystalline silicon film (film thickness of about 200 nm) 43b is deposited on the silicon nitride film 45 by the CVD method, and heat treatment (600 ° C., 12 hours) is performed. Then, an n-type polycrystalline silicon film (about 200 nm thick) 47 doped with an n-type impurity such as phosphorus (P) is deposited on the upper portion thereof by the CVD method.

After that, the silicon pillar 60, the gate electrode (n-type polycrystalline silicon films 55, 57) and the like are formed through the same steps as those in the first embodiment. Further, an information storage capacitive element (not shown) is formed.

In this case, the silicon nitride film 46 is formed between the non-doped polycrystalline silicon films 43a and 43b. This film is called a shutter barrier film and has the function of reducing the leak current between the source and drain of the PLED type transistor by adjusting the band gap.

In the PLED type transistor provided with such an insulating film, the leak current between the source and the drain can be reduced by about two digits as compared with a normal vertical transistor in which these insulating films are not provided. Therefore, the on / off ratio can be improved. In addition, the refresh characteristics of the DRAM memory cell can be improved. Further, the operation speed of the DRAM can be improved. Further, the characteristics of the semiconductor device can be improved, such as reduction in power consumption.

Further, as shown in FIG. 31, a three-layer silicon nitride film may be provided.

As shown in FIG. 31, for example, an n-type polycrystalline silicon film (about 200 nm thick) 41 doped with an n-type impurity such as phosphorus (P) is deposited by the CVD method, and then an insulating film is formed thereon. As a silicon nitride film 42 of about 1 nm
To form. The silicon nitride film 42 is formed, for example, by nitriding the surface of the n-type polycrystalline silicon film 41, and this nitriding treatment is performed using, for example, ammonia (NH ₃ ).
Heat treatment is performed in an atmosphere at 800 ° C. for about 2 minutes. Next, for example, a non-doped polycrystalline silicon film (a film thickness of about 200 nm) 43a is formed on the silicon nitride film 42 by CVD.
After being deposited by the method, heat treatment (600 ° C., 12 hours) is performed. Then, a silicon nitride film 45 having a thickness of about 2 to 3 nm is formed as an insulating film on the upper portion thereof. The silicon nitride film 45 is formed, for example, by nitriding the surface of the polycrystalline silicon film 43a, and this nitriding treatment is performed by heat treatment at 800 ° C. for about 5 minutes in an ammonia (NH ₃ ) atmosphere, for example. Next, after depositing, for example, a non-doped polycrystalline silicon film (about 200 nm in thickness) 43b on the silicon nitride film 45 by the CVD method, heat treatment (600
(° C, 12 hours).

Then, a silicon nitride film 46 of about 1 nm is formed as an insulating film on the polycrystalline silicon film 43b. The silicon nitride film 46 is the silicon nitride film 4
It can be formed similarly to 2. Then, on the silicon nitride film 46, n-type impurities such as phosphorus (P) are doped.
C-type polycrystalline silicon film (film thickness of about 200 nm) 47
Deposit by method D.

After that, the silicon pillar 60, the gate electrode (n-type polycrystalline silicon films 55, 57) and the like are formed through the same steps as those in the first embodiment. Further, an information storage capacitive element (not shown) is formed.

In this case, a silicon nitride film 46 (shutter barrier film) is formed between the non-doped polycrystalline silicon films 43a and 43b, and the polycrystalline silicon film 43a is also formed.
Silicon nitride films 42 and 46 (diffusion barrier films) are formed on the lower part of the above and the upper part of the polycrystalline silicon film 43b.

Therefore, the effect of the PLED type transistor described above can be obtained.

The step of forming these silicon nitride films is omitted (for example, the silicon nitride film 42 of the first embodiment,
32 is omitted, as shown in FIG. 32, n-type doped with an n-type impurity such as phosphorus (P) is formed above and below the non-doped polycrystalline silicon film (film thickness of about 400 nm) 43, for example. The polycrystalline silicon films (about 200 nm thick) 41 and 47 are located.

In this case, the effect of the PLED type transistor described above cannot be obtained, but it goes without saying that it has the other effects described in the first embodiment.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0134]

The effects obtained by the typical ones of the inventions disclosed in this application will be briefly described as follows.
It is as follows.

A semiconductor integrated circuit device having a memory cell composed of an MISFET for information transfer and a capacitive element, wherein the MISFET for information transfer is constituted by a vertical transistor, and the capacitive element is formed on the vertical transistor.

Further, a thin insulating film is formed on the intermediate portion of the semiconductor layer in which the channel of this vertical transistor is formed or in the upper and lower portions thereof.

As a result, the semiconductor integrated circuit device can be miniaturized or highly integrated. Further, the performance of the semiconductor integrated circuit device can be improved. In addition, the manufacturing yield can be improved.

Further, the MISFET forming the peripheral circuit is of a horizontal type, and this MISFET is used for the information transfer (vertical type).
It is formed before the MISFET.

As a result, miniaturization or higher integration of the semiconductor integrated circuit device can be achieved. Further, the performance of the semiconductor integrated circuit device can be improved. In addition, the manufacturing yield can be improved.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of essential parts of a substrate showing a method for manufacturing a semiconductor integrated circuit device (DRAM) which is Embodiment 1 of the present invention.

FIG. 2 is a sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 3 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 4 is a sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 5 is a sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 6 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 7 is a main-portion cross-sectional view of the substrate showing the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of the present invention;

FIG. 8 is a plan view of a principal portion of the substrate, showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 9 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 10 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 11 is a plan view of a principal portion of the substrate, showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 12 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 13 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 14 is a plan view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 15 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 16 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 17 is a plan view of a principal portion of the substrate, showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 18 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 19 is a main-portion cross-sectional view of the substrate, which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 20 is a plan view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 21 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;

FIG. 22 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention;

FIG. 23 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 24 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 25 is a plan view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 26 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 27 is a main-portion cross-sectional view of the substrate, which shows the manufacturing method of the semiconductor integrated circuit device which is Embodiment 1 of the present invention.

FIG. 28 is a plan view of a principal portion of the substrate, showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 29 is a fragmentary cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device according to the first embodiment of the present invention.

FIG. 30 is a main-portion cross-sectional view of the substrate showing the method of manufacturing the semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 31 is a fragmentary cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 32 is a main-portion cross-sectional view of the substrate showing the method for manufacturing the semiconductor integrated circuit device which is Embodiment 2 of the present invention.

FIG. 33 is a cross-sectional view of the essential part of the substrate, for showing the method for manufacturing the semiconductor integrated circuit device which is the embodiment of the present invention.

FIG. 34 is a diagram showing a method for manufacturing a semiconductor integrated circuit device, for explaining the effect of the embodiment of the present invention.

[Explanation of symbols]

1 semiconductor substrate (substrate) 2a silicon oxide film 2b silicon nitride film 2c silicon oxide film 3 (separation) groove 5 silicon oxide film 7 p-type well 7 n n-type well 9 gate insulating film 11 n-type polycrystalline silicon film 13 W film 15 Silicon nitride film 17 n ⁻ type semiconductor region 17p p ⁻ type semiconductor region 19 Sidewall film 21 n ⁺ type semiconductor region 21p p ⁺ type semiconductor region 23 Silicon oxide film 25 Silicon nitride film 27 Silicon oxide film 29 Wiring groove 31 W film 33 Silicon nitride film 35 Silicon oxide film 37 Wiring trench 39 W film 41 n-type polycrystalline silicon film 42 Silicon nitride film 43 Non-doped polycrystalline silicon film 43a Non-doped polycrystalline silicon film 43b Non-doped polycrystalline silicon film 45 Silicon nitride film 46 Silicon nitride film 47 n-type polycrystalline silicon film 49 silicon oxide film 51 nitriding Recon film 53 Silicon oxide film 55 n-type polycrystalline silicon film 57 n-type polycrystalline silicon film 59 Silicon oxide film 60 Silicon pillar 60M mask 61 Silicon oxide film 63 Through hole 65 Silicon nitride film 67 Silicon oxide film 69 Hole 71 Ru film 73 Tantalum oxide film 75 Laminated film of Ru film and W film 77 Interlayer insulating film BL Bit line C Information storage capacitor C1 Contact hole G1 Gate electrode M1 First layer wiring MA Memory cell region P1 Plug PA Peripheral circuit region PT1 First pattern PT2 Second pattern Qn n-channel type MISFET Qp p-channel type MISFET Qs Information transfer MISFET SB Bit line BL spacing SP1 First pattern spacing SP2 Second pattern spacing ST Step SW Word line WL spacing WB Bit line BL spacing Width WL Word line W P1 width of first pattern WP2 width of second pattern WW width of word line WL

   ─────────────────────────────────────────────────── ─── Continued front page    (72) Inventor Masahiro Moiwa             5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company within Hitachi Semiconductor Group (72) Inventor Kazuo Nakazato             1-280, Higashikoigakubo, Kokubunji, Tokyo             Hitachi, Ltd. Research & Development Division (72) Inventor Teruaki Kisu             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Hideyuki Matsuoka             1-280, Higashikoigakubo, Kokubunji, Tokyo             Central Research Laboratory, Hitachi, Ltd. (72) Inventor Tsuyoshi Tabata             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within (72) Inventor Satoru Haga             5-22-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock             Ceremony Company Hitachi Cho-LS System             Within F term (reference) 5F083 AD01 AD03 AD15 AD31 AD48                       AD49 GA01 GA05 GA09 GA25                       JA04 JA06 JA14 JA39 JA40                       KA01 KA05 MA06 MA19 NA01                       PR06 PR09 PR13 PR15 PR23                       PR29 PR40 ZA04 ZA05 ZA06                       ZA07

Claims (34)

[Claims] 1. A semiconductor integrated circuit device having a memory cell composed of an MISFET for information transfer and a capacitor, wherein the MISFET for information transfer is formed on a semiconductor substrate via a first insulating film. A semiconductor pillar having a first semiconductor layer, a second semiconductor layer and a third semiconductor layer formed from below; (b) a boundary between the first semiconductor layer and the second semiconductor layer; A second insulating film formed on a boundary between the second semiconductor layer and the third semiconductor layer; (c) a gate insulating film formed on a sidewall of the semiconductor pillar; and (d) a gate insulating film formed on a sidewall of the semiconductor pillar. A gate electrode formed via a film, wherein the capacitive element comprises: (e) a first conductive film formed on the third semiconductor layer; and (f) on the first conductive film. A third insulating film formed on the first insulating film, and (g) on the third insulating film. The formed second conductive film,
A semiconductor integrated circuit device comprising: 2. The semiconductor integrated circuit device according to claim 1, wherein the third insulating film is a high dielectric film. 3. The third insulating film is made of tantalum oxide (Ta).
_2. The semiconductor integrated circuit device according to claim 1, which is a ₂ O ₅ ) film. 4. The third insulating film is an aluminum oxide (Al ₂ O ₃ ) film, a BST (Ba _x Sr ₁ -x TiO ₃ ) film or an STO (SrTiO ₃ ) film. 1. The semiconductor integrated circuit device according to 1. 5. The semiconductor integrated circuit device according to claim 1, wherein the second insulating film is a silicon nitride film. 6. The semiconductor integrated circuit device according to claim 1, wherein a fourth insulating film is formed in a central portion of the second semiconductor layer substantially in parallel with the second insulating film. 7. The semiconductor integrated circuit device according to claim 1, wherein the occupied area of the memory cell is 4F ² when the minimum processing dimension is F. 8. The semiconductor integrated circuit device according to claim 1, wherein a wiring electrically connected to the gate electrode is formed in the first insulating film. 9. The semiconductor integrated circuit device according to claim 8, wherein the first insulating film is a laminated film, and the wiring is embedded in a film forming the first insulating film. . 10. The semiconductor integrated circuit device according to claim 1, wherein a wiring electrically connected to the first semiconductor layer is formed in the first insulating film. 11. The first insulating film is a laminated film,
11. The semiconductor integrated circuit device according to claim 10, wherein the wiring is embedded in a film forming the first insulating film. 12. The first insulating film in the first insulating film,
2. The semiconductor integrated circuit device according to claim 1, wherein a wiring is formed under the semiconductor layer, and the width of the wiring is smaller than the width of the semiconductor pillar in the width direction of the wiring. 13. A first wiring and a second wiring electrically separated from the first wiring are formed in the first insulating film, and the first wiring is electrically connected to the gate electrode. 2. The semiconductor integrated circuit device according to claim 1, wherein the second wiring is electrically connected to the first semiconductor layer and extends in a direction orthogonal to the first wiring. 14. The semiconductor integrated circuit device according to claim 13, wherein the second wiring is located in a layer above the first wiring. 15. The semiconductor integrated circuit device according to claim 13, wherein the width of the second wiring is smaller than the width of the first wiring. 16. The first wiring in the first insulating film,
A second wiring that is electrically separated from the first wiring and extends in a direction orthogonal to the first wiring is formed, and the semiconductor pillar has a pattern of each of the first wiring and the second wiring. 2. It is located on the intersection.
The semiconductor integrated circuit device described. 17. The semiconductor integrated circuit device according to claim 16, wherein the second wiring is located above the first wiring, and the semiconductor pillar is located above the second wiring. 18. A semiconductor integrated circuit device having a memory cell composed of an MISFET for information transfer and a capacitive element, wherein the MISFET for information transfer is formed on a semiconductor substrate via a first insulating film. A semiconductor pillar, in which a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer are formed from below, and (b) a second insulating film formed in the central portion of the second semiconductor layer. (C) a gate insulating film on the sidewall of the semiconductor pillar, and (d) a gate electrode formed on the sidewall of the semiconductor pillar with the gate insulating film interposed therebetween. A first conductive film formed on the third semiconductor layer, (f) a third insulating film formed on the first conductive film, (g) formed on the third insulating film A second conductive film,
A semiconductor integrated circuit device comprising: 19. A MISFET for forming a peripheral circuit in a peripheral circuit region, the memory cell having a memory cell including an MISFET for information transfer and a capacitive element in a memory cell region of a semiconductor substrate.
The information transfer MISFET includes: (a) a semiconductor pillar formed on a semiconductor substrate via a first insulating film, the first semiconductor layer, the second semiconductor layer, and A semiconductor pillar having a third semiconductor layer formed from below; (b) a semiconductor pillar formed at a boundary between the first semiconductor layer and the second semiconductor layer and at a boundary between the second semiconductor layer and the third semiconductor layer; 2 insulating film, (c) a first gate insulating film formed on the sidewall of the semiconductor pillar, and (d) a first gate electrode formed on the sidewall of the semiconductor pillar via the gate insulating film. And (e) a first conductive film formed on the third semiconductor layer, (f) a third insulating film formed on the first conductive film, and (g) ) A second conductive film formed on the third insulating film,
And a second gate insulating film formed on the semiconductor substrate, and (i) a second gate electrode formed on the second gate insulating film. And (j) a semiconductor region formed on both sides of the second gate electrode, the semiconductor integrated circuit device. 20. A MISFET that constitutes the peripheral circuit
Is an n-channel MISFET and a p-channel MI
20. The semiconductor integrated circuit device according to claim 19, wherein the semiconductor integrated circuit device is a complementary MISFET having an SFET. 21. The peripheral circuit region is an element region partitioned by an isolation region formed in a semiconductor substrate, and has a plurality of element regions in which MISFETs constituting the peripheral circuit are formed. 20. The semiconductor integrated circuit device according to claim 19, wherein an element region defined by an isolation region formed in the semiconductor substrate is not formed in the semiconductor substrate in the cell region. 22. A MISFET that constitutes the peripheral circuit
Is formed in an element region defined by a fourth insulating film embedded in the groove in the semiconductor substrate, and the memory cell is formed by a fourth insulating film embedded in the groove in the semiconductor substrate and an upper portion thereof. 20. The semiconductor integrated circuit device according to claim 19, wherein the semiconductor integrated circuit device is formed on the fifth insulating film. 23. A lateral MIS forming a memory cell composed of a vertical MISFET for information transfer and a capacitive element in a memory cell region of a semiconductor substrate and forming a peripheral circuit in a peripheral circuit region.
A method of manufacturing a semiconductor integrated circuit device for forming a FET, comprising: (a) forming a lateral MISFET forming a peripheral circuit in a peripheral circuit region of a semiconductor substrate; and (b) after the step (a), A step of forming a first insulating film on a semiconductor substrate including an upper part of the MISFET, and (c) a vertical MISFET for information transfer on the first insulating film.
A semiconductor pillar having a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer formed from below, a gate insulating film formed on a sidewall of the semiconductor pillar, and the gate on a sidewall of the semiconductor pillar. A step of forming a vertical MISFET for information transfer having a gate electrode formed via an insulating film; and (d) a step of forming a capacitive element on the third semiconductor layer of the vertical MISFET for information transfer. A method of manufacturing a semiconductor integrated circuit device, comprising: 24. A second insulating film is formed on the boundary between the first semiconductor layer and the second semiconductor layer and the boundary between the second semiconductor layer and the third semiconductor layer of the vertical MISFET for information transfer. 24. The method of manufacturing a semiconductor integrated circuit device according to claim 23. 25. The method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein a second insulating film is formed in the central portion of the second semiconductor layer of the information transfer vertical MISFET. 26. The method of manufacturing a semiconductor integrated circuit device according to claim 23, wherein the surface of the first insulating film is planarized. 27. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a memory cell composed of an MISFET for information transfer and a capacitive element in a memory cell region of a semiconductor substrate, comprising: (a) a first insulating film above the semiconductor substrate. Forming a first wiring and a second wiring that extend in a direction orthogonal to each other through (b) a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on the second wiring. Forming a first pattern extending in the same direction as the second wiring by sequentially depositing and selectively removing these laminated films; and (c) a gate insulating film on a sidewall of the first pattern. And (d) a step of forming a first conductive film on the sidewall of the first pattern via the gate insulating film, and (e) a step between the first patterns after the step (d). By etching the first distribution A step of exposing a surface of the semiconductor integrated circuit device, and (f) a step of forming a second conductive film between the first patterns after the step (e). Method. 28. The method of manufacturing a semiconductor integrated circuit device according to claim 27, wherein the first wiring is made of a metal film. 29. The method of manufacturing a semiconductor integrated circuit device further comprises: (g) selectively removing the first pattern, the gate insulating film, and the first and second conductive films after the step (f). 28. The method for manufacturing a semiconductor integrated circuit device according to claim 27, further comprising the step of forming a second pattern extending in the same direction as the first wiring by removing the second pattern. 30. A method of manufacturing a semiconductor integrated circuit device, comprising: forming a memory cell composed of an MISFET for information transfer and a capacitive element in a memory cell region of a semiconductor substrate, comprising: (a) a first insulating film above a semiconductor substrate. Forming a first wiring and a second wiring that extend in a direction orthogonal to each other through (b) a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on the second wiring. Forming a first pattern extending in the same direction as the second wiring by sequentially depositing and selectively removing these laminated films; and (c) a gate insulating film on a sidewall of the first pattern. And (d) forming a first conductive film between the first patterns, and (e) selectively removing the first pattern, the gate insulating film and the first conductive film. The same wiring as the first wiring The method of manufacturing a semiconductor integrated circuit device characterized by comprising the step, of forming a second pattern extending in. 31. A second insulating film is formed at a boundary between the first semiconductor layer and the second semiconductor layer and a boundary between the second semiconductor layer and the third semiconductor layer of the information transfer MISFET. 31. The method of manufacturing a semiconductor integrated circuit device according to claim 30. 32. The method of manufacturing a semiconductor integrated circuit device according to claim 30, wherein a second insulating film is formed in a central portion of the second semiconductor layer of the information transfer MISFET. 33. A method of manufacturing a semiconductor integrated circuit device, comprising forming a memory cell including an information transfer MISFET and a capacitive element in a memory cell region of a semiconductor substrate and forming a MISFET forming a peripheral circuit in a peripheral circuit region. (A) a step of forming a MISFET forming a peripheral circuit in a peripheral circuit region of the semiconductor substrate, and (b) a first step on the semiconductor substrate including the MISFET upper part.
A step of forming an insulating film, and (c) sequentially depositing a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer on the first insulating film, and selectively removing these laminated films, A step of forming a pattern extending in a first direction, (d) a step of forming a gate insulating film on a sidewall of the pattern extending in the first direction, and (e) a step of (d), Filling a conductive film between the patterns; and (f) forming a second insulating film in the peripheral circuit region to reduce the difference between the surface of the memory cell region and the surface of the peripheral circuit region. And (g) etching the pattern in a second direction to form a semiconductor pillar composed of the first semiconductor layer, the second semiconductor layer, and the third semiconductor layer. Method of manufacturing circuit device. 34. A method of manufacturing a semiconductor integrated circuit device, comprising forming a memory cell composed of an MISFET for information transfer and a capacitive element in a memory cell region of a semiconductor substrate, and forming a MISFET constituting a peripheral circuit in a peripheral circuit region. (A) a step of forming a MISFET forming a peripheral circuit in a peripheral circuit region of the semiconductor substrate, and (b) a first step on the semiconductor substrate including the MISFET upper part.
Forming an insulating film, (c) forming a second insulating film on the first insulating film, and (d) extending in the first direction by selectively removing the second insulating film. Forming a wiring groove for forming the first wiring by forming a metal film in the wiring groove, (e) forming a third insulating film on the first wiring, and (f) Forming a fourth insulating film on the third insulating film, and (g) forming a wiring groove extending in a second direction orthogonal to the first direction by selectively removing the fourth insulating film. After the formation, a step of forming a second wiring by embedding a metal film in the wiring groove, and (h) a first semiconductor layer, a second semiconductor layer and a third semiconductor layer are sequentially formed on the second wiring. By depositing and selectively removing these laminated films, a pattern extending in the second direction is formed. And (i) forming a gate insulating film on a side wall of the first pattern extending in the second direction, and (j) forming a gate insulating film on a side wall of the first pattern extending in the second direction. Forming a first conductive film via a film; (k) using the first conductive film as a mask, the fourth and third films
Exposing the first wiring by removing an insulating film; (l) embedding a second conductive film between the first patterns after the step (k); A second pattern extending in the first direction by selectively removing the first pattern, the gate insulating film, and the first and second conductive films, the first pillar, the silicon pillar, and the second pillar of the silicon pillar. Forming a second pattern composed of a sidewall gate insulating film and a gate electrode extending in two directions; (n) forming a fifth insulating film between the second patterns; and (o) the third semiconductor. And a step of forming a capacitive element on the layer, the method for manufacturing a semiconductor integrated circuit device.