KR100897281B1 - Column Address Control Circuit of Semiconductor Memory Apparatus - Google Patents

Abstract

According to an embodiment of the present invention, an input, a storage operation, and an output operation are divided in response to a column enable signal, and the column address is received and stored during the disable period of the column enable signal, And a column address latch portion for outputting the column address as an internal column address.

Column Address, Column Enable Signal, Latch

Description

Column address control circuit of semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a column address control circuit.

A semiconductor memory device having a general column address control circuit includes a first control circuit 10, a second control circuit 20, and a decoding unit 30, as shown in FIG. 1. Hereinafter, the first column address CA1 is a signal obtained by pre-decoding the column addresses 2 to 4 and indicates a signal under the control of the column enable signal YAE. In addition, the second column address CA2 indicates a signal obtained by precoding the column addresses from 5 to 9.

The first control circuit 10 outputs the first column address CA1 as a first internal column address CA1_int during the enable period of the column enable signal YAE.

The first control circuit 10 includes a first NAND gate ND1 and a first inverter IV1. The first NAND gate ND1 receives the column enable signal YAE and the first column address CA1. The first inverter IV1 receives the output signal of the first NAND gate ND1 and outputs the first internal column address CA1_int.

The second control circuit 20 drives the second column address CA2 and outputs the second internal column address CA2_int. The second control circuit 20 includes second and third inverters IV2, IV3. The second inverter IV2 receives the second column address CA2. The third inverter IV3 receives the output signal of the second inverter IV2 and outputs the second internal column address CA2_int.

The decoding unit 30 decodes the first and second internal column addresses CA1_int and CA2_int to generate a column selection signal YS <i>.

The semiconductor memory device including the column address control circuit configured as described above operates as shown in FIG. 2.

After the read command Read is input to the semiconductor memory device, the column enable signal YAY is enabled high.

The first control circuit 10 receives the first column address CA1 and the column enable signal YAE and corresponds to the address 1 of the first column address CA1 and the column enable signal. The first internal column address CA1_int having the same enable period as the enable period of (YAE) is generated.

The second control circuit 20 drives the second column address CA2 to generate the second internal column address CA2_int corresponding to the address 2 of the second column address CA2.

The decoding unit 30 decodes the first internal column address CA1_int and the second internal column address CA2_int to address (1) and the second column address CA2 of the first column address CA1. Generates the column selection signal YS <i> corresponding to the address (1). In this case, the enable period of the column select signal YS <i> is the same as the enable period of the column enable signal YAE. The same is true when generating the column selection signal YS <i> corresponding to the address 2 of the first column address CA1 and the address 2 of the second column address CA2. 2 shows a normal operation of a semiconductor memory device having a general column address control circuit.

In the semiconductor memory device, an active signal is enabled after a read command is input. The active signal is enabled and the column enable signal YAE is enabled after a predetermined time. In this case, until the active signal is enabled and the column enable signal (YAE) is enabled, it is referred to as RAS to CAS Delay and is represented by tRCD.

As the operation power supply voltage level of the semiconductor memory device is lowered, the voltage level stored in the cell is lowered, and the voltage level used in the bit line sense amplifier is also lowered, thereby increasing tRCD. Therefore, in designing a semiconductor memory device, a compensation circuit is added to compensate for the tRCD characteristic. One of them is to internally delay the enable timing of the column select signal YS <i> in read or write operations, thereby increasing the time for which the potential levels of the bit lines and bit line bars are amplified. There is a way to make it happen. However, the method of delaying the column select signal YS <i> has a limitation in the delay time.

For example, as shown in FIG. 3, a read command is input every two cycles of the clock CLK, and first and second column addresses CA1 and CA2 are changed every two cycles of the clock CLK. . When the column enable signal YAE is delayed to generate the column select signal YS <i>, the first and second column addresses are between the enable and disable timing of the delayed column enable signal YAE. (CA1, CA2) changes. As a result, the column select signal YS <i> corresponding to the address 1 of the first and second column addresses CA1 and CA2 is generated, and the first and second column addresses CA2 are immediately generated. The column select signal YS <i> corresponding to the address (2) of Δ) is also generated.

As shown in FIG. 2, in order for the semiconductor memory device to perform a normal operation, the enable period of the column enable signal YAE and the enable period of the column select signal YS <i> must be the same. . In addition, when the column select signal YS <i> is enabled and disabled once, the corresponding column select signal YS <i> should not change. However, as shown in FIG. 3, when the address corresponding to the enable and disable timing of the column select signal YS <i> is different, the column select signal YS <i> corresponding to the address 1 is different. ) Is shorter than the enable period of the column enable signal YAE, which may cause abnormal read operation, and is immediately output after the column select signal YS <i> corresponding to the address (1). The semiconductor memory device may not perform a normal read operation due to the column selection signal YS <i> corresponding to the address 2.

The present invention provides a column address control circuit of a semiconductor memory device capable of performing a normal read or write operation in delaying a column enable signal due to an increase in tRCD, but without limiting the delay time of the column enable signal. The purpose is.

The column address control circuit of the semiconductor memory device according to an exemplary embodiment of the present invention classifies an input and a storage operation and an output operation in response to a column enable signal, and receives and stores a column address during a disable period of the column enable signal. And a column address latch unit configured to output the column address stored during the enable period of the column enable signal as an internal column address.

The column address control circuit of the semiconductor memory device according to an embodiment of the present invention may perform a normal read or write operation even if the delay time of the column enable signal is increased to compensate for an increase in tRCD. There is an effect that can increase the operation reliability.

The column address control circuit of the semiconductor memory device according to the embodiment of the present invention includes a first column address latch unit 100 and a second column address latch unit 200 as shown in FIG. 4.

The first column address latch unit 100 includes a first inverter IV11, a first input unit 110, a first latch unit 120, a first output unit 130, and an initialization unit 140. .

The first inverter IV11 inverts and outputs the column enable signal YAE.

When the column enable signal YAE is low, the first input unit 110 inverts the first column address CA1 and outputs the inverted first column address CA1 to the first latch unit 120.

The first input unit 110 receives the column enable signal YAE at a first control terminal, receives an output signal of the first inverter IV11 at a second control terminal, and inputs the first column address at the input terminal. It may include a first control inverter (IVC11) receiving the CA1).

The first latch unit 120 stores the output signal of the first input unit 110.

The first latch unit 120 may include second and third inverters IV12 and IV13. The second inverter IV12 inverts the output signal of the first input unit 110 and outputs the inverted signal to the first output unit 130. The third inverter IV13 inverts the output signal of the second inverter IV12 and inputs it to the second inverter IV12 again.

The first output unit 130 outputs the output signal of the first latch unit 120 as a first internal column address CA1_int when the column enable signal YAE is enabled high.

The first output unit 130 may include a pass gate PG11 that outputs the first internal column address CA1_int when the column enable signal YAE is enabled high. The pass gate PG11 receives the column enable signal YAE at the first control terminal, receives the output signal of the first inverter IV11 at the second control terminal, and receives the first latch unit at the input terminal. The output signal of 120) is input.

The initialization unit 140 initializes the first internal column address CA1_int to a low level when the column enable signal YAE is disabled low.

The initialization unit 140 may include a transistor N11 that connects an output node of the first output unit 130 to a ground terminal VSS when the column address YAE is disabled as a switching element. have. The transistor N11 has a gate connected to an output signal of the first inverter IV11, a drain connected to an output node of the first output unit 130, and a source connected to a ground terminal VSS.

The second column address latch unit 200 may connect the fourth inverter IV14, the second input unit 210, the second latch unit 220, the second output unit 230, and the third latch unit 240. Include.

The fourth inverter IV14 inverts and outputs the column enable signal YAE.

When the column enable signal YAE is low, the second input unit 210 inverts the second column address CA2 and outputs the inverted second column address CA2 to the second latch unit 220.

The second input unit 210 receives the column enable signal YAE at a first control terminal, receives an output signal of the fourth inverter IV14 at a second control terminal, and inputs the second column address at the input terminal. It may include a second control inverter (IVC12) receiving the CA2).

The second latch unit 220 stores the output signal of the second input unit 210.

The second latch unit 220 may include fifth and sixth inverters IV15 and IV16. The fifth inverter IV15 inverts the output signal of the second input unit 210 and outputs the inverted signal to the second output unit 230. The sixth inverter IV16 inverts the output signal of the fifth inverter IV15 and inputs it to the fifth inverter IV15 again.

When the column enable signal YAE is enabled high, the second output unit 230 inverts the output signal of the second latch unit 220 and outputs the inverted output signal to the third latch unit 240.

The second output unit 230 may include a third control interleaver IVC13 that inverts and outputs an output signal of the second latch unit 220 when the column enable signal YAE is enabled high. Can be. The third control inverter IVC13 receives the column enable signal YAE at the first control terminal, receives the output signal of the fourth inverter IV14 at the second control terminal, and the second latch unit at the input terminal. The output signal of 220 is received.

The third latch unit 240 inverts the output signal of the second output unit 230 and outputs the second internal column address CA2_int.

The third latch unit 240 includes seventh and eighth inverters IV17 and IV18. The seventh inverter IV17 inverts the output signal of the second output unit 230 and outputs the second internal column address CA2_int. The eighth inverter IV18 inverts the output signal of the seventh inverter IV17 and inputs it to the seventh inverter IV17 again.

5 illustrates a column address control circuit of a semiconductor memory device according to another embodiment of the present invention. At this time, the first column address latch unit 100-1 and the second column address latch unit 200-1 shown in FIG. 5 are disabled when the column enable signal YAE is low to reduce power consumption. Is configured to store only the first and second column addresses CA1 and CA2.

Like the first column address latch unit 100 of FIG. 4, the first column address latch unit 100-1 of FIG. 5 may include a first input unit 110, a first output unit 130, and an initialization unit 140. ) Are the same but differ only in the configuration of the first latch unit 120-1 and only the first latch unit 120-1 will be described.

The first latch unit 120-1 of FIG. 5 is configured as a fourth control inverter IVC14 instead of the third inverter IV13 of the first latch unit 120 of FIG. 4. The fourth control inverter IVC14 receives the inverted column enable signal YAE at the first control terminal, receives the column enable signal YAE at the second control terminal, and controls the input terminal and the output terminal. 3 Connected in the same manner as inverter IV13.

The second column address latch unit 200-1 of FIG. 5 and the second column address latch unit 200 of FIG. 4 also have other configurations (the second input unit 210, the second output unit 230, and the third latch unit). 240 are the same, but only the second latch portion 220-1 is different. Therefore, only the second latch unit 220-1 will be described.

The second latch unit 220-1 of FIG. 5 is configured as the fifth control inverter IVC15 instead of the sixth inverter IV16 of the second latch unit 220 of FIG. 4. The fifth control inverter IVC15 receives the column enable signal YAE inverted at a first control terminal and is controlled by receiving the column enable signal YAE at a second control terminal. The same connection as the sixth inverter IV16 is performed.

The first latch unit 120-1 and the second latch unit 220-1 shown in FIG. 5 may be configured to provide the first and second column addresses CA1 only when the column enable signal YAE is disabled. , CA2). Therefore, the first latch unit 120-1 and the second latch unit 220-1 may reduce power consumption than power consumed by the first and second latch units 120 and 220 of FIG. 4. .

The operation of the column address control circuit of the semiconductor memory device according to the embodiment of the present invention configured as described above will be described with reference to FIG. 6.

The column address control circuit according to the embodiment of the present invention is configured to store and output the first and second column addresses CA1 and CA2 when the column enable signal YAE is enabled.

In the first column address latch unit 100 of FIG. 4, the column enable signal YAE is disabled from the first column address CA1 when the column enable signal YAE is enabled. And output as the first internal column address CA1_int. Meanwhile, the second column address latch unit 200 of FIG. 4 may convert the second column address CA2 of the column enable signal YAE when the column enable signal YAE is enabled. And output as the second internal column address CA2_int for one period.

Therefore, as compared with the general column address control circuit performing the abnormal operation illustrated in FIG. 3, the first and second internal column addresses CA1_int and CA2_int may generate a normal column selection signal YS <i>. So that it is output. That is, in the semiconductor memory device having the column address control circuit according to the present invention, the column selection signals corresponding to the first and second column addresses CA1 and CA2 when the column enable signal YAE is enabled. (YS <i>) may be output in the enable period of the column enable signal YAE. Therefore, when the column enable signal YS <i> is generated by delaying the column enable signal YAE as tRCD increases in the low-power semiconductor memory, the delay time of the column enable signal YAE is limited. By overcoming the above, there is an effect of increasing the operational reliability of the semiconductor memory device.

As those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features, the embodiments described above should be understood as illustrative and not restrictive in all aspects. Should be. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

1 is a circuit diagram of a column address control circuit of a semiconductor memory device according to the prior art;

2 is a timing diagram of a normal column address control circuit according to FIG. 1;

3 is a timing diagram of an abnormal column address control circuit according to FIG. 1;

4 is a circuit diagram of a column address control circuit of a semiconductor memory device according to an embodiment of the present invention;

5 is a circuit diagram of a column address control circuit of a semiconductor memory device according to another embodiment of the present invention;

6 is a timing diagram of a semiconductor memory device having a column address control circuit according to the present invention.

<Description of the symbols for the main parts of the drawings>

100: first column address latch portion 200: second column address latch portion

Claims (15)

In response to the column enable signal, an input, a storage operation, and an output operation are divided, and a column address is received and stored during the disable period of the column enable signal, and the column address stored during the enable period of the column enable signal is stored. A column address latch portion for outputting as an internal column address, The column address includes a first column address and a second column address, the internal column address includes a first internal column address, and a second internal column address, The column address latch unit stores the first column address during the disable period of the column enable signal and outputs the stored first column address as the first internal column address when the column enable signal is enabled. One column address latch, and The second column address latch unit configured to store the second column address during the disable period of the column enable signal and to output the stored second column address as the second internal column address when the column enable signal is enabled; And a column address control circuit of the semiconductor memory device. delete The method of claim 1, The first column address latch unit And initialize the first internal column address when the column enable signal is disabled. The method of claim 3, wherein The first column address latch unit An input unit configured to receive the first column address in response to the column enable signal; A latch unit for storing an output signal of the input unit; An output unit configured to output an output signal of the latch unit as the first internal column address in response to the column enable signal; And an initialization unit configured to initialize the first internal column address in response to the column enable signal. The method of claim 4, wherein The input unit And a switching device configured to transfer the first column address to the latch unit when the column enable signal is disabled. The method of claim 4, wherein The latch portion And storing an output signal of the input unit only when the column enable signal is enabled. The method of claim 6, The latch portion An inverter for inverting and outputting an output signal of the input unit; And a control inverter for inverting the output signal of the inverter and outputting the inverted signal as an input signal of the inverter when the column enable signal is enabled. The method of claim 4, wherein The output unit And a switching device configured to output an output signal of the latch unit as the first internal column address when the column enable signal is enabled. The method of claim 4, wherein The initialization unit And a switching device for connecting the output node of the output unit to a ground terminal when the column enable signal is disabled. The method of claim 1, The second column address latch unit An input unit configured to receive the second column address in response to the column enable signal; A first latch unit for storing an output signal of the input unit; An output unit configured to output an output signal of the first latch unit as the second internal column address in response to the column enable signal; And a second latch unit configured to store the second internal column address. The method of claim 10, The input unit And a switching device configured to transfer the second column address to the first latch part when the column enable signal is disabled. The method of claim 10, The latch portion And storing an output signal of the input unit only when the column enable signal is enabled. The method of claim 12, The latch portion An inverter for inverting and outputting an output signal of the input unit; And a control inverter for inverting the output signal of the inverter and outputting the inverted signal as an input signal of the inverter when the column enable signal is enabled. The method of claim 10, The output unit And a switching device configured to output an output signal of the first latch unit as the second internal column address when the column enable signal is enabled. The method of claim 14, The second latch portion And maintain the potential level of the second internal column address even when the switching element is turned off.

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