JP2002246891A - Input buffer circuit and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an input buffer circuit and a semiconductor device capable of properly fetching a signal. SOLUTION: A control circuit 300 for switching a signal to be inputted to an SSTL input buffer circuit 800 is connected to an SSTL input buffer circuit 800 so that an inside clock enable signal int.CKE being an output signal can be properly controlled, and that the malfunction of the circuit can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input buffer circuit and a semiconductor device, and more particularly to a signal control configuration at power-on.

[0002]

2. Description of the Related Art With the speeding up of microprocessors, higher-speed data transfer using higher frequencies is required in data transfer between LSI chips. However, the TTL which is the input / output level of the conventional LSI is
At the (Transistor Transistor Logic) level or the CMOS level, the influence of signal reflection and the influence of crosstalk become high when the signal frequency exceeds 50 MHz, and normal data transfer becomes difficult.

In order to address these problems, SDRA
High-speed small-amplitude interface standard SSTL (Stub Series Terminated Logi) for M (synchronous dynamic random access memory (especially double data rate DDR-SDRAM))
c) is proposed, and this standard is based on JEDEC (Joint Electron
It has been recognized as an industry standard by Device Engineering (US Electronic Standards Committee).

FIG. 16 is a block diagram of a conventional CMOS input buffer circuit 600. CMOS input buffer circuit 600 receives external clock enable signal ext. C
KE and enable signal enable, and receives internal clock enable signal int. Outputs CKE.

FIG. 17 shows an example of a conventional CMOS input buffer circuit 600. CMOS input buffer circuit 6
00 is an external clock enable signal ext. NAND circuit 90 receiving CKE and enable signal enable and inverter 91 are included.

The NAND circuit 90 has an enable signal enab
If le is ignored, it functions as an inverter.

Inverter 91 receives an output signal of NAND circuit 90 and receives an internal clock enable signal int.
Outputs CKE.

FIG. 18 shows a CMOS input buffer circuit 60.
6 is a timing chart for explaining the operation of the "0".

When the enable signal enable is "H", the external clock enable signal ext. If the level of CKE is high, the internal clock enable signal int. CKE becomes "H". On the other hand, the external clock enable signal ext. If the level of CKE is low,
Internal clock enable signal int. CKE is “L”
Becomes

FIG. 19 is a block diagram of an SSTL input buffer circuit 800 which is a high-speed interface.

SSTL input buffer circuit 800 receives an external clock enable signal ext. CKE, enable signal enable and external reference voltage ext. Vref (hereinafter, Vr
ef. ) In response to the internal clock enable signal int. Outputs CKE.

FIG. 20 shows an SSTL input buffer circuit 80.
0 is an example. As shown in FIG. 20, the SSTL input buffer circuit 800 includes P-channel MOS transistors PT1, PT2 and PT3, and an N-channel M transistor.
OS transistors NT1, NT2 and NT3, and an inverter 10 are included.

As shown in FIG. 20, a P-channel MOS transistor PT1 and an N-channel MOS transistor N
T1 is the external power supply voltage ext. Vdd (hereinafter, Vdd
And ) And the node N6. P-channel MOS transistor PT2 and N-channel MOS transistor NT2 are connected in series between power supply voltage Vdd and node N6.

Gate electrode of P-channel MOS transistor PT1 and P-channel MOS transistor PT
The two gate electrodes are both connected to a connection node (referred to as a node X1) between the P-channel MOS transistor PT1 and the N-channel MOS transistor NT1.

The gate electrode of N-channel MOS transistor NT1 is connected to node N1 and has a reference voltage Vre.
Receive f. The gate electrode of N-channel MOS transistor NT2 is connected to node N7, and receives an external clock enable signal ext. Receive CKE.

N channel type MOS transistor NT3
Is connected between node N6 and the ground potential. N-channel MOS transistor NT3 receives an enable signal enable at a gate electrode.

P channel type MOS transistor PT2 and N channel type MOS transistor NT2 are connected to node N8.
Connected.

Transistor PT3 is connected between power supply voltage Vdd and node N8, and its gate electrode receives enable signal enable.

Inverter 10 receives a signal from node N8 and receives an internal clock enable signal int. CKE
Is output.

Next, the operation of the SSTL input buffer circuit 800 will be described. Here, it is assumed that a sufficient time has elapsed after power-on.

The SSTL input buffer circuit 800 receives an external clock enable signal ext. CKE and reference voltage Vr
ef is amplified and output.

For example, the reference voltage Vref and the external clock enable signal ext. CKE and an external clock enable signal ext. If the level of CKE is high, the internal clock enable signal int. CKE is
"H", the reference voltage Vref and the external clock enable signal ext. CKE and an external clock enable signal ext. If the level of CKE is low, the internal clock enable signal int. CKE becomes “L”.

Since the configuration of the SSTL input buffer circuit 800 is a pair configuration that is electrically parallel, noise components are canceled. Therefore, there is an advantage that a signal having a small amplitude can be transmitted at a high speed.

[0024]

By the way, SDRAM
Alternatively, in the DDR-SDRAM, after the power supply voltage Vdd is raised, the reference voltage Vref is raised normally, and the external clock enable signal ext. It is necessary to set the level of the CKE to "L" so that an indefinite command is not accepted.

FIG. 21 is a diagram showing signal waveforms when the power supply voltage Vdd is raised. However, the power supply voltage Vd
After the input of d, in the period t1, the reference voltage Vref and
External clock enable signal ext. The level with CKE is both "L".

Therefore, SSTL input buffer circuit 8
00, the reference voltage Vref and the external clock enable signal ext. When comparing the level with CKE,
Internal clock enable signal int. It is unknown whether CKE will be "H" or "L".

It is assumed that the external clock enable signal ex
t. If it is recognized that CKE is higher than the level of reference voltage Vref, internal clock enable signal int. CKE
Becomes "H", the internal clock operates (enable state).

Then, during this period, an external command (ext./RAS, / CAS, / CS, / W
Although E) is undefined, there is a problem that the command is accepted.

According to the present invention, the internal clock enable signal int. Which is the output signal of the input buffer when the external power supply Vdd is raised. The purpose is to control CKE.

[0030]

An input buffer circuit according to the present invention has an input terminal for receiving an externally transmitted input signal, an input reference terminal for receiving an input reference signal serving as a reference, and an input from the input terminal. An interface circuit that determines a logic level of the input signal based on a comparison between a potential level of the input signal and a potential level of the input reference signal input from the input reference terminal, and outputs a signal according to the determination result. And a control circuit for controlling the input reference signal output to the input reference terminal.

Preferably, the control circuit includes a plurality of terminals for receiving a plurality of voltages including a reference voltage, and a switch circuit for connecting one of the plurality of terminals to the input reference terminal. A level comparison circuit for generating a switching signal for controlling switching of the switch circuit according to the level of the reference voltage.

In particular, the switch circuit supplies the reference voltage or the power supply voltage to the input reference terminal, and the level comparison circuit determines a rise of the reference voltage generated based on the power supply voltage. The switching signal is generated by comparing a voltage with the reference voltage.

In particular, it further comprises a circuit for latching the output of the level comparison circuit. In addition, the input buffer circuit according to the present invention is configured such that, based on a comparison between an input terminal for receiving an input signal transmitted from the outside and a potential level of the input signal input from the input terminal and a reference voltage, the logic of the input signal is An interface circuit that determines a level and outputs a signal according to the determination result, and a control circuit that controls an output signal of the interface circuit according to the reference voltage.

Preferably, the control circuit includes a plurality of terminals for receiving a plurality of voltages including an output signal of the interface circuit, and a switch for setting one of the plurality of terminals to an output signal of the control circuit. A level comparison circuit that generates a switching signal for controlling switching of the switch circuit according to the level of the reference voltage.

In particular, the switch circuit supplies an output signal of the interface circuit or a ground voltage, and the level comparison circuit determines a rise of the reference voltage generated based on a power supply voltage; The switching signal is generated by comparing with the reference voltage.

In particular, there is further provided a circuit for latching the output of the level comparison circuit. The input buffer circuit according to the present invention may further comprise: an input terminal receiving an input signal transmitted from the outside; and a logic of the input signal based on a comparison between a potential level of the input signal input from the input terminal and a reference voltage. A first interface circuit that determines a level and outputs a signal corresponding to the determination result; and a logical level of the input signal based on a comparison between a potential level of the input signal input from the input terminal and a threshold value. And a second interface circuit that outputs a signal according to the determination result, and controls a signal output from the first interface circuit or the second interface circuit according to the level of the reference voltage. A control circuit.

Preferably, the control circuit has a plurality of terminals for receiving a plurality of voltages including a signal output from the first interface circuit and a signal output from the second interface circuit. A switching circuit that uses one of the plurality of terminals as an output signal of the control circuit; and a level comparison circuit that generates a switching signal that controls switching of the switching circuit according to a level of the reference voltage.

[0038] In particular, the switch circuit supplies an output signal of the first interface circuit or an output signal of the second interface circuit, and the level comparison circuit supplies the output signal of the reference voltage generated based on a power supply voltage. The switching signal is generated by comparing a predetermined voltage for determining a rise with the reference voltage.

In particular, there is further provided a circuit for latching the output of the level comparison circuit. A semiconductor device according to the present invention includes an input buffer circuit, and an output buffer circuit that operates by receiving a power supply voltage, wherein the input buffer circuit has an input terminal that receives an externally transmitted input signal, and an input reference that serves as a reference. An input reference terminal for receiving a signal, and based on a comparison between a potential level of the input signal input from the input terminal and a potential level of the input reference signal input from the input reference terminal, changes a logic level of the input signal. An interface circuit that determines and outputs a signal corresponding to the determination result, and a control circuit that controls the input reference signal output to the input reference terminal, wherein the control circuit includes a plurality of voltages including a reference voltage. And a switch circuit for connecting one of the plurality of terminals to the input terminal; and Depending on the level of pressure, and a level comparison circuit for generating a switching signal for controlling switching of the switching circuit.

Preferably, the switch circuit supplies the reference voltage or the power supply voltage to the input reference terminal, and the level comparison circuit determines a rise of the reference voltage generated based on the power supply voltage. The switching signal is generated by comparing the predetermined voltage with the reference voltage.

In particular, there is further provided a circuit for latching the output of the level comparison circuit. Further, the semiconductor device of the present invention includes an input buffer circuit, and an output buffer circuit that operates by receiving a power supply voltage, wherein the input buffer circuit has an input terminal that receives an input signal transmitted from outside, and the input terminal An interface circuit that determines a logical level of the input signal based on a comparison between a potential level of the input signal input from the reference voltage and a reference voltage, and outputs a signal according to the determination result, and the interface circuit according to the reference voltage. A control circuit that controls an output signal of an interface circuit, wherein the control circuit includes an output signal of the interface circuit, a plurality of terminals for receiving a plurality of power supply voltages, and one of the plurality of terminals. A switch circuit serving as an output signal of the control circuit, and a switch circuit of the switch circuit according to a level of the reference voltage. And a level comparing circuit for generating a switching signal for controlling the Toggles.

Preferably, the switch circuit supplies an output signal of the interface circuit or a ground voltage, and the level comparison circuit determines a rise of the reference voltage generated based on the power supply voltage. And the reference voltage to generate the switching signal.

Preferably, the apparatus further comprises a circuit for latching the output of the level comparison circuit. Further, the semiconductor device of the present invention includes an input buffer circuit, and an output buffer circuit that operates by receiving a power supply voltage, wherein the input buffer circuit has an input terminal that receives an input signal transmitted from the outside,
A first interface circuit that determines a logic level of the input signal based on a comparison between a potential level of the input signal input from the input terminal and a reference voltage, and outputs a signal according to a determination result; A second interface circuit that determines a logical level of the input signal based on a comparison between a potential level of the input signal input from an input terminal and a threshold, and outputs a signal according to the determination result;
A control circuit that controls a signal output from the first interface circuit or the second interface circuit in accordance with a level of the reference voltage, wherein the control circuit includes an output signal of the first interface circuit; A plurality of terminals for receiving a plurality of voltages, respectively, including an output signal of a second interface circuit; a switch circuit for setting one of the plurality of terminals as an output signal of the control circuit; and a level of the reference voltage. And a level comparison circuit for generating a switching signal for controlling switching of the switch circuit.

Preferably, the switch circuit supplies an output signal of the first interface circuit or an output signal of the second interface circuit, and the level comparison circuit outputs the reference voltage generated based on a power supply voltage. The switching signal is generated by comparing a predetermined voltage for determining the rising of the reference voltage with the reference voltage.

Preferably, the apparatus further comprises a circuit for latching an output of the level comparison circuit.

[0046]

Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding portions have the same reference characters allotted, and description thereof will not be repeated.

(Embodiment 1) FIG. 1 is a block diagram of an input buffer circuit 1000 according to Embodiment 1 of the present invention.

The input buffer circuit 1000 shown in FIG.
The control circuit 300 includes a TL input buffer circuit 800 and a control circuit 300 that switches a reference voltage input to the SSTL input buffer circuit 800.

The output node of the control circuit 300 is
Connected to input node N1 of SSTL input buffer circuit 800.

SSTL input buffer circuit 800 receives external clock enable signal ext. By comparing CKE with a reference voltage input to node N1, internal clock enable signal int. Outputs CKE.

FIG. 2 is a diagram showing an example of a specific configuration of control circuit 300 according to the first embodiment of the present invention.

The control circuit 300 includes a level comparison circuit 12 and a switch circuit 11.

The level comparison circuit 12 has an input node N4,
The level of the signal from N5 is compared and determined, and the switch circuit 1
1 to output a switch signal SW for controlling the switching of No. 1.

That is, the signal level from input node N5 is determined based on the signal level from input node N4. For example, if the level of the signal from the input node N5 is higher than the level of the signal from the input node N4, the switch signal S
W becomes "H". On the other hand, if the signal from the input node N5 is lower in level than the signal from the input node N4,
The switch signal SW becomes “L”.

The switch circuit 11 includes a level comparison circuit 12
Is a circuit for switching the signal output from the input nodes N2 and N3 by the switch signal SW. For example, when the switch signal SW is "L", the signal from the input node N3 is supplied to the output node N10. When the switch signal SW is
When "H", the signal from the input node N2 is
10 is supplied.

FIG. 3 is a diagram showing an example of a specific configuration of input buffer circuit 1000 according to the first embodiment of the present invention.

Here, at the input nodes N2, N3, N4, N5 of the control circuit 300, the reference voltage Vref, the power supply voltage Vdd, and the switch voltage 1/2, respectively.
Vdd-α (α is a minute positive value; the same applies hereinafter) and a reference voltage Vref.

The operation of the input buffer circuit 1000 will be described with reference to the timing chart of FIG.

Here, the SSTL input buffer circuit 800
Is set to "H".

First, after supplying the power supply voltage Vdd, the reference voltage V
During the period (t1) until the rise of the reference voltage Vref and the external clock enable signal ext. CKE
Is "L".

At this time, when the level comparison circuit 12 determines and compares the switch voltage 1/2 Vdd-α with the reference voltage Vref, the level of the reference voltage Vref is low, so that the switch signal SW which is the output signal of the level comparison circuit 12 is obtained.
Becomes “L”.

Therefore, through the switch circuit 11,
Power supply voltage Vdd from input node N3 is input to node N1.

The SSTL input buffer circuit 800 uses the external clock enable signal ext. Ext. Based on the power supply voltage Vdd as a signal from the input node N1. CKE levels are compared, and internal clock enable signal int. CKE
Is output. The power supply voltage Vdd is “H” and the external clock enable signal ext. CKE is "L".
Therefore, internal clock enable signal int. CK
E becomes "L".

Internal clock enable signal int. CK
E is a signal for enabling or disabling the operation of the internal clock, and the internal clock enable signal int. Since CKE is at "L", the operation of the internal clock is stopped (disabled).

Then, the reference voltage Vref rises and the external clock enable signal ext. In a period (t2) until CKE rises, reference voltage Vref is at "H" and external clock enable signal ext. CKE is "L".

At this time, the level comparison circuit 12 compares the switch voltage 1/2 Vdd-α with the reference voltage Vref. Now, the reference voltage Vref is in a state of the reference voltage Vref = １ Vdd because the power supply voltage Vdd has risen. Therefore, the switch signal SW becomes “H” because the level of the reference voltage Vref is high.

Therefore, SSTL input buffer circuit 8
The signal of the input node N1 at 00 is supplied to the input node N2.

The SSTL input buffer circuit 800 uses the reference voltage Vref, which is a signal from the input node N2, as a reference, and sets the external clock enable signal ext. CKE levels are compared, and internal clock enable signal int. CK
E is output.

Reference voltage Vref is at "H", and external clock enable signal ext. Since CKE is "L", the internal clock enable signal int. CKE is "L"
Remains.

Next, the external clock enable signal ex
t. Period (t3) when CKE is "H"(> Vref)
Then, the SSTL input buffer circuit 800 uses the reference voltage Vref, which is a signal from the input node N2, as a reference.
External clock enable signal ext. Compare the levels of CKE.

External clock enable signal ext. CK
E becomes “H” (> Vref), the internal clock enable signal int. CKE becomes "H", and the internal clock operates to enter a standby state.

As described above, the SSTL input buffer circuit 8
00, the reference voltage Vref and the power supply voltage V
dd and the external clock enable signal ext. CKE
When both are "L" (t1), the operation of the internal clock can be stopped.

Here, an example of the configuration of the semiconductor device 10000 having the input buffer circuit 1000 according to the first embodiment of the present invention will be described with reference to FIG. Semiconductor device 1000
0 is the external clock ext. CLK
And / ext. DLL (Delay Locked Loop) 200 for receiving CLK and generating an internal clock, control signals (row address strobe signal / RAS, column address strobe signal / CAS, chip select signal / CS, write enable signal / WE, external clock enable signal ext , CKE, etc.) and the input buffer 20 receiving the address signals An (n = 0, 1,..., 11) and the bank address signals BA0, BA1.
2. a control signal generating circuit 203 for generating an internal control signal in response to an output of the input buffer 201; a row address latch 204 for latching a row address output from the input buffer 202 in response to the internal control signal; Address latch 205 for latching a column address output from input buffer 202, a plurality of memory cells arranged in a matrix, a plurality of word lines arranged in a row direction, and a plurality of bit lines arranged in a column direction , A row decoder 207 for selecting a row based on the output of a row address latch 204 according to an internal control signal, and a column selection based on an output of a column address latch 205 according to an internal control signal. And a column decoder 208.

Input buffers 201 and 202 are DL
The input signal is taken in synchronization with the internal clock output from L200. The input buffer 201 includes the input buffer circuit 1000 described above.

Semiconductor device 10000 further writes data into memory array 206 or
Array input / output circuit 209 for reading data from the memory, read data latch 210 for latching read data according to an internal control signal, an output buffer for fetching data latched in read data latch 210 and outputting to data input / output terminal DQi 211, a write data latch 212 for latching write data, and an input buffer 213 for taking in data from the data input / output terminal DQi and outputting the write data to the write data latch 212.

The output buffer 211 outputs the internal clock int. CLK and / int. C
It operates in synchronization with LK. Also, the output buffer 211
Receives a power supply voltage VddQ used for the operation.

Although the power supply voltage Vdd is used as the voltage supplied to the input node N1 of the SSTL input buffer circuit 800, the present invention is not limited to this.

The input buffer circuit 1010 shown in FIG. 6 may be used instead of the input buffer circuit 1000. In the input buffer circuit 1010, the power supply voltage VddQ input to the output buffer 211 is used as the voltage supplied to the node N1 of the SSTL input buffer circuit 800.

In response to this, the control circuit 3
00 is connected to a switch voltage of 1/2 VddQ
-Α is received.

Power supply voltage VddQ and power supply voltage Vdd input to output buffer 211 are at the same level, and the same result can be obtained.

(Embodiment 2) FIG. 7 is a block diagram of an input buffer circuit 2000 according to Embodiment 2 of the present invention.

The input buffer circuit 2000 shown in FIG.
Control circuit 30 for switching output signals of TL input buffer circuit 800 and SSTL input buffer circuit 800
0.

In the second embodiment, the output signal of SSTL input buffer circuit 800 is supplied to input node N2 of control circuit 300. Then, the internal clock enable signal int. CKE is output.

SSTL input buffer circuit 800 receives an external clock enable signal ex input to node N7.
t. CKE and reference voltage Vref input to node N1
And the internal clock enable signal int. C
KE 'is output.

According to the result of the level comparison between nodes N4 and N5, internal clock enable signal int. CK
E ′ or the signal at node N3 is output from node N10.

FIG. 8 is a diagram showing an example of a specific configuration of input buffer circuit 2000 according to the second embodiment of the present invention.

Here, at the input nodes N2, N3, N4 and N5 of the control circuit 300, the internal clock enable signal int. CKE ',
Ground voltage ext. Vss, switch voltage 1 / 2V
dd-α and the reference voltage Vref are input.

The operation of input buffer circuit 2000 will be described with reference to the timing chart of FIG.

Here, SSTL input buffer circuit 800
Is set to "H".

First, after the supply of the power supply voltage Vdd, the reference voltage V
During the period (t1) until the rise of the reference voltage Vref and the external clock enable signal ext. CKE
Is "L".

Therefore, SSTL input buffer circuit 8
00 internal clock enable signal in
t. CKE ′ may be “H” as described above.

However, at this time, in the level comparison circuit 12, the switch voltage 1/2 Vdd-α and the reference voltage Vre
When f is compared with f, the level of the reference voltage Vref is low, so that the switch signal SW that is the output signal of the level comparison circuit 12 becomes “L”.

Therefore, via the switch circuit 11,
Ground voltage ext. From input node N3. Vss is supplied to the node N10. Therefore, internal clock enable signal int. CKE becomes "L" and the operation of the internal clock is stopped.

Next, the reference voltage Vref rises and the external clock enable signal ext. In a period (t2) until CKE rises, reference voltage Vref is at "H" and external clock enable signal ext. CKE is "L".

At this time, the level comparison circuit 12 compares the switch voltage 1/2 Vdd-α with the reference voltage Vref. Now, the reference voltage Vref is in a state of the reference voltage Vref = １ Vdd because the power supply voltage Vdd has risen. Therefore, the switch signal SW which is an output signal because the level of the reference voltage Vref is high is:
It becomes "H".

Therefore, SSTL input buffer circuit 8
00 output from the internal clock enable signal int. C
KE ′ is supplied to the output node N10 of the control circuit 300.

The SSTL input buffer circuit 800 uses an external clock enable signal ext. CKE levels are compared, and internal clock enable signal int. C
KE 'is output.

Reference voltage Vref is at "H", and external clock enable signal ext. Since CKE is "L", the internal clock enable signal int. CKE 'is "L", and the internal clock enable signal int. C
KE also remains at "L".

Next, the external clock enable signal ex
t. Period (t3) when CKE is "H"(> Vref)
Then, the SSTL input buffer circuit 800 uses the reference voltage Vref, which is a signal from the input node N1, as a reference.
External clock enable signal ext. Compare the levels of CKE.

External clock enable signal ext. CK
E becomes “H” (> Vref), the internal clock enable signal int. CKE 'becomes "H" and the internal clock enable signal int. Since CKE is also at "H", the internal clock operates to enter the standby state.

As described above, the SSTL input buffer circuit 8
00 as an external clock enable signal e
xt. CKE and the ground voltage ext. Vss and the external clock enable signal ext. The operation of the internal clock can be stopped even when CKE is both "L" (t1).

FIG. 10 shows a case where the power supply voltage Vdd of the switch voltage 1/2 Vdd-α input to the control circuit 300 included in the input buffer 201 of FIG.
This is an input buffer circuit 2010 according to the second embodiment of the present invention in which the power supply voltage VddQ input to the input buffer circuit 1 is replaced.

The connection relationship is the same as that described in the first embodiment, and description thereof will not be repeated. Corresponding to this, input node N4 of control circuit 300 receives switch voltage 1/2 VddQ-α.

Power supply voltage VddQ and power supply voltage Vdd input to output buffer 211 are at the same level, and the same result can be obtained.

(Embodiment 3) FIG. 11 is a block diagram of an input buffer circuit 3000 according to Embodiment 3 of the present invention.

The input buffer circuit 3000 shown in FIG.
The circuit includes an STL input buffer circuit 800, a CMOS input buffer circuit 600, and a control circuit 300 that switches between an output signal of the SSTL input buffer circuit 800 and an output signal of the CMOS input buffer circuit 800.

In the third embodiment, the output signal of SSTL input buffer circuit 800 is supplied to input node N2 of control circuit 300. The output signal of the CMOS input buffer circuit 600 is supplied to the input node N3 of the control circuit 300.

SSTL input buffer circuit 800 is connected to external clock enable signal ex input to node N7.
t. CKE and reference voltage Vref input to node N1
And the internal clock enable signal int. C
KE 'is output.

CMOS input buffer circuit 600 receives external clock enable signal ext. The internal clock enable signal int. CKE "is output.

FIG. 12 shows an example of a specific configuration of input buffer circuit 3000 according to the third embodiment of the present invention.

Here, at the input nodes N2, N3, N4 and N5 of the control circuit 300, the internal clock enable signal int. CKE ',
Internal clock enable signal int. CKE ", the switch voltage 1/2 Vdd-.alpha., And the reference voltage Vref. The internal clock enable signal int.CKE is output from the output node N10 of the control circuit 300.
Is output.

The operation of input buffer circuit 3000 will be described with reference to the timing chart of FIG.

Here, SSTL input buffer circuit 800
Is set to "H".

First, after the power supply voltage Vdd is applied, the reference voltage V
During the period (t1) until the rise of the reference voltage Vref and the external clock enable signal ext. CKE
Is "L".

Therefore, SSTL input buffer circuit 8
00 internal clock enable signal in
t. CKE ′ may be “H” as described above.

However, at this time, in the level comparison circuit 12, the switch voltage 1/2 Vdd-α and the reference voltage Vre
f, the reference signal Vref is low, so that the switch signal SW which is the output signal of the level comparison circuit 12 is obtained.
Becomes “L”.

Therefore, through the switch circuit 11,
Internal clock enable signal in from input node N3
t. CKE "is supplied to the node N10. Therefore, since the internal clock enable signal int.CKE" is "L", the internal clock enable signal int.
CKE becomes "L", and the operation of the internal clock is stopped.

Next, reference voltage Vref rises and external clock enable signal ext. In a period (t2) until CKE rises, reference voltage Vref is at "H" and external clock enable signal ext. CKE is "L".

At this time, the level comparison circuit 12 compares the switch voltage 1/2 Vdd-α with the reference voltage Vref. Now, the reference voltage Vref is in a state of the reference voltage Vref = １ Vdd because the power supply voltage Vdd has risen. Therefore, the switch signal SW which is an output signal because the level of the reference voltage Vref is high is:
It becomes "H".

Therefore, SSTL input buffer circuit 8
00 output from the internal clock enable signal int. C
KE ′ is supplied to the output node N10 of the control circuit 300.

The SSTL input buffer circuit 800 uses an external clock enable signal ext. REF. Based on a reference voltage Vref, which is a signal from the input node N1. CKE levels are compared, and internal clock enable signal int. CK
E 'is output.

Reference voltage Vref is at "H" and external clock enable signal ext. Since CKE is "L", the internal clock enable signal int. CKE 'is "L", and the internal clock enable signal int. C
KE also remains at "L".

Next, the external clock enable signal ex
t. Period (t3) when CKE = “H” (> Vref)
Then, the SSTL input buffer circuit 800 uses the reference voltage Vref, which is a signal from the input node N1, as a reference.
External clock enable signal ext. Compare the levels of CKE.

External clock enable signal ext. CK
E becomes “H” (> Vref), the internal clock enable signal int. CKE 'becomes "H" and the internal clock enable signal int. Since CKE is also at "H", the internal clock operates to enter the standby state.

As described above, the SSTL input buffer circuit 8
00 and the CMOS output signal are used interchangeably, so that the reference voltage Vref and the external clock enable signal ext. The operation of the internal clock can be stopped even when CKE is both "L" (t1).

FIG. 14 shows a case where the power supply voltage Vdd of the switch voltage 1/2 Vdd-α input to the control circuit 300 included in the input buffer 201 of FIG.
An input buffer circuit 3010 according to a third embodiment of the present invention, in which the power supply voltage VddQ input to the input buffer circuit 1 is replaced.

The connection relation is the same as that described in the first embodiment, and description thereof will not be repeated. Corresponding to this, input node N4 of control circuit 300 receives switch voltage 1/2 VddQ-α.

The levels of power supply voltage VddQ and power supply voltage Vdd input to output buffer 211 are the same, and the same result can be obtained.

(Embodiment 4) FIG. 15 shows a level comparison circuit 13 obtained by improving the level comparison circuit 12 used in Embodiments 1 to 3 of the present invention.

Level Comparison Circuit 1 of Embodiment 4 of the Present Invention
Reference numeral 3 includes a level comparison circuit 12, an inverter 92, and a P-channel MOS transistor PT4.

The level comparison circuit 12 receives the enable signal enab from the nodes N4 and N5 and the inverter 92.
In response to le, a switch signal SW, which is an output signal, is supplied to the node N20.

Inverter 92 receives a signal from node N20 and outputs an enable signal enable.

P-channel MOS transistor PT4
Is provided between the power supply voltage Vdd and the node N20. A gate electrode of the P-channel type MOS transistor PT4 is connected to an enable signal which is an output signal of the inverter 92.
Receive enable.

In the level comparison circuit 13 of the present invention, when the switch signal SW output from the level comparison circuit 12 becomes “H”, an “L” level enable signal enable is input to the level comparison circuit 12.

The level comparison circuit 12 outputs the enable signal en
"able" stops the operation by "L". On the other hand, the P-channel MOS transistor PT4 is turned on, and the switch signal SW is latched at "H".

As a result, the power consumption of the level comparison circuit 13 can be reduced. The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description of the embodiments, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0137]

According to the input buffer circuit and the semiconductor device of the present invention, the signal input to the interface circuit is switched according to the reference voltage, so that it takes time for the reference voltage to rise when the power is turned on. It is possible to avoid malfunction of the circuit.

Further, when a signal is switched according to the reference voltage, the power consumption of the entire circuit can be reduced by providing a latch circuit.

According to the input buffer circuit and the semiconductor device of the present invention, the signal output from the interface circuit is switched to another signal according to the reference voltage, so that it takes time for the reference voltage to rise when the power is turned on. Therefore, it is possible to avoid causing a malfunction of the circuit caused by this.

Further, when a signal output from the interface circuit is switched to another signal according to the reference voltage, the power consumption of the entire circuit can be reduced by providing a latch circuit.

According to the input buffer circuit and the semiconductor device of the present invention, the signal output from the first interface circuit is switched to the signal output from the second interface circuit in accordance with the reference voltage, so that the power is turned on. It is possible to prevent the circuit from malfunctioning due to the time required for the rise of the reference voltage.

Further, when a signal output from the first interface circuit is switched to a signal output from the second interface circuit according to the reference voltage, the power consumption of the entire circuit is reduced by providing a latch circuit. can do.

[Brief description of the drawings]

FIG. 1 shows an input buffer circuit 1 according to a first embodiment of the present invention.
000 is a block diagram.

FIG. 2 is a diagram showing an example of a specific configuration of a control circuit 300 according to Embodiment 1 of the present invention.

FIG. 3 is an input buffer circuit 1 according to the first embodiment of the present invention.
000 is a diagram showing an example of a specific configuration of 000. FIG.

FIG. 4 is an input buffer circuit 1 according to the first embodiment of the present invention.
000 is a timing chart.

FIG. 5 is an input buffer circuit 1 according to the first embodiment of the present invention.
FIG. 13 is a diagram illustrating an example of a configuration of a semiconductor device 10000 having a 000.

FIG. 6 is an input buffer circuit 1 according to the first embodiment of the present invention.
It is a figure which shows an example of a specific structure of 010.

FIG. 7 shows an input buffer circuit 2 according to a second embodiment of the present invention.
000 is a block diagram.

FIG. 8 shows an input buffer circuit 2 according to a second embodiment of the present invention.
000 is a diagram showing an example of a specific configuration of 000. FIG.

FIG. 9 shows an input buffer circuit 2 according to the second embodiment of the present invention.
000 is a timing chart.

FIG. 10 is a diagram illustrating an example of a specific configuration of an input buffer circuit 2010 according to Embodiment 2 of the present invention.

FIG. 11 is a block diagram of an input buffer circuit 3000 according to a third embodiment of the present invention.

FIG. 12 is a diagram illustrating an example of a specific configuration of an input buffer circuit 3000 according to the third embodiment of the present invention.

FIG. 13 is a timing chart of the input buffer circuit 3000 according to the third embodiment of the present invention.

FIG. 14 is a diagram illustrating an example of a specific configuration of an input buffer circuit according to a third embodiment of the present invention;

FIG. 15 is a diagram showing an improved example of the level comparison circuit used in the first to third embodiments of the present invention.

FIG. 16 shows a conventional CMOS input buffer circuit 600.
It is a block diagram of.

FIG. 17 shows a conventional CMOS input buffer circuit 600.
It is a figure showing an example of.

FIG. 18 shows a conventional CMOS input buffer circuit 600.
6 is a timing chart of FIG.

FIG. 19 is a block diagram of the SSTL input buffer circuit 800.

FIG. 20 is a diagram illustrating an example of an SSTL input buffer circuit 800;

FIG. 21 is a diagram illustrating signal waveforms when the power supply voltage Vdd is raised.

[Explanation of symbols]

10, 91, 92 inverter, 11 switch circuit,
12, 13 level comparison circuit, 90 NAND circuit, 2
01, 202 input buffer, 203 control signal generation circuit, 204 row address latch, 205 column address latch, 206 memory array, 207 row decoder, 208 column decoder, 209 array input / output circuit, 210 read data latch, 211 output buffer, 212 Write data latch, 213 input buffer, 300 control circuit, 600, 800, 10
00,1010,2000,2010,3000,30
10 input buffer circuit, 10000 semiconductor device.

 ──────────────────────────────────────────────────続 き Continuing on the front page F term (reference) 5J056 AA01 BB02 BB17 BB37 CC02 CC09 DD13 DD29 FF01 FF06 FF07 FF08 KK00 5K029 AA01 AA11 DD04 HH01 HH08 5M024 AA14 AA40 BB03 BB32 DD36 DD39 DD40 JJ03 PP02

Claims (21)

[Claims] An input terminal for receiving an input signal transmitted from outside; an input reference terminal for receiving an input reference signal serving as a reference; a potential level of the input signal input from the input terminal; An interface circuit that determines a logical level of the input signal based on a comparison with a potential level of the input reference signal to be input, and outputs a signal corresponding to the determination result; and the input reference that outputs to the input reference terminal. An input buffer circuit comprising: a control circuit that controls a signal. 2. The control circuit, comprising: a plurality of terminals for respectively receiving a plurality of voltages including a reference voltage; a switch circuit for connecting one of the plurality of terminals to the input reference terminal; A level comparison circuit for generating a switching signal for controlling switching of the switch circuit according to the level of the reference voltage. The input buffer circuit according to claim 1. 3. The switch circuit supplies the reference voltage or the power supply voltage to the input reference terminal, and the level comparison circuit determines a rise of the reference voltage generated based on the power supply voltage. 3. The input buffer circuit according to claim 2, wherein the switching signal is generated by comparing a voltage with the reference voltage. 4. The input buffer circuit according to claim 2, further comprising a circuit for latching an output of said level comparison circuit. 5. An input terminal for receiving an input signal transmitted from the outside, and a logic level of the input signal is determined based on a comparison between a potential level of the input signal input from the input terminal and a reference voltage. An input buffer circuit, comprising: an interface circuit that outputs a signal according to a determination result; and a control circuit that controls an output signal of the interface circuit according to the reference voltage. 6. The control circuit, comprising: a plurality of terminals for receiving a plurality of voltages including an output signal of the interface circuit; and a switch circuit for setting one of the plurality of terminals to an output signal of the control circuit. The input buffer circuit according to claim 5, further comprising: a level comparison circuit that generates a switching signal for controlling switching of the switch circuit according to a level of the reference voltage. 7. The switch circuit supplies an output signal of the interface circuit or a ground voltage, the level comparison circuit determines a rise of the reference voltage generated based on a power supply voltage, and a predetermined voltage for determining a rise of the reference voltage. 7. The input buffer circuit according to claim 6, wherein said switching signal is generated by comparing with said reference voltage. 8. The input buffer circuit according to claim 6, further comprising a circuit for latching an output of said level comparison circuit. And determining a logic level of the input signal based on a comparison between an input terminal receiving an input signal transmitted from the outside and a potential level of the input signal input from the input terminal and a reference voltage. A first interface circuit that outputs a signal according to a determination result, and a logic level of the input signal is determined based on a comparison between a potential level of the input signal input from the input terminal and a threshold value, A second interface circuit that outputs a signal according to the determination result; and a control circuit that controls a signal output from the first interface circuit or the second interface circuit according to the level of the reference voltage. ,
Input buffer circuit. 10. The control circuit, comprising: a plurality of terminals for receiving a plurality of voltages including a signal output from the first interface circuit and a signal output from the second interface circuit; A switch circuit that uses one of the plurality of terminals as an output signal of the control circuit, and a level comparison circuit that generates a switching signal that controls switching of the switch circuit according to a level of the reference voltage. Item 10. The input buffer circuit according to Item 9. 11. The switch circuit supplies an output signal of the first interface circuit or an output signal of the second interface circuit, and the level comparison circuit outputs a signal of the reference voltage generated based on a power supply voltage. The input buffer circuit according to claim 10, wherein the switching signal is generated by comparing a predetermined voltage for determining a rise with the reference voltage. 12. The input buffer circuit according to claim 10, further comprising a circuit for latching an output of said level comparison circuit. 13. An input buffer circuit comprising: an input buffer circuit; and an output buffer circuit that receives a power supply voltage and outputs a signal processing result of the input buffer circuit, wherein the input buffer circuit receives an input signal transmitted from outside. An input reference terminal for receiving an input reference signal serving as a reference, based on a comparison between a potential level of the input signal input from the input terminal and a potential level of the input reference signal input from the input reference terminal, An interface circuit that determines a logic level of the input signal and outputs a signal according to the determination result; and a control circuit that controls the input reference signal to be output to the input reference terminal. A plurality of terminals for receiving a plurality of voltages, respectively, including a voltage; and one of the plurality of terminals as the input terminal. A semiconductor device, comprising: a switch circuit for connection; and a level comparison circuit for generating a switching signal for controlling switching of the switch circuit according to a level of the reference voltage. 14. The switch circuit supplies the reference voltage or the power supply voltage to the input reference terminal, and the level comparison circuit determines a rise of the reference voltage generated based on the power supply voltage. 14. The semiconductor device according to claim 13, wherein the switching signal is generated by comparing a predetermined voltage with the reference voltage. 15. The semiconductor device according to claim 13, further comprising a circuit for latching an output of said level comparison circuit. 16. An input buffer circuit, comprising: an input buffer circuit; and an output buffer circuit for receiving a power supply voltage and outputting a signal processing result of the input buffer circuit, wherein the input buffer circuit receives an input signal transmitted from outside. An interface circuit that determines a logic level of the input signal based on a comparison between a potential level of the input signal input from the input terminal and a reference voltage, and outputs a signal according to a determination result; A control circuit that controls an output signal of the interface circuit in accordance with a voltage, wherein the control circuit includes: a plurality of terminals for receiving a plurality of voltages, including an output signal of the interface circuit; and the plurality of terminals. A switch circuit that takes one of the output signals from the control circuit; and a level of the reference voltage. And a level comparison circuit for generating a switching signal for controlling switching of the switch circuit. 17. The switch circuit supplies an output signal or a ground voltage of the interface circuit, and the level comparison circuit includes a predetermined voltage for determining a rise of the reference voltage generated based on the power supply voltage. 17. The switching signal is generated by comparing the switching signal with the reference voltage.
13. The semiconductor device according to claim 1. 18. The semiconductor device according to claim 16, further comprising a circuit for latching an output of said level comparison circuit. 19. An input buffer circuit, comprising: an input buffer circuit; and an output buffer circuit for receiving a power supply voltage and outputting a signal processing result of the input buffer circuit, wherein the input buffer circuit receives an input signal transmitted from outside. A first interface circuit that determines a logic level of the input signal based on a comparison between a potential level of the input signal input from the input terminal and a reference voltage, and outputs a signal according to the determination result; A second interface circuit that determines a logical level of the input signal based on a comparison between a potential level of the input signal input from the input terminal and a threshold, and outputs a signal according to the determination result; Controlling a signal output from the first interface circuit or the second interface circuit in accordance with the level of the reference voltage A plurality of terminals for receiving a plurality of voltages, each of the plurality of terminals including an output signal of the first interface circuit and an output signal of the second interface circuit; A semiconductor device, comprising: a switch circuit that uses one of its terminals as an output signal of the control circuit; and a level comparison circuit that generates a switching signal that controls switching of the switch circuit according to a level of the reference voltage. 20. The switch circuit supplies an output signal of the first interface circuit or an output signal of the second interface circuit, and the level comparison circuit outputs a signal of the reference voltage generated based on a power supply voltage. 20. The semiconductor device according to claim 19, wherein the switching signal is generated by comparing a predetermined voltage for determining a rise with the reference voltage. 21. The semiconductor device according to claim 19, further comprising a circuit for latching an output of said level comparison circuit.