KR100573720B1 - Power semiconductor device - Google Patents

Abstract

An undoped GaN channel layer 1, an n-type Al _0.2 Ga _0.8 N barrier layer 2 formed on the channel layer 1, and a p-type Al _0.1 Ga _0.9 N semiconductor layer selectively formed on the barrier layer 2 (3 ), A barrier located on either side of the semiconductor layer 3 and adjacent to the semiconductor layer 3, at least between the drain electrode 4 formed on the barrier layer 2, at least between the semiconductor layer 3 and the drain electrode 4. A power semiconductor device comprising an insulating film 7 formed on the layer 2 and a field plate electrode 8 formed on the insulating film 7 is disclosed.

Description

Power semiconductor device {POWER SEMICONDUCTOR DEVICE}

The present invention relates to a power semiconductor device used for power control. In particular, the present invention relates to lateral type power FETs using nitride semiconductors, Schottky barrier diodes (SBDs), and the like.

Power semiconductor devices such as switching devices and diodes are used in power control circuits such as switching mode power supplies and inverter circuits. Power semiconductor devices require characteristics such as high breakdown voltage and low ON resistance. There is a trade-off relationship determined by the device material between the breakdown voltage and the ON resistance of the power semiconductor device. With recent advances in technology, low ON resistance near the limits of the main device material, silicon, is realized in power semiconductor devices. In order to further reduce the ON resistance, it is necessary to change the device material. Nitride semiconductors such as GaN and AlGaN, silicon carbide (SiC), and wide band gap semiconductors are used as the switching device materials. By doing so, it is possible to improve the trade-off relationship determined by the material, and to achieve a low ON resistance. High Electron Mobility Transistors (HEMT) using nitride semiconductors such as GaN and AlGaN are disclosed in the following documents. The document is "p-Capped GaN-AlGaN-GaN High Electron Mobility Transistors" by "Coffie et al." Disclosed in "VOL. 23, No. 10. OCTOBER 2002, page 598-590" of "IEEE ELECTRON DEVICE LETTERS". .

In recent years, research on power semiconductor devices using wide band gap semiconductors has often been conducted. In nitride semiconductors such as GaN, low ON resistance has been realized. However, no design has been made that takes into account the inherent characteristics of the power device, namely avalanche withstand capability. This is because GaN-based devices are designed based on radio frequency (RF) devices.

Moreover, a field plate electrode is provided in the FET, thus high breakdown voltage is achieved. The above technique is disclosed in, for example, Japanese Patent Laid-Open Nos. Hei 5-21793, 2001-230263, and Japanese Patent No. 3231613.

An object of the present invention is to provide a power semiconductor device having a high avalanche resistance and a very low ON resistance.

According to this aspect of the invention, an undoped or n-type Al _Y Ga ₁ formed on one surface of the first semiconductor layer, the first semiconductor layer of undoped Al _X Ga _1-X N (0 ≦ _X ≦ 1) A second semiconductor layer of _-Y N (0≤Y≤1, X <Y), a third semiconductor layer of p-type Al _Z Ga _1-Z N (0≤Z≤1) selectively formed on the second semiconductor layer, A first electrode formed on one of both sides of the third semiconductor layer and formed on the second semiconductor layer adjacent to the third semiconductor layer, at least between the first electrode formed on the second semiconductor layer, and at least between the third semiconductor layer and the first electrode; Provided is a power semiconductor device having formed field plate electrodes.

The power semiconductor device according to the present invention generates a two-dimensional electron gas having a high mobility by combining an AlGaN-based heterojunction structure, and uses an electron gas generated as a carrier for carrying current, thereby achieving low ON resistance. . Since a nitride semiconductor having a wide band gap is used and a field plate structure is adopted, a high breakdown voltage is realized. Furthermore, since the p-type AlGaN layer is formed on the surface of the semiconductor layer, it is possible to quickly release holes when avalanche breakdown occurs. Thus, high avalanche resistance can be obtained. Avalanche breakdown occurs in the semiconductor, i.e., at the p-n junction surface, and is not present at the interface between the semiconductor and the protective film, such as the end of the field plate electrode. By doing so, it is possible to prevent an unstable interface due to heat, and thus it is possible to realize an element having high reliability.

1 is a cross-sectional view schematically showing a power semiconductor device according to a first embodiment of the present invention;

2 is a sectional view schematically showing a power semiconductor device according to a first modification of the first embodiment;

3 is a sectional view schematically showing a power semiconductor device according to a second modification of the first embodiment;

4 is a sectional view schematically showing a power semiconductor device according to a third modification of the first embodiment;

5 is a sectional view schematically showing a power semiconductor device according to a second embodiment of the present invention;

6 (a) and 6 (b) are cross-sectional views and characteristic diagrams for explaining the second embodiment;

7 (a) to 7 (c) are cross-sectional views and characteristic diagrams for explaining the second embodiment;

8 is a sectional view schematically showing a power semiconductor device according to a third embodiment of the present invention;

9 is a sectional view schematically showing a power semiconductor device according to a fourth embodiment of the present invention;

10 is a sectional view schematically showing a power semiconductor device according to a modification of the fourth embodiment;

11 is a sectional view schematically showing a power semiconductor device according to a fifth embodiment of the present invention;

12 is a sectional view schematically showing a power semiconductor device according to a first modification of the fifth embodiment;

13A and 13B are a cross-sectional view and a plan view schematically illustrating a power semiconductor device according to a second modification of the fifth embodiment;

14 is a sectional view schematically showing a power semiconductor device according to a sixth embodiment of the present invention;

15 is a schematic cross-sectional view of a power semiconductor device according to a seventh embodiment of the present invention;

(A) and (b) are sectional drawing and characteristic diagram for demonstrating the said 7th Example.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Corresponding parts are designated by like reference numerals throughout the drawings.

(First embodiment)

1 is a cross-sectional view schematically illustrating a structure of a junction type power HEMT (High Electron Mobility Transistor) according to a first embodiment of the present invention.

The HEMT comprises a channel layer 1 comprising a GaN layer (X = 0) as undoped Al _X Ga _1-X N (0 ≦ _X ≦ 1). The thickness of the channel layer 1 is set to about 1 to 2 mu m to obtain a breakdown voltage of 600V. The barrier layer 2 has a thickness of 0.02 μm and is formed on the surface (one side) of the channel layer 1 as n-type Al _Y Ga _1-Y N (0 ≦ _Y ≦ ₁ , X <Y). Barrier layer 2 comprises an Al _0.2 Ga _0.8 N layer (Y = 0.2) in which Si is doped in an amount of about 10 ¹³ (atom / cm ² ) as impurities. Moreover, the semiconductor layer 3 has a thickness of 0.01 mu m and is selectively formed on the barrier layer 2 as p-type Al _Z Ga _1-Z N (0 ≦ _Z ≦ 1). The semiconductor layer 3 includes an Al _0.1 Ga _0.9 N layer (Z = 0.1) doped with Mg as an impurity.

The drain electrode 4 (D: first electrode) and the source electrode 5 (S: second electrode) made of Ti / Al / Ni / Au are formed of the semiconductor layer 3 on the barrier layer 2. It is formed separately from each other on both sides. The drain and source electrodes 4, 5 are electrically connected to the surface of the barrier layer 2, respectively.

A gate electrode 6 (G: gate electrode) made of Pt or Ni / Au is formed on the semiconductor layer 3. The gate electrode 6 is electrically connected to the surface of the semiconductor layer 3.

In order to cover the gate electrode 6 and the surrounding barrier layer 2 continuously, an insulating film 7 is formed. A field plate electrode 8 made of Ti / Al / Ni / Au is formed on the insulating film 7 so as to be positioned between the gate electrode 6 and the drain electrode 4. The field plate electrode 8 is electrically connected to the source electrode 5.

The HEMT having the above structure operates as a junction type FET in which the depth of the depletion layer formed in the surface region of the channel layer 1 is controlled in accordance with the voltage applied to the gate electrode 6. Thus, the current flowing between the source and drain electrodes 5, 4 is controlled in accordance with the depth of the depletion layer.

In the HEMT of the first embodiment, nitride semiconductors such as Al _X Ga _1-X N, Al _Y Ga _1-Y N, and Al _Z Ga _1-Z N having a wide band gap are used as the device materials. Therefore, the critical field is strengthened, and the high breakdown voltage of the device can be realized. The field plate electrode 8 is formed between the gate and the drain for determining the breakdown voltage. Therefore, when a voltage is applied, the electric field applied between the gate electrode 6 and the drain electrode 4 is lowered, and the reduction of the breakdown voltage can be prevented. A high mobility two-dimensional electron gas is generated at the AlGaN / GaN hetero interface including the barrier layer 2 and the channel layer 1, so that a low ON resistance can be realized.

Moreover, the p-type semiconductor layer 3 is formed on the n-type barrier layer 2. Therefore, if avalanche breakdown occurs in the device, the generated holes quickly move to the p-type semiconductor layer 3, and thus high avalanche resistance capability is realized.

Furthermore, since the p-type semiconductor layer 3 is formed on the barrier layer 2, the following effect is obtained, that is, the effect that the gate leakage current is reduced.

In a typical HEMT structure, the breakdown voltage is determined by the electric field generated at the Schottky junction of the gate. In contrast, in the HEMT structure of the embodiment, the electric field generated at the p-n junction between the p-type semiconductor layer 3 and the n-type barrier layer determines the breakdown voltage. That is, a yield point exists in a semiconductor layer compared with the structure in which the characteristic nonuniformity of a Schottky junction element tends to become large. Therefore, the following effects, i.e., nonuniformity of breakdown voltage, are prevented.

Moreover, in a typical HEMT structure, high electric fields are generated in gate schottky interfaces, field plate ends, metal interfaces between semiconductors and passivation films, and the like. For this reason, if avalanche breakdown is designed to occur at this point, a change in characteristics due to heat is likely to occur. In contrast, in the HEMT structure of the above embodiment, the yield point exists at the pn junction of the semiconductor layer. Therefore, the stability of avalanche breakdown increases, and a device with high reliability is realized.

Since the field plate electrode 8 is connected to the source electrode 5, the gate / drain capacitance therebetween becomes small, and therefore a high speed switching operation is realized.                 

The semiconductor layer 3 including the p-type Al _0.1 Ga _0.9 N layer is uniformly formed by crystal growth together with the channel layer 1 and the barrier layer 2. Thereafter, the semiconductor layer 3 is patterned and formed by etching. Alternatively, the semiconductor layer 3 is formed by crystal growth and then by a selective oxidation process. Alternatively, the channel layer 1 and the barrier layer 2 may be formed by crystal growth, and the semiconductor layer 3 may then be formed on the surface of those layers by selective growth.

(First modification of the first embodiment)

FIG. 2 is a schematic cross-sectional view illustrating a structure of the power HEMT shown in FIG. 1 according to the first modification. In the power HEMT shown in FIG. 1, a dielectric layer 7 is formed to continuously cover the gate electrode 6 and the surrounding barrier layer 2, and the field plate electrode 8 is electrically connected to the source electrode 5. You are connected.

In contrast, the power HEMT of FIG. 2 has the following structure. In other words, the dielectric layer 7 is formed so as to be located between the semiconductor layer 3 and the drain electrode 4, and is adjacent to the semiconductor layer 3. The gate electrode 6 is formed to extend to the dielectric layer 7 in addition to the upper surface of the semiconductor layer 3. That is, according to the first modification, the gate electrode 6 simultaneously functions as the field plate electrode 8 shown in FIG.

The modified power HEMT can achieve the same effect as that of FIG. 1, and furthermore, the field plate electrode and the gate electrode can be formed together. Thus, the following effects are obtained. That is, the manufacturing process can be simplified when compared with FIG.                 

(2nd modification of 1st Example)

3 is a cross-sectional view schematically illustrating a structure of the power HEMT shown in FIG. 1 according to a second modified example. The power HEMT of FIG. 3 differs from FIG. 1 in that the gate electrode 6 is formed to extend to the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3. That is, in the power HEMT of FIG. 3, the gate electrode 6 forms a Schottky junction with the barrier layer 2.

According to the second variant, the gate electrode 6 forms a schottky connection with the barrier layer 2. However, since the semiconductor layer 3 is connected to the gate electrode 6, holes are released through the semiconductor layer 3 at the time of avalanche breakdown, and thus a high avalanche resistance capability is realized as in the case of FIG. Moreover, the same effects as in the case of FIG. 1 are obtained.

(Third Modified Example of First Embodiment)

4 is a cross-sectional view schematically illustrating a structure of the power HEMT shown in FIG. 1 according to a third modified example. In the power HEMT of FIG. 3, the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3. In contrast, in the power HEMT of FIG. 4, the gate electrode 6 is formed to extend to the surface of the barrier layer 2 adjacent to the source electrode 5 of the semiconductor layer 3.

According to the third variant, the gate electrode 6 forms a schottky connection with the barrier layer 2. However, since the semiconductor layer 3 is connected to the gate electrode 6, holes are released through the semiconductor layer 3 at the time of avalanche breakdown, and thus a high avalanche resistance capability is realized as in the case of FIG. Moreover, the same effects as in the case of FIG. 1 are obtained.

Second Embodiment                 

5 is a schematic cross-sectional view of a structure of a junction type power HEMT according to a second embodiment of the present invention. In the power HEMT of FIG. 1, the semiconductor layer 3 including the p-AlGaN layer was formed to the same length as the gate electrode 6. That is, the ends of the semiconductor layer 3 on the drain electrode 4 side are aligned at the positions of the ends of the gate electrode 6 on the same side.

In contrast, in the power HEMT of the second embodiment, in the semiconductor layer 3 including the p-AlGaN layer, the drain electrode 4 has an end at the end of the drain electrode 4 from the end of the gate electrode 6 at the drain electrode 4 side. 4) is formed to extend to the side. Moreover, the semiconductor layer 3 is formed so that the end of the drain electrode 4 side can be located under the field plate electrode 8.

FIG. 6A is an enlarged cross-sectional view of an end region of the power HEMT semiconductor layer 3 of FIG. 5, and FIG. 6B is an electric field in the barrier layer 2 when the power HEMT of FIG. 5 operates. Characteristic diagram showing the distribution.

As shown in FIG. 5, the semiconductor layer 3 is formed such that the terminal on the side of the drain electrode 4 can be located below the field plate electrode 8. By doing so, as shown in Fig. 6B, the field concentration points exist at the end of the semiconductor layer 3 and the end of the field plate electrode 8. In FIG. 6B, the characteristic curve 21 (line) shows a case where the insulating film 7 is formed thick with a predetermined thickness, while the characteristic curve 22 shows a case where the insulating film 7 is formed thin in a predetermined thickness. Indicates.

More specifically, the dielectric layer 7 below the field plate electrode 8 is formed to have an appropriate thickness, so that avalanche breakdown occurs, that is, the point where the electric field is maximized is set at the end of the semiconductor layer 3. . Therefore, since the holes are released quickly during avalanche yield, sufficient avalanche resistance can be ensured.

The following is a description of the method of setting the thickness of the insulating film 7 so that the electric field is maximum at the end of the semiconductor layer 3. FIG. 7A is an enlarged cross-sectional view of an end region of the power HEMT semiconductor layer 3 illustrated in FIG. 5. FIG. 7B is a characteristic diagram showing electric field distribution in the horizontal direction when the power HEMT of FIG. 5 operates. FIG. 7C is a characteristic diagram illustrating electric field distribution in the vertical direction when the power HEMT of FIG. 5 operates. In FIGS. 7B and 7C, the end of the semiconductor layer 3 on the drain electrode 4 side is set to A, and the point of the barrier layer 2 below the end of the field plate electrode 8 is set to A. FIG. The point at the end of the field plate electrode 8 is set to C. The electric fields at points A to C are set to E _A , E _B , and E _C , respectively. Further, the distance from point A to B, that is, the length of the field plate electrode 8 is set to L, and the thickness of the insulating film 7 is set to t.

Based on the magnitude of the electric field of each point and the dimension of each element, the voltage V _AB between the points A and B and the voltage V _CB between the points C and B are each expressed by the following equation.

V _AB = (E _A + E _B ) L / 2

V _CB = E _C t

The potential of the field plate electrode 8 is almost equal to the potential of the semiconductor layer 3, and therefore the voltage V _AB is equal to the voltage V _CB . Since the electric flux density persists, the relationship between the electric field E _B and the electric field E _C is expressed as in Equation 3 below.

_{ε i · E C = ε S} E B

Here, ε _i is the dielectric constant (relative permittivity) of the insulating film 7, and ε _S is the dielectric constant of the barrier layer 2. Equations 1 to 3 are modified so that the relationship between the electric fields E _A and E _B can be determined. The relationship is represented by the following equation (4).

E _A / E _B = 2ε _S t / ε _i L-1

In this case, the electric field E _A is set larger than the electric field E _B , and therefore the avalanche resistance is large. Therefore, the ratio of E _A and E _B represented by equation (4) is set larger than one. The following equation (5) is obtained by modifying the equation (4) based on the above.

ε _S t> ε _I L

Therefore, it is preferable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so as to satisfy the relationship represented by the above expression (5).                 

If the length L of the field plate electrode is set to 2 μm, the insulating film 7 is made of SiO ₂ , and the composition ratio of the barrier layer 2 including the AlGaN layer is set to 0.2, the dielectric constant ε _i and ε _S ) are 3.9 and 9.3, respectively. Therefore, it is preferable that the thickness of the insulating film 7 is set to 0.83 mu m or more.

In wide band gap semiconductors such as AlGaN and GaN, the critical field is close to the dielectric breakdown field of the insulating film. If the dielectric breakdown voltage of the insulating film 7 is less than the avalanche breakdown voltage, the dielectric breakdown voltage determines the breakdown voltage of the device. In this case, if a voltage equal to the breakdown voltage of the device is applied to the device, the device is destroyed. If the critical field of the semiconductor layer is equal to the dielectric breakdown field of the insulating film, the electric field E _C of point _C shown in FIG. 7C is the electric field E _A of point A shown in FIG. 7B. Becomes smaller. By doing so, genetic surrender can be avoided.

When Equations 1 to 3 are modified so that the relationship between E _A and E _C can be determined, the relationship is represented by Equation 6 below.

E _A / E _C = 2t / L-ε _i / ε _S

The ratio represented by Equation 6 becomes larger than 1, so that the genetic yield can be avoided. Therefore, it is preferable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so that the following expression (7) is satisfied.                 

2t / L> (1 + ε _i / ε _S )

Similarly, if the length L of the field plate electrode is set to 2 mu m, the insulating film 7 is made of SiO ₂ , and the composition ratio of the barrier layer 2 including the AlGaN layer is set to 0.2, the dielectric constant (ε _i , ε _S ) are 3.9 and 9.3, respectively. Therefore, it is preferable that the thickness t of the insulating film 7 is set to 1.4 µm or more.

(Third Embodiment)

8 is a schematic cross-sectional view of a structure of a junction type power HEMT according to a third embodiment of the present invention. Since the distance between the gate and the drain determines the breakdown voltage of the side power device shown in Fig. 1, it is preferable to lengthen the distance. Moreover, the distance between the source and the gate which is not related to the breakdown voltage is shortened. This contributes to reducing the ON resistance. In the power HEMT according to the third embodiment, the distance between the gate and the drain is set wider than the distance between the gate and the source to achieve high breakdown voltage and low ON resistance. More specifically, the distance Lgd is set wider than the distance Lgs. That is, the distance Lgd is the distance between the gate electrode 6 end of the drain electrode 4 side and the drain electrode 4 end of the gate electrode 6 side. The distance Lgs is the distance between the end of the gate electrode 6 on the side of the source electrode 5 and the end of the source electrode 5 on the side of the gate electrode 6.

FIG. 8 shows a case where the terminal of the semiconductor layer 3 on the drain electrode 4 side is located below the field plate electrode 8. However, the third embodiment is not limited to the above arrangement, and as shown in Fig. 1, the semiconductor layer 3 is formed such that the end of the drain electrode 4 side is aligned with the end of the gate electrode 6; Can be. As shown in FIGS. 3 and 4, the gate electrode 6 extends to the surface of the barrier layer 2 adjacent to the drain electrode 4 side of the semiconductor layer 3 or on the side of the source electrode 5. It may be formed so as to extend.

(Example 4)

9 is a schematic cross-sectional view of a structure of a junction type power HEMT according to a fourth embodiment of the present invention. The power HEMT shown in FIG. 9 differs from that shown in FIG. 1 in the following points. That is, a semiconductor layer 9 including a GaN layer (W = 0) doped with Mg as an impurity has a p-type Al _W Ga _1-W N (0≤W≤) on the backside (the other side) of the channel layer 1. It is formed as 1). The back electrode 10 made of Pt is further formed on the surface of the semiconductor layer 9. In this case, the back electrode 10 is electrically connected to the source electrode 5.

In the power HEMT having the above structure, holes generated when avalanche breakdown occurs are emitted through the semiconductor layer 9 and the back electrode 10, thus making it possible to further strengthen the avalanche resistance.

(Modification of the fourth embodiment)

10 is a sectional view showing a modification of the fourth embodiment. As shown in FIG. 10, the thickness td of the channel layer 1 is set smaller than the distance Lgd between the gate electrode 6 and the drain electrode 4. By doing so, avalanche breakdown is less likely to occur at the junction between the channel layer 1 and the semiconductor layer 9, so that the thickness of the channel layer 1 determines the breakdown voltage. In this case, since the thickness of the channel layer 1 is adjusted in the crystal growth, it is possible to manufacture an element with almost no change in the breakdown voltage. The concentration of impurities contained in the semiconductor layer 9 becomes high, and thus holes are released quickly, and eventually high avalanche resistance is expected.

In the HEMTs of the fourth embodiment and the modification, the contacts formed to the semiconductor layer 9 on the rear surface of the channel layer 1 are taken out from the rear surface of the substrate. Contact to the semiconductor layer 9 may be withdrawn from the same surface as the source electrode 5. In this case, a conductive substrate is not necessary.

The p-type semiconductor layer 9 quickly emits holes generated in the channel layer 1, and therefore, it is preferable that the semiconductor layer 9 has a band gap equal to or narrower than that of the channel layer 1. For this reason, it is preferable that the composition ratio W of the semiconductor layer 9 is equal to or smaller than the composition ratio X of the channel layer 1.

(Example 5)

11 is a schematic cross-sectional view of a structure of a lateral GaN-MISFET according to a fifth embodiment of the present invention.

In the MISFET according to the fifth embodiment, the gate insulating film 11 is added to the HEMT shown in FIG. More specifically, the gate insulating film 11 is formed so as to cover the semiconductor layer 3 and the surrounding barrier layer 2 continuously. The gate electrode 6 is formed on the gate insulating film 11 positioned on the semiconductor layer 3. In this case, the opening region is partially formed in the gate insulating film 11 so that the semiconductor layer 3 is electrically connected to the gate electrode through the opening region.

In the MISFET having the above structure, the surface of the channel layer 1 is formed of a channel inverted according to the voltage applied to the gate electrode 6. The current flowing between the source electrode 5 and the drain electrode 4 is controlled according to the formation state of the inverted channel.

In the MISFET of the above embodiment, nitride semiconductors such as Al _X Ga _1-X N, Al _Y Ga _1-Y N, and Al _Z Ga _1-Z N having a wide band gap are used as the device materials. Therefore, it is possible to improve the critical field and to realize high breakdown voltage in the device. The field plate electrode 8 is formed between the gate and the drain for determining the breakdown voltage. For this reason, when the voltage is applied, the electric field applied between the gate electrode 6 and the drain electrode 4 is reduced, and thus it is possible to prevent the reduction of the breakdown voltage. A two-dimensional electron gas with high mobility is produced at the hetero interface between the barrier layer 2 and the channel layer, so that a low ON resistance is realized.

The p-type semiconductor layer 3 is formed on the n-type barrier layer 2. Therefore, when avalanche breakdown occurs in the device, the generated holes quickly move to the p-type semiconductor layer 3, whereby a high avalanche effect is obtained.

Moreover, since the p-type semiconductor layer 3 is formed over the barrier layer 2, the effect that the gate leakage current is reduced can be obtained.

In the structure of this embodiment, the electric field at the p-n junction between the p-type semiconductor layer 3 and the n-type barrier layer 2 determines the breakdown voltage. Since the breakdown point exists in the semiconductor layer, the effect that the nonuniformity of the breakdown voltage is prevented is obtained.

In the structure of this embodiment, the yield point is in the p-n junction of the semiconductor layer. Thus, avalanche breakdown increases stably, and an element with high reliability can be realized.

Since the field plate electrode 8 is connected to the source electrode 5, the capacitance between the gate and the drain becomes small, and therefore a high speed switching operation can be realized.

Since the semiconductor layer 3 is electrically connected to the gate electrode 6, there is an effect that the following effects, i.e., a small gate leakage current can be obtained.

(First modification of the fifth embodiment)

12 shows a MISFET according to a first modification of the fifth embodiment. As shown in the MISFET shown in FIG. 12, the gate insulating film 11 may be formed without an opening region so that the semiconductor layer 3 is insulated from the gate electrode 6. Since the MISFET has such a structure, it is possible to greatly reduce the gate leakage current.

In this case, the semiconductor layer 3 is not electrically connected to the gate electrode so as to be in a potential floating state, and thus holes are not emitted to the semiconductor layer 3. For this reason, in the modified MISFET, the source electrode 5 is formed so that it can partially extend to the upper region of the semiconductor layer 3. By doing so, the semiconductor layer 3 is electrically connected with the source electrode 5. Thus, the avalanche current flows through the semiconductor layer 3 to the source electrode 5 but not to the gate electrode 6. For this reason, it is possible to reduce the load on the gate drive circuit for driving the gate electrode 6.

Moreover, it is preferable that the interface state with the semiconductor layer 3 is small. For this reason, the following film is used as the preferable gate insulating film 11. That is, an oxide film such as an Al _X Ga _2-X O ₃ film oxidizing an AlGaN layer, and an insulating film such as Al ₂ O ₃ , SiN or the like deposited by a CVD process are included.

If the concentration of impurities in the semiconductor layer 3 is too high, this becomes a factor that deteriorates the control characteristic of the inverted channel generated by the voltage applied to the gate electrode. That is, the mutual conductance of the gate electrode 6 becomes small. On the contrary, if the impurity concentration of the semiconductor layer 3 is too low, the emission resistance becomes large when releasing holes. Therefore, in consideration of the above two aspects, the impurity concentration of the semiconductor layer 3 is preferably set equal to the barrier layer 2.

(2nd modification of 5th Example)

13A and 13B are cross-sectional views and a plan view schematically illustrating a structure according to a second modification example of the power MISFET shown in FIG. 12. In the power MISFET shown in FIG. 12, the semiconductor layer 3 was formed over the entire surface in the gate width direction.

In contrast, in the power MISFET shown in Figs. 13A and 13B, the semiconductor layer 3 is formed in a rectangular shape in the gate width direction. Since the semiconductor layer 3 has the above shape, the gate threshold voltage and the ON resistance can be controlled.

Since the semiconductor layer 3 is formed in a rectangular shape, both the region where the semiconductor layer 3 is formed and the region where it is not formed exist in the lower portion of the gate. In the region where the semiconductor layer 3 is formed, the gate threshold voltage is high, and the channel resistance and offset resistance between the gate and the source are large. On the contrary, in the region where the semiconductor layer 3 is not formed below the gate, the gate threshold voltage is low, and the channel resistance and offset resistance between the gate and the source are small.

In the entire device, the former and the latter regions are operated simultaneously. Therefore, the threshold voltage or the ON resistance can be adjusted by changing the spacing and density between the rectangular semiconductor layers 3.

(Example 6)

14 is a schematic cross-sectional view illustrating a structure of a side GaN-Schottky barrier diode (SBD) according to a sixth embodiment of the present invention.

The SBD has a channel layer 1 comprising an undoped GaN layer, like the FET shown in FIG. A barrier layer 2 comprising an n-type Al _0.2 Ga _0.8 N layer (Y = 0.2) is formed on the surface of the channel layer 1. Moreover, a plurality of semiconductor layers 3 comprising a p-type Al _0.1 Ga _0.9 N layer is selectively formed on the barrier layer 2.

An anode electrode 12 (A: second electrode) made of Ni / Au is formed to continuously cover the semiconductor layer 3 and the surrounding barrier layer 2. An insulating film 7 is formed on the barrier layer 2 so as to contact the anode electrode 12. The field plate electrode 8 made of Ni / Au is formed on the insulating film 7. The field plate electrode 8 is electrically connected to the anode electrode 12. In addition, a cathode electrode 13 (K: first electrode) made of Ti / Al / Ni / Au is formed on the barrier layer 2 in a state separated from the anode electrode 12.

In the SBD of the sixth embodiment, an n-AlGaN / GaN heterostructure including the barrier layer 2 and the channel layer 1 is employed as in the HEMT described above. By doing so, it is possible to realize high breakdown voltage and very low ON resistance.

A semiconductor layer 3 comprising a p-AlGaN layer is formed over the barrier layer 2 comprising an n-AlGaN layer. By doing so, holes are safely released when avalanche breakdown occurs, thus high voltage effects can be expected. Since the semiconductor layer 3 is formed in this manner, it is possible to reduce the Schottky junction region which directly contacts the anode electrode 12 and the barrier layer, and it is possible to reduce the reverse leakage current.

(Example 7)

15 is a schematic cross-sectional view illustrating a structure of a Schottky barrier diode (SBD) according to a seventh embodiment of the present invention.

In the SBD of the seventh embodiment, the semiconductor layer 3 is formed at the Schottky junction end. In this case, the end of the semiconductor layer 3 on the cathode electrode 13 side is located between the end of the field plate electrode 8 on the cathode electrode 13 side and the end of the anode electrode 12 on the cathode electrode 13 side.

FIG. 16A is an enlarged cross-sectional view of an end of the semiconductor layer 3 shown in FIG. 15, and FIG. 16B shows an electric field distribution in the barrier layer 2 when the SBD of FIG. 15 operates. Characteristic diagram.

As shown in FIG. 15, the semiconductor layer 3 is formed such that the end region on the side of the cathode electrode 13 is located below the field plate electrode 8. By doing so, as shown in Fig. 16B, the field concentration point is located at the end of the semiconductor layer 3 and the end of the field plate electrode 8. In FIG. 16B, the characteristic curve 23 shows a case where the insulating film 7 is formed thick with a predetermined thickness, while the characteristic curve 24 shows a case where the insulating film 7 is formed thin in a predetermined thickness.

More specifically, as described in the HEMT of the second embodiment, the thickness t of the insulating film 7 in the SBD is set such that the relative equations 5 and 7 are satisfied. By doing so, it is possible to ensure avalanche resistance and avoid dielectric breakdown.

The present invention has been described based on the first to seventh embodiments. The present invention is not limited to the above embodiments, and is also applicable to modifications that can be easily invented by those skilled in the art.

For example, the semiconductor layer 3 including the p-AlGaN layer used for emitting holes preferably has a narrower band gap than the barrier layer 2 including the n-AlGaN layer in terms of hole emission. . That is, it is preferable that the composition ratio of Al is small and a p-GaN layer can be used. In order to reduce the contact resistance to the semiconductor layer 3, a semiconductor layer such as an InGaN layer having a narrow band gap is used as the contact layer. The contact layer may be formed between the gate electrode 6 or the anode electrode 12 and the semiconductor layer 3.

In this embodiment, a combination of AlGaN / GaN was employed as the device material. In such a case, a combination of GaN / InGaN or AlN / AlGaN may be employed.                 

The invention is not limited to monopolar devices such as junction FETs and the like. In this case, the present invention is also easily applicable to bipolar devices such as pin diodes and IGBTs employing the p layer on the drain side of the MISFET as long as the device is lateral.

As is clear from the above description, the present invention makes it possible to obtain a lateral GaN based power device having a high avalanche resistance, a high breakdown voltage, and a very low ON resistance.

Claims (17)

A first semiconductor layer of undoped Al _X Ga _1-X N (0 ≦ _X ≦ 1); A second semiconductor layer of undoped or n-type Al _Y Ga _1-Y N (0 ≦ _Y ≦ ₁ , X <Y) formed on one surface of the first semiconductor layer; A third semiconductor layer of p-type Al _Z Ga _1-Z N (0 ≦ _Z ≦ ₁ ) selectively formed over the second semiconductor layer; A first electrode disposed on one of both sides of the third semiconductor layer and formed on the second semiconductor layer; An insulating film formed over the second semiconductor layer adjacent to the third semiconductor layer, at least between the third semiconductor layer and the first electrode; A power semiconductor device comprising a field plate electrode formed over an insulating film. The method of claim 1, A second electrode on the other of both sides of the third semiconductor layer and formed on the second semiconductor layer; It further comprises a control electrode formed on the third semiconductor layer, A power semiconductor device, wherein a field plate electrode is electrically connected to a control electrode or a second electrode. 3. The power semiconductor device according to claim 2, wherein the third semiconductor layer end on the first electrode side is located between the control electrode end on the first electrode side and the field plate electrode end on the first electrode side. The thickness of the insulating film under the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , the dielectric constant of the second semiconductor layer is set to ε _S , and the first electrode side. When the distance between the end of the third semiconductor layer of and the end of the control electrode on the first electrode side is set to L, the thickness t of the insulating film ε _S t> ε _i L A power semiconductor device, characterized in that set to satisfy the relationship of. The thickness of the insulating film under the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , the dielectric constant of the second semiconductor layer is set to ε _S , and the first electrode side. When the distance between the end of the third semiconductor layer of and the end of the control electrode on the first electrode side is set to L, the thickness t of the insulating film 2t / L> (1 + ε _i / ε _S ) A power semiconductor device, characterized in that set to satisfy the relationship of. The power semiconductor device of claim 2, wherein a distance between the first electrode and the control electrode is wider than a distance between the second electrode and the control electrode. The power semiconductor device according to claim 2, further comprising a gate insulating film formed between the control electrode and the third semiconductor layer. 8. The power semiconductor device of claim 7, wherein the second electrode is electrically connected to the third semiconductor layer. The power semiconductor device according to claim 8, wherein the third semiconductor layer is formed in a rectangular shape in a direction perpendicular to the first and second electrodes arranged in parallel. The semiconductor device according to claim 2, further comprising a fourth semiconductor layer of p-type Al _W Ga _1-W N (0≤W≤1, W≤X) formed on the other surface of the first semiconductor layer, And the fourth semiconductor layer is electrically connected to the second electrode. The power semiconductor device of claim 10, wherein a thickness of the first semiconductor layer is smaller than a gap between the control electrode and the first electrode. A first semiconductor layer of undoped Al _X Ga _1-X N (0 ≦ _X ≦ 1); A second semiconductor layer of undoped or n-type Al _Y Ga _1-Y N (0 ≦ _Y ≦ ₁ , X <Y) formed on the surface of the first semiconductor layer; A third semiconductor layer of p-type Al _Z Ga _1-Z N (0 ≦ _Z ≦ ₁ ) selectively formed over the second semiconductor layer; An insulating film formed on the second semiconductor layer; A field plate electrode formed over the insulating film; A first electrode formed on the second semiconductor layer; And a second electrode formed on the third semiconductor layer. 13. The power semiconductor device of claim 12, wherein the second electrode is electrically connected to the second semiconductor layer. 13. The power semiconductor device of claim 12, wherein the second electrode is electrically connected to the field plate electrode. 13. The power semiconductor device according to claim 12, wherein the third semiconductor layer end on the first electrode side is located between the field plate electrode end on the first electrode side and the second electrode end on the first electrode side. 13. The film of claim 12, wherein the thickness of the insulating film under the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , the dielectric constant of the second semiconductor layer is set to ε _S , and the first electrode side. When the distance between the end of the third semiconductor layer and the end of the first electrode side control electrode is set to L, the thickness t of the insulating film ε _S t> ε _i L A power semiconductor device, characterized in that set to satisfy the relationship of. 13. The film of claim 12, wherein the thickness of the insulating film under the field plate electrode is set to t, the dielectric constant of the insulating film is set to ε _i , the dielectric constant of the second semiconductor layer is set to ε _S , and the first electrode side. When the distance between the end of the third semiconductor layer of and the end of the control electrode on the first electrode side is set to L, the thickness t of the insulating film 2t / L> (1 + ε _i / ε _S ) A power semiconductor device, characterized in that set to satisfy the relationship of.

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