JP6163956B2 - Compound semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a compound semiconductor device and a manufacturing method thereof.

  Compound semiconductor devices, particularly nitride semiconductor devices, have been actively developed as high breakdown voltage and high output semiconductor devices utilizing characteristics such as high saturation electron velocity and wide band gap. As nitride semiconductor devices, many reports have been made on field effect transistors, in particular, high electron mobility transistors (HEMTs). In particular, AlGaN / GaN HEMTs using GaN as an electron transit layer and AlGaN as an electron supply layer are attracting attention. In AlGaN / GaN.HEMT, strain caused by the difference in lattice constant between GaN and AlGaN is generated in AlGaN. A high-concentration two-dimensional electron gas (2DEG) is obtained by the piezoelectric polarization generated thereby and the spontaneous polarization of AlGaN. Therefore, high breakdown voltage and high output can be realized.

JP 2003-59943 A JP 2008-98434 A

Nitride semiconductor devices represented by AlGaN / GaN HEMT are expected to be applied as high breakdown voltage and high output power devices, but their performance has not yet reached the theoretical limit, and further performance improvement can be achieved. It is desired.
One cause of the breakdown voltage drop in nitride semiconductor devices is that when a high voltage is applied to the drain electrode in a pinch-off state in an ordinary semiconductor structure, an electric field concentrates on the gate electrode end on the drain electrode side, causing the device to break down. It has been reported that As a solution to this, there are attempts to reduce the electric field density by extending the separation distance between the gate electrode and the drain electrode, and a technique for relaxing the electric field as a field plate structure in which the gate electrode partially extends toward the drain electrode.

However, there is a problem that the technique for increasing the separation distance between the gate electrode and the drain electrode and improving the device breakdown voltage has a direct relationship with the miniaturization of a device that is a high-frequency application technique. In the technique using the field plate structure, the capacitance between the gate and the drain is increased by the field plate, and there is a concern about the deterioration of the high frequency characteristics such as the reduction of the cutoff frequency (f _T ) and the maximum oscillation frequency (f _MAX ).

  The present invention has been made in view of the above problems, and provides a highly reliable compound semiconductor device that achieves high breakdown voltage and high output with excellent high-frequency characteristics and a method for manufacturing the same, while reducing the device size. The purpose is to provide.

One aspect of the compound semiconductor device includes a compound semiconductor layer, an electrode above the compound semiconductor layer, and a p-type semiconductor covered by the electrode from one side surface to the upper surface above the compound semiconductor layer. The electrode has an electrode length defined by a lower portion of the electrode, and the p-type semiconductor includes a first portion in which the p-type impurity is activated and a second portion in which the p-type impurity is inactivated. And having a part .

One aspect of a method for manufacturing a compound semiconductor device includes a step of forming a compound semiconductor layer, a step of forming a p-type semiconductor above the compound semiconductor layer, and covering the p-type semiconductor from one side surface to an upper surface. Forming an electrode, wherein the electrode has an electrode length defined by a lower portion of the electrode , the p-type semiconductor has a first portion in which a p-type impurity is activated, and the p-type impurity is inactive A second portion .

  According to the above aspects, a highly reliable compound semiconductor device that achieves high breakdown voltage and high output with excellent high-frequency characteristics can be obtained even though the device size is reduced.

It is a schematic sectional drawing which shows the manufacturing method of AlGaN / GaN * HEMT by 1st Embodiment to process order. FIG. 2 is a schematic cross-sectional view illustrating the AlGaN / GaN HEMT manufacturing method according to the first embodiment in the order of steps, following FIG. 1. It is a schematic sectional drawing which shows in order the main process of the manufacturing method of AlGaN / GaN * HEMT by 2nd Embodiment. In AlGaN / GaN HEMT by 2nd Embodiment, it is a characteristic view shown based on the comparison with a comparative example about the electric field strength at the time of power-off. In AlGaN / GaN HEMT by 2nd Embodiment, it is a characteristic view which shows the relationship with the drain voltage Vd of the drain current Id at the time of pinch-off. It is a connection diagram which shows schematic structure of the power supply device by 3rd Embodiment. It is a connection diagram which shows schematic structure of the high frequency amplifier by 4th Embodiment.

(First embodiment)
In the present embodiment, a nitride semiconductor AlGaN / GaN.HEMT that is a compound semiconductor is disclosed as a semiconductor device.
1 to 2 are schematic cross-sectional views showing the method of manufacturing the AlGaN / GaN HEMT according to the first embodiment in the order of steps.

First, as shown in FIG. 1A, a compound semiconductor multilayer structure 2 is formed as a stacked body of a plurality of compound semiconductor layers on, for example, a semi-insulating SiC substrate 1 as a growth substrate. As the growth substrate, a Si substrate, a sapphire substrate, a GaAs substrate, a GaN substrate, or the like may be used instead of the SiC substrate. Further, the conductivity of the substrate may be semi-insulating or conductive.
The compound semiconductor multilayer structure 2 includes a buffer layer 2a, an electron transit layer 2b, a spacer layer 2c, an electron supply layer 2d, and a cap layer 2e.

  In the compound semiconductor multilayer structure 2, two-dimensional electron gas (2DEG) is generated near the interface between the electron transit layer 2b and the electron supply layer 2d (more precisely, near the interface between the electron transit layer 2b and the spacer layer 2c). . This 2DEG is generated based on the difference in lattice constant between the compound semiconductor (here, GaN) of the electron transit layer 2b and the compound semiconductor (here, AlGaN) of the electron supply layer 2d.

More specifically, the following compound semiconductors are grown on the SiC substrate 1 by, for example, metal organic vapor phase epitaxy (MOVPE). Instead of the MOVPE method, a molecular beam epitaxy (MBE) method or the like may be used.
On the SiC substrate 1, AlN is about 200 nm thick, i (Intensive Undoped) -GaN is about 1 μm thick, i-AlGaN is about 5 nm thick, and n-AlGaN is about 30 nm thick. , N-GaN is sequentially grown to a thickness of about 10 nm. Thereby, the buffer layer 2a, the electron transit layer 2b, the spacer layer 2c, the electron supply layer 2d, and the cap layer 2e are formed. As the buffer layer 2a, AlGaN may be used instead of AlN, or GaN may be grown at a low temperature.

As growth conditions for AlN, a mixed gas of trimethylaluminum (TMAl) gas and ammonia (NH ₃ ) gas is used as a source gas. As a growth condition for GaN, a mixed gas of trimethylgallium (TMGa) gas and NH ₃ gas is used as a source gas. As growth conditions for AlGaN, a mixed gas of TMAl gas, TMGa gas, and NH ₃ gas is used as a source gas. The presence / absence and flow rate of TMAl gas as an Al source and TMGa gas as a Ga source are appropriately set according to the compound semiconductor layer to be grown. The flow rate of ammonia gas, which is a common raw material, is about 100 ccm to 10 LM. The growth pressure is about 50 Torr to 300 Torr, and the growth temperature is about 1000 ° C. to 1200 ° C.

When growing AlGaN and GaN as n-type, that is, when forming the electron supply layer 2d and the cap layer 2e, for example, SiH ₄ gas containing Si as an n-type impurity is added to the source gas at a predetermined flow rate, GaN and AlGaN are doped with Si. The doping concentration of Si is about 1 × 10 ¹⁸ / cm ^{3 to} about 1 × 10 ²⁰ / cm ³ , for example, about 5 × 10 ¹⁸ / cm ³ .

Subsequently, as shown in FIG. 1B, an element isolation region 3 is formed.
Specifically, for example, argon (Ar) is ion-implanted into a portion to be an inactive region of the compound semiconductor multilayer structure 2. Thereby, the element isolation region 3 is formed in the compound semiconductor multilayer structure 2 and the surface layer portion of the SiC substrate 1. The element isolation region 3 defines an AlGaN / GaN.HEMT element region (transistor region) on the compound semiconductor multilayer structure 2.
The element isolation may be performed by using, for example, an STI (Shallow Trench Isolation) method instead of the above-described implantation method. At this time, for example, a chlorine-based etching gas is used for the dry etching of the compound semiconductor multilayer structure 2.

Subsequently, as shown in FIG. 1C, the source electrode 4 and the drain electrode 5 are formed.
In detail, first, each formation planned site | part of the source electrode and drain electrode in the cap layer 2e of the compound semiconductor laminated structure 2 is removed by lithography and dry etching. As a result, electrode recesses 2A and 2B are formed in the cap layer 2e of the compound semiconductor multilayer structure 2.
Next, a resist mask for forming the source electrode and the drain electrode is formed. A resist is applied onto the compound semiconductor multilayer structure 2, and the resist is processed by lithography. Thus, openings for exposing the electrode recesses 2A and 2B are formed. Thus, a resist mask having the opening is formed.

  Using this resist mask, as an electrode material, for example, Ti / Al (Ti is the lower layer and Al is the upper layer), for example, by evaporation, a resist mask including the inside of the opening that exposes the respective formation sites of the source electrode and the drain electrode Deposit on top. The thickness of Ti is about 20 nm, and the thickness of Al is about 200 nm. The resist mask and Ti / Al deposited thereon are removed by a lift-off method. Thereafter, the SiC substrate 1 is heat-treated in a nitrogen atmosphere, for example, at a temperature of about 400 ° C. to 1000 ° C., for example, about 600 ° C., and the remaining Ti / Al is brought into ohmic contact with the electron supply layer 2c. If an ohmic contact with the Ti / Al electron supply layer 2d is obtained, heat treatment may be unnecessary. Thus, the source electrode 4 and the drain electrode 5 in which the electrode recesses 2A and 2B are embedded and in ohmic contact with the electron supply layer 2d are formed.

Subsequently, as shown in FIG. 2A, an inactive p-type semiconductor layer 10 is formed on the compound semiconductor multilayer structure 2.
Specifically, first, p-type GaN is deposited on the entire surface of the compound semiconductor multilayer structure 2 by a MOVPE method to a thickness of about 5 nm or less, for example, about 3 nm. When p-type GaN is grown, a p-type impurity such as one selected from Mg and C is added to the GaN source gas. In this embodiment, Mg is used as the p-type impurity. Mg is added to the source gas at a predetermined flow rate, and GaN is doped with Mg. The doping concentration of Mg is, for example, about 1 × 10 ¹⁹ / cm ^{3 to} about 1 × 10 ²¹ / cm ³ , for example, about 1 × 10 ¹⁹ / cm ³ . When the doping concentration is lower than about 1 × 10 ¹⁹ / cm ³ , the p-type is not sufficient and normally-on. If it is higher than about 1 × 10 ²¹ / cm ³ , the crystallinity is lost and sufficient characteristics cannot be obtained.

  Next, the deposited p-type GaN is processed by lithography and dry etching, and the p-type GaN is left only at a predetermined portion between the source electrode 4 and the drain electrode on the compound semiconductor multilayer structure 2. As described above, the inactive p-type semiconductor layer 10 is formed on the compound semiconductor multilayer structure 2.

Subsequently, as shown in FIG. 2B, an active p-type semiconductor layer 6 is formed.
Specifically, the inactive p-type semiconductor layer 10 is annealed in a nitrogen atmosphere at about 700 ° C. to 1000 ° C., here 900 ° C. Thereby, the inactive p-type semiconductor layer 10 is activated, and the active p-type semiconductor layer 6 is formed.

Subsequently, as shown in FIG. 2C, a gate electrode 7 is formed.
Specifically, a resist mask is formed to form a gate electrode. Apply resist on the entire surface. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. The applied resist is processed by lithography. As described above, a resist mask having an opening that exposes a portion where the gate electrode is to be formed is formed.

  Next, using the above resist mask, as an electrode material, for example, Ni / Au (Ni is a lower layer and Au is an upper layer) is deposited on the resist mask including each opening, for example, by vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 7 covering the active p-type semiconductor layer 6 is formed. The gate electrode 7 is formed so as to cover the active p-type semiconductor layer 6 from the side surface on the source electrode 4 side to the upper surface. The gate electrode 7 is in contact with the active p-type semiconductor layer 6 in parallel at the lower side, and is in contact with the surface of the compound semiconductor multilayer structure 2 at the bottom of the lower portion, and the gate length Lg is defined in the lower portion. The

  Thereafter, the AlGaN / GaN HEMT according to the present embodiment is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 7.

  In the AlGaN / GaN.HEMT according to the present embodiment, the active p-type semiconductor layer 6 is provided on the compound semiconductor multilayer structure 2 so as to be aligned with the gate electrode 7 on the drain electrode 5 side of the gate electrode 7. With this configuration, due to the presence of the active p-type semiconductor layer 6, electric field concentration at the drain electrode side end of the gate electrode 7 is alleviated, and the breakdown voltage of the device in the off state is improved. According to the present embodiment, a highly reliable AlGaN / GaN HEMT capable of achieving a high breakdown voltage and high output with excellent high-frequency characteristics and achieving a normally-off operation is achieved although the device size is reduced.

(Second Embodiment)
In this embodiment, AlGaN / GaN.HEMT is disclosed as a semiconductor device as in the first embodiment, but is different in that the configuration of the p-type semiconductor layer is different.
FIG. 3 is a schematic cross-sectional view showing the main steps of the AlGaN / GaN HEMT manufacturing method according to the second embodiment.

  In the present embodiment, first, similarly to the first embodiment, the respective steps of FIGS. 1A to 2A are sequentially performed. At this time, the inactive p-type semiconductor layer 10 is formed on the compound semiconductor multilayer structure 2.

Subsequently, as shown in FIG. 3A, a protective film 21 is formed.
Specifically, an insulating film, here a SiN film, is deposited by CVD or the like over the entire surface so as to cover the inactive p-type semiconductor layer 10. The SiN film is processed by lithography and dry etching to form the opening 21a. A surface portion corresponding to half of the inactive p-type semiconductor layer 10 on the source electrode 4 side of the inactive p-type semiconductor layer 10 is exposed from the opening 21a. Thus, the protective film 21 having the opening 21a is formed.

Subsequently, as shown in FIG. 3B, a p-type semiconductor layer 22 is formed.
Specifically, the inactive p-type semiconductor layer 10 is annealed in a nitrogen atmosphere at about 700 ° C. to 1000 ° C., here 900 ° C. By the annealing process, the inactive p-type semiconductor layer 10 is activated only at a portion corresponding to half of the inactive p-type semiconductor layer 10 on the source electrode 4 side, which is a portion exposed from the opening 21 a of the protective film 21. The portion corresponding to half of the inactive p-type semiconductor layer 10 on the drain electrode 5 side is not activated because the surface is covered with the protective film 21, and the inactive initial state is maintained. As described above, one half of the source electrode 4 side is integrated as an active p-type semiconductor layer 22a that is the first portion, and the other half of the drain electrode 5 side is integrated as an inactive p-type semiconductor layer 22b that is the second portion. The p-type semiconductor layer 22 is formed.
After the annealing process, the protective film 21 is removed by a predetermined wet process.

Subsequently, as shown in FIG. 3C, a gate electrode 23 is formed.
Specifically, a resist mask is formed to form a gate electrode. Apply resist on the entire surface. Here, for example, a two-layer resist having a cage structure suitable for the vapor deposition method and the lift-off method is used. The applied resist is processed by lithography. As described above, a resist mask having an opening that exposes a portion where the gate electrode is to be formed is formed.

  Next, using the above resist mask, as an electrode material, for example, Ni / Au (Ni is a lower layer and Au is an upper layer) is deposited on the resist mask including each opening, for example, by vapor deposition. The thickness of Ni is about 30 nm, and the thickness of Au is about 400 nm. The resist mask and Ni / Au deposited thereon are removed by a lift-off method. Thus, the gate electrode 23 covering the p-type semiconductor layer 22 is formed. The gate electrode 23 is formed so as to cover the p-type semiconductor layer 22 from the side surface (side surface on the source electrode 4 side) of the active p-type semiconductor layer 22a to the upper surface. The gate electrode 23 is in contact with the active p-type semiconductor layer 22a in parallel at the lower side surface, and is in contact with the surface of the compound semiconductor multilayer structure 2 at the bottom surface of the lower portion. The gate length Lg is defined in the lower portion. The

  Thereafter, the AlGaN / GaN HEMT according to the present embodiment is formed through various processes such as electrical connection of the source electrode 4, the drain electrode 5, and the gate electrode 23.

  Hereinafter, the operation and effect of the AlGaN / GaN HEMT manufactured as described above will be described based on a comparison with the comparative example.

  FIG. 4 is a characteristic diagram showing the electric field strength when the power is turned off in the AlGaN / GaN HEMT according to the present embodiment, based on a comparison with a comparative example. The electric field strength is shown in relation to the position between the source electrode and the drain electrode. As a comparative example, an AlGaN / GaN HEMT having no p-type semiconductor layer 22 in the present embodiment is illustrated.

  In the AlGaN / GaN HEMT of the comparative example, a large electric field concentration occurs at the drain electrode side end of the gate electrode. On the other hand, in the AlGaN / GaN HEMT of this embodiment, a spatial electron density distribution is formed in 2DEG by the active p-type semiconductor layer 22a and the inactive p-type semiconductor layer 22b of the p-type semiconductor layer 22. . Due to the presence of the inactive p-type semiconductor layer 22b, an electric field is gently distributed from the p-type semiconductor layer 22 to the source electrode 4 and from the p-type semiconductor layer 22 to the drain electrode 5, and the gate electrode is thereby distributed. It can be confirmed that the electric field at the drain electrode side end of 23 is greatly relaxed as compared with the comparative example.

  FIG. 5 is a characteristic diagram showing the relationship between the drain current Id and the drain voltage Vd at the time of pinch-off in the AlGaN / GaN HEMT according to the present embodiment. As a comparative example, similarly to the case of FIG. 4, an AlGaN / GaN HEMT having a configuration without the p-type semiconductor layer in the present embodiment is illustrated.

In the present embodiment, it was confirmed that the withstand voltage was significantly improved as compared with the comparative example. From this, it can be seen that the AlGaN / GaN HEMT of this embodiment greatly improves the high-frequency characteristics such as the cutoff frequency (f _T ) and the maximum oscillation frequency (f _MAX ).

  As described above, according to the present embodiment, the device size can be reduced, but a high withstand voltage and high output can be achieved with excellent high-frequency characteristics, and a highly reliable AlGaN / GaN HEMT capable of obtaining a normally-off operation. Is realized.

(Third embodiment)
In the present embodiment, a power supply device to which the AlGaN / GaN HEMT according to the first or second embodiment is applied is disclosed.
FIG. 6 is a connection diagram illustrating a schematic configuration of the power supply device according to the third embodiment.

The power supply device according to this embodiment includes a high-voltage primary circuit 31 and a low-voltage secondary circuit 32, and a transformer 33 disposed between the primary circuit 31 and the secondary circuit 32. The
The primary circuit 31 includes an AC power supply 34, a so-called bridge rectifier circuit 35, and a plurality (four in this case) of switching elements 36a, 36b, 36c, and 36d. The bridge rectifier circuit 35 includes a switching element 36e.
The secondary side circuit 32 includes a plurality (three in this case) of switching elements 37a, 37b, and 37c.

  In the present embodiment, the switching elements 36a, 36b, 36c, 36d, 36e of the primary side circuit 31 are the AlGaN / GaN HEMTs according to the first or second embodiment. On the other hand, the switching elements 37a, 37b, and 37c of the secondary circuit 32 are normal MIS • FETs using silicon.

  In the present embodiment, a highly reliable AlGaN / GaN HEMT capable of achieving a high breakdown voltage and a high output with excellent high frequency characteristics and obtaining a normally-off operation is applied to a high voltage circuit, although the device size is reduced. As a result, a highly reliable high-power power supply circuit is realized.

(Fourth embodiment)
In the present embodiment, a high-frequency amplifier to which the AlGaN / GaN HEMT according to the first or second embodiment is applied is disclosed.
FIG. 7 is a connection diagram illustrating a schematic configuration of the high-frequency amplifier according to the fourth embodiment.

The high-frequency amplifier according to the present embodiment includes a digital predistortion circuit 41, mixers 42a and 42b, and a power amplifier 43.
The digital predistortion circuit 41 compensates for nonlinear distortion of the input signal. The mixer 42a mixes an input signal with compensated nonlinear distortion and an AC signal. The power amplifier 43 amplifies the input signal mixed with the AC signal, and includes the AlGaN / GaN HEMT according to the first or second embodiment. In FIG. 7, for example, by switching the switch, the output side signal is mixed with the AC signal by the mixer 42b and sent to the digital predistortion circuit 41.

  In the present embodiment, a highly reliable AlGaN / GaN HEMT that can achieve a high withstand voltage and high output with excellent high frequency characteristics and obtain a normally-off operation is applied to a high frequency amplifier, although the device size is reduced. As a result, a high-reliability, high-voltage high-frequency amplifier is realized.

(Other embodiments)
In the first to fourth embodiments, AlGaN / GaN.HEMT is exemplified as the compound semiconductor device. As a compound semiconductor device, besides the AlGaN / GaN.HEMT, the following HEMT can be applied.

・ Other HEMT examples 1
In this example, InAlN / GaN.HEMT is disclosed as a compound semiconductor device.
InAlN and GaN are compound semiconductors whose lattice constants can be made close to each other depending on the composition. In this case, in the first embodiment and the modification described above, the electron transit layer is formed of i-GaN, the spacer layer is formed of i-AlN, the electron supply layer is formed of n-InAlN, and the cap layer is formed of n-GaN. In this case, since the piezoelectric polarization hardly occurs, the two-dimensional electron gas is mainly generated by the spontaneous polarization of InAlN.

  According to this example, similar to the AlGaN / GaN HEMT described above, the device size can be reduced, but high withstand voltage and high output can be achieved with excellent high frequency characteristics, and normally-off operation is achieved. / GaN HEMT is realized.

・ Other HEMT examples 2
In this example, InAlGaN / GaN.HEMT is disclosed as a compound semiconductor device.
GaN and InAlGaN are compound semiconductors in which the latter can make the lattice constant smaller by the composition than the former. In this case, in the first embodiment and the modification described above, the electron transit layer is formed of i-GaN, the spacer layer is formed of i-AlN, the electron supply layer is formed of n-InAlGaN, and the cap layer is formed of n-GaN.

  According to this example, similar to the AlGaN / GaN HEMT described above, the device size can be reduced, but high withstand voltage and high output can be achieved with excellent high frequency characteristics, and normally-off operation is achieved. / GaN HEMT is realized.

  Hereinafter, various aspects of the compound semiconductor device, the manufacturing method thereof, the power supply device, and the high-frequency amplifier will be collectively described as appendices.

(Appendix 1) a compound semiconductor layer;
An electrode above the compound semiconductor layer;
A p-type semiconductor covered with the electrode extending from one side surface to the upper surface above the compound semiconductor layer;
The compound semiconductor device, wherein an electrode length of the electrode is defined by a lower portion of the electrode.

  (Additional remark 2) The said p-type semiconductor has the 1st part by which the p-type impurity was activated, and the 2nd part by which the p-type impurity was made inactive, The additional remark 1 characterized by the above-mentioned Compound semiconductor device.

  (Supplementary note 3) The compound semiconductor device according to supplementary note 2, wherein the p-type semiconductor has the first portion and the second portion arranged in parallel.

(Appendix 4) Any one of appendices 1 to 3, wherein the p-type semiconductor has a p-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less. The compound semiconductor device described in 1.

(Appendix 5) A step of forming a compound semiconductor layer;
Forming a p-type semiconductor above the compound semiconductor layer;
Forming an electrode that covers the p-type semiconductor from one side surface to the upper surface,
The method of manufacturing a compound semiconductor device, wherein an electrode length of the electrode is defined by a lower portion of the electrode.

  (Supplementary note 6) The p-type semiconductor includes a first portion in which a p-type impurity is activated and a second portion in which the p-type impurity is inactivated. A method for manufacturing a compound semiconductor device.

  (Supplementary note 7) The method for manufacturing a compound semiconductor device according to supplementary note 6, wherein the p-type semiconductor has the first portion and the second portion arranged in parallel.

(Appendix 8) In any one of appendices 5 to 7, the p-type semiconductor has a p-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less. The manufacturing method of the compound semiconductor device of description.

(Supplementary note 9) A power supply circuit including a transformer and a high-voltage circuit and a low-voltage circuit across the transformer,
The high-voltage circuit has a transistor,
The transistor is
A compound semiconductor layer;
An electrode above the compound semiconductor layer;
A p-type semiconductor covered with the electrode extending from one side surface to the upper surface above the compound semiconductor layer;
The power supply circuit according to claim 1, wherein an electrode length of the electrode is defined by a lower portion of the electrode.

(Appendix 10) A high frequency amplifier that amplifies and outputs an input high frequency voltage,
Has a transistor,
The transistor is
A compound semiconductor layer;
An electrode above the compound semiconductor layer;
A p-type semiconductor covered with the electrode extending from one side surface to the upper surface above the compound semiconductor layer;
The high-frequency amplifier according to claim 1, wherein an electrode length of the electrode is defined by a lower portion of the electrode.

DESCRIPTION OF SYMBOLS 1 SiC substrate 2 Compound semiconductor laminated structure 2a Buffer layer 2b Electron travel layer 2c Spacer layer 2d Electron supply layer 2e Cap layer 3 Element isolation region 4 Source electrode 2A, 2B Electrode recess 5 Drain electrode 6 Active p-type semiconductor layer 10 Inactive p-type semiconductor layers 7 and 23 gate electrode 21 protective film 21a opening 22 p-type semiconductor layer 22a active p-type semiconductor layer 22b inactive p-type semiconductor layer 31 primary side circuit 32 secondary side circuit 33 transformer 34 AC power supply 35 bridge rectifier circuit 36a, 36b, 36c, 36d, 36e, 37a, 37b, 37c Switching element 41 Digital predistortion circuit 42a, 42b Mixer 43 Power amplifier

Claims (6)

A compound semiconductor layer;
An electrode above the compound semiconductor layer;
A p-type semiconductor covered with the electrode extending from one side surface to the upper surface above the compound semiconductor layer;
The electrode has an electrode length defined by the lower part of the electrode ,
The p-type semiconductor has a first portion in which a p-type impurity is activated and a second portion in which the p-type impurity is inactivated . 2. The compound semiconductor device according to claim 1 , wherein the p-type semiconductor has the first portion and the second portion arranged in parallel. The p-type semiconductor, the compound semiconductor device according to claim 1 or 2, characterized in that the concentration of the p-type impurity is a 1 × 10 ²¹ / cm ³ or less 1 × 10 ¹⁹ / cm ³ or more. Forming a compound semiconductor layer;
Forming a p-type semiconductor above the compound semiconductor layer;
Forming an electrode that covers the p-type semiconductor from one side surface to the upper surface,
The electrode has an electrode length defined by the lower part of the electrode ,
The method of manufacturing a compound semiconductor device, wherein the p-type semiconductor includes a first portion in which a p-type impurity is activated and a second portion in which the p-type impurity is deactivated . The method of manufacturing a compound semiconductor device according to claim 4 , wherein the p-type semiconductor has the first portion and the second portion arranged in parallel. 6. The method of manufacturing a compound semiconductor device according to claim 4 , wherein the p-type semiconductor has a p-type impurity concentration of 1 × 10 ¹⁹ / cm ³ or more and 1 × 10 ²¹ / cm ³ or less. .

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