KR100462317B1 - AC PD Drive - Google Patents

Abstract

The present invention relates to an AC PDP driving apparatus capable of efficiently controlling a memory for storing an image signal required for driving a high resolution AC PDP regardless of the characteristics of a scanning method.

To this end, the present invention is implemented with a wired logic (Data Wire register) 102 to rearrange the image signal (RGB) in order from the upper bit to the lower bit in order of the arrangement of each pixel of the PDP (101) and A memory 103 for storing the data arranged by the data array register 102 and a memory address ROM for storing the address of the data stored in the memory 103 in a chronological order of memory reference according to a scanning method. (Read Only Memory) 104 and a controller 105 which refers to a memory address stored in the memory address ROM 104 according to a scanning method and outputs a corresponding image signal to the PDP 101. .

Description

AC PD Drive

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a driving device of a plasma display panel (PDP), which is one of flat panel displays, and has a memory for storing an image signal required to drive a high resolution AC PDP regardless of scanning characteristics. The present invention relates to an AC PDP driving apparatus that can be efficiently controlled.

As is well known, a plasma display device (PDP) obtains a discharge by adjusting a voltage applied between vertical and horizontal electrodes of a cell constituting a pixel, and the amount of discharged light is controlled by varying the length of discharge time in the cell. .

The full screen includes a write pulse for inputting a digital image signal to vertical and horizontal electrodes of each cell, a scan pulse for scanning, a sustain pulse for maintaining a discharge, and a discharge. It is obtained by driving the matrix type by applying an erase pulse to stop the discharge of the cells.

In addition, the gray level required for image display is made by varying the length of time each cell is discharged within a given time (1/30 second for NTSC TV signal) required to display the entire image. Implement

In this case, the brightness of the screen is determined by the brightness when each cell is driven to the maximum, and in order to increase the brightness, the discharge time of the cell can be maintained as long as possible within a given time to compose one screen. The drive circuit must be designed.

Contrast, which is the difference in contrast, is determined by the brightness and brightness of the background of the lamp, and in order to increase the contrast, the background needs to be darkened as well as the brightness is increased. Flat display devices for high-definition television (HDTV) require 256 gray levels, resolution of 1280 x 1024 or higher, and contrast under 200 lux lighting requires 100: 1 or higher.

Therefore, an image digital signal necessary for displaying 256 gray levels requires an 8-bit signal for each RGB, and the discharge time of the cell must be kept as long as possible in order to obtain the required luminance and contrast.

The gray scale includes a line scanning method and a subfield method.

The sub-scanning method currently attracting the most attention in the AC PDP is that the 8-bit digital video signal is collected between the same weight bits from the MSB to the LSB. The sub-screens are composed by scanning for T / 2, T / 4, ..., T / 128, respectively, and 256 gray scales are realized by using the integral effect of the eye on the light emitted from each sub-screen.

However, since the PDP must be driven in a matrix manner, there is a limitation in that a light pulse cannot be applied to one or more horizontal electrodes at a time for a given vertical electrode, and therefore, the horizontal electrodes must be driven at different times.

Therefore, in order to compose each sub-screen, it is necessary to scan all the horizontal electrodes, and each cell can maintain the discharge only for a time reduced by the scanning time from the time allocated to the average sub-screen.

The time required for scanning increases as the number of horizontal electrodes increases, and since discharge cannot be maintained during this time, it becomes a factor that causes a decrease in brightness and contrast of the PDP, and thus the time required for scanning needs to be reduced as much as possible.

In addition, since the difference in discharge time between the upper bits and the lower bits is large and the secondary screen is sequentially configured in the sub-screen configuration, a flicker phenomenon occurs due to the difference in the discharge time.

In order to reduce the flickering, it is necessary to configure the upper bit subscreen with a long discharge time and the lower bit subscreen with a short discharge time in an appropriate order.

FIG. 1 illustrates a typical three-electrode surface discharge AC PDP cell structure, in which a partition 10 has a first insulating substrate 1 and a second insulating substrate 2 in parallel. The row electrodes 3 consist of two scan electrodes and two common electrodes and are arranged in parallel with each other on the insulating layer 1.

The data electrodes 4 are arranged parallel to each other under the insulating layer 2 to form a matrix with the row electrodes 3, and the insulating layers 5 and 6 are each a row electrode 3. The electrode is covered by overheating electrode 4 to protect the electrode. Since the electrode is covered with an insulating film, the discharge is soon extinguished when a direct current voltage is applied between the electrodes. In the case of an AC PDP having such an electrode structure, an AC voltage having an inverted polarity must be applied between electrodes in order to maintain discharge.

In addition, the protective film 7 is covered on the insulating film 5, which not only protects the insulating film and extends its life, but also increases the emission efficiency of secondary electrons and reduces the change in discharge characteristics due to oxide contamination of the refractory metal. MgO thin film is mainly used to give.

In addition, the fluorescent layer 9 is coated on the insulating layer 6, is excited by the ultraviolet rays generated by the discharge to generate red, green, blue (RGB) visible light, the discharge region 8 is discharged It is the space of the cell to proceed and is mainly filled with Ar and Xe mixed gas to improve the UV emission efficiency.

2 shows an electrode arrangement diagram of a three-electrode surface discharge AC PDP, in which each cell 11 is configured at a point where the row electrodes and the column electrodes cross at right angles to each other, and the row electrodes are mainly used for scanning the screen. It consists of the S1 ~ Sm scan electrode group and the C1 ~ Cm common electrode group mainly used to maintain the discharge, the column electrodes are mainly used for data input.

The sealing region 12 is used to maintain the vacuum of the entire PDP, and inserts an insulator partition between the insulating layers 1 and 2 and seals the edge of the PDP with an adhesive.

3 illustrates a typical driving waveform for driving an AC PDP. The sustain pulses for maintaining the discharge of the cell are applied to the C1 to Cm common electrodes, and the pulses and shapes of the common electrodes are applied to the S1 to Sm scan electrodes. Apply the same but different sustain pulses.

In addition, scan pulses used for scanning the screen and erase pulses for stopping the discharge of the discharged cells are additionally input to each of the scan electrodes to control on and off of the cells.

In addition, the data pulses synchronized with the scan pulses input to the scan electrodes are input to the D1 to Dn data electrodes to obtain a write pulse.

If the cells S1 and D1 are to be discharged, a positive data pulse is inputted to D1 and a scan pulse is inputted to S1 in synchronization with the data pulses to discharge the voltage between the S1 and D1 electrodes. The discharge is generated above the threshold voltage necessary to cause the discharge.

This state is maintained until the next erase pulse is applied by the electric field generated by the charged particles charged to the insulating film by the discharge and the electric field generated by the sustain pulses of S1 and C1, and the erase pulse having a lower amplitude than the scan pulse. When is applied, a small discharge occurs that is insufficient for the sum of the electric field by the charged particles and the electric field by the erasing pulse to sustain the discharge, and the discharge disappears when the next sustain pulse is applied.

To summarize the role of each electrode, scan electrodes serve as sustain and screen scan, while common electrodes perform only a sustain function, and data electrodes are responsible for data input for screen configuration.

FIG. 4 illustrates a sub-screen scanning method for implementing 256 gray scales based on the driving waveform shown in FIG. 3. One screen includes eight sub-screens, and the scan electrodes of the panel according to the temporal order of the horizontal axis. In the (vertical axis), data is sequentially input from the data electrodes from the first scan electrode to the last scan electrode (m-th scan electrode) and sequentially from the MSB to the LSB.

The write pulse is applied to the selected scan electrode on the left diagonal line of each sub-screen, and the erase pulse is applied on the right diagonal line. Here, since two or more light pulses cannot be applied to one pixel at the same time, the time of each sub-screen is constant as T. The sustain pulse is regularly applied to the common electrode separately from the waveform applied to the scan electrode as shown in FIGS. 2 and 3.

On the other hand, in the case of the non-interlacing method, the image signal is sequentially input from the outside of the RGB 8 bit image signal of each pixel from the upper left to the lower right of the panel.

However, due to the characteristics of the PDP pixel, it is difficult to scan it directly to the panel, and thus a memory for storing an image signal is required.

The memory reference address control method according to the scanning scheme is generally implemented in three forms as follows.

First, after rearranging the input image signals in the order of output to the panel, they are stored in order in the memory, and the image signals are output while increasing the reference address of the memory sequentially when outputting to the panel. In this case, the structure of controlling the storage of the video signals in the memory becomes complicated because the video signals must be arranged in a pre-output order before the video signals are stored in the memory. Panel output control of the signal is simplified.

Secondly, video signals are stored in memory in the order of input, and the memory addresses are referred to according to the driving order of the scanning method when outputting to the panel. In contrast to the first method, the method of controlling the storage of the video signal in the memory is simple, while the output control structure of the video signal in the memory is complicated.

Third: When the first and second methods are mixed, some of the video signals are rearranged and stored in the memory when the video signals are stored in the memory, and the memory addresses are partially referred to according to the scanning method when outputting to the panel. . In this case, both video signal storage control and video signal output control in the memory can be complicated, but there is an advantage of optimizing memory control.

Although these three memory control methods have been described using a sub-screen scanning method as an example, the basic structure may be applied to other scanning methods.

However, the conventional AC PDP driving apparatus for driving a PDP by such a memory control method has a problem in that a driving circuit having a different structure is required according to the characteristics of the scanning method, that is, the various scanning methods.

Therefore, the present invention has been proposed to solve the above problems of the prior art, by referencing the address of the memory required for input and output image information to the memory using a ROM (Read Only Memory) or PLA (Programmable Logic Array) Firstly, the memory can be controlled regardless of the scanning method, and secondly, the ROM or PLA having a memory reference address can be changed without having a different driving circuit according to various scanning methods. The goal is to allow the testing of different injection methods in the furnace.

The technical means of the present invention for achieving this object is the data arranging means for rearranging the video signal RGB in order from the upper bit to the lower bit in the order of arrangement of the pixels of the PDP, and the data arranging means Video signal storage means for storing the stored data, video signal address storage means for storing the address of the video signal stored in the video signal storage means in a reference order in a temporal order according to a scanning method, and the video signal address storage means. And a control means for referring to the address of the stored video signal according to a scanning method and outputting the corresponding video signal to the PDP.

Hereinafter, the present invention will be described with reference to the accompanying drawings.

FIG. 5 is a block diagram of the AC PDP driving apparatus according to the present invention, which is a schematic block diagram from the input of an image signal to a panel using a third method of the above three memory control methods.

As shown, the data array register 102 is implemented by wired logic to rearrange the image signal RGB in order from the upper bit to the lower bit in the arrangement order of the pixels of the PDP 101, A memory 103 for storing data arranged by the data array register 102 and a memory address ROM for storing the address of the data stored in the memory 103 in a memory reference order of a temporal order according to a scanning method ( Read Only Memory 104 and a controller 105 for referencing a memory address stored in the memory address ROM 104 according to a scanning method so that a corresponding video signal is output to the PDP 101. .

In the figure, reference numeral 106 denotes a ROM address counter.

The memory address ROM 104 according to the present invention is not possible in one embodiment of the video signal address storage means for storing the address of the video signal stored in the memory 103, it can be used alternatively to PLA.

When described with reference to Figures 4 to 9 attached to the operation and effect of the present invention configured as described above are as follows.

First, the arrangement of the image signals in the memory 103 varies slightly depending on the scanning method, but as shown in FIG. 6, the upper bits MSB in the memory 103 are arranged in the arrangement order of the pixels of the PDP 101. In turn, it stores the lower bits (LSB).

In the case of the sub-screen scanning method when outputting an image signal to the PDP 101, the output signal is output in the order of the first scan electrode to the last scan electrode (m-th scan electrode) as shown in the driving waveform of FIG. The image signal is sequentially output to the data electrode of the PDP 101.

Therefore, in this case, the memory reference address shown in FIG. 6 is sequentially increased, and the corresponding video signal is output to the PDP 101.

FIG. 7 illustrates a data map of the memory address ROM 104 storing the memory reference address of FIG. 6, in which the data storage order of the memory address ROM 104 is a temporal order of the memory reference address. When the video signal is output to the PDP 101, the reference address of the memory address ROM 104 is sequentially increased to output the addresses of the stored memory 103 to the memory control circuits one by one in accordance with an external clock. .

8 illustrates a scanning method for a high resolution AC PDP, in which the vertical axis represents a scan electrode and the horizontal axis represents a scanning method over time.

As shown in FIG. 4, since the driving electrodes are not sequentially selected from the first to the last, unlike the conventional sub-screen scanning method of FIG. 4, the image signals in the memory 103 are not stored in the output order of the PDP 101. If not, the memory address stored in the memory address ROM 104 will be frequently referred to at output.

FIG. 9 shows a memory address arrangement in the memory address ROM 104 which stores a memory reference address necessary for outputting the video signal to the PDP 101 when it is assumed that the storage of the video signal in the memory 103 is the same as that of FIG. As a result, the data storage order of the memory address ROM 104 is in the order of memory reference addresses in a chronological order.

As described above, according to the present invention, the memory address required for input / output of image information to the memory can be referred to using ROM or PLA, so that the memory can be controlled regardless of the characteristics of the scanning method in one general-purpose driving apparatus. In addition, it is effective to compare and analyze the efficiency of each other by applying various scanning methods evenly.

1 is a structural diagram of a typical three-electrode surface discharge AC PDP cell.

FIG. 2 is a layout view of electrodes of the three-electrode surface discharge AC PDP shown in FIG.

3 is a drive waveform diagram using an electrode arrangement of the three-electrode surface discharge AC PDP shown in FIG. 2;

4 is a sub-screen scanning method using the driving waveform shown in FIG.

5 is a block diagram of an AC PDP driving apparatus according to the present invention;

FIG. 6 is a video signal arrangement diagram in the memory shown in FIG. 5; FIG.

FIG. 7 is a memory reference address arrangement diagram according to the sub-screen scanning scheme in the memory address ROM shown in FIG. 5; FIG.

8 is a scanning scheme for high resolution AC PDP.

9 is a memory address arrangement diagram in a memory address ROM according to the video signal arrangement shown in FIG.

*** Explanation of symbols for the main parts of the drawing ***

101: Plasma Display Panel (PDP) 102: data array register

103: memory 104: memory address ROM

105: controller

Claims (2)

Data arranging means for rearranging the image signal RGB in order from the upper bit to the lower bit in the arrangement order of the pixels of the PDP; Image signal storing means for storing data arranged by the data arranging means; Image signal address storage means for storing the address of the image signal stored in the image signal storage means in a reference order of a temporal order according to a scanning method; And a control means for referring to the address of the video signal stored in the video signal address storage means according to a scanning method and outputting the corresponding video signal to the PDP. The method of claim 1, The video signal address storage means is a CD PD drive device, characterized in that configured by selecting any one of a ROM (PLA) and a PLA (PLA).

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